Performance enhancement of 8-bit DIVIDER

Submitted in partial fulfillment of the requirements for the degree of

Bachelor of Technology
in
Electronics & Communication Engineering
by

Sagar Srivastava - 2100970310134

Shashank Singh - 2100970310143
Shweta Yadav - 2100970310154

Under the Guidance of

Mr. Amit Gupta

Department of Electronics and Communication Engineering

(B. Tech ECE – Accredited by NBA),
Galgotias College of Engineering and Technology, Greater Noida
(Affiliated to DR.A.P. J Abdul Kalam Technical University, Lucknow)

January 2024
 DECLARATION

We hereby declare that the report entitled “Performance enhancement of 8-bit

DIVIDER” submitted by us, for the award of the degree of Bachelor of Technology
in Electronics and Communication Engineering to Galgotias College of Engineering
and Technology, Greater Noida affiliated to Dr. A.P.J. Abdul Kalam Technical
University, Lucknow is a record of bonafide work carried out by us under the
supervision of Mr. Amit Gupta.

We further declare that the work reported in this report has not been submitted and
will not be submitted, either in part or in full, for the award of any other degree or
diploma in this institute or any other institute or university.

Place: Greater Noida

Date: Signature of the Candidates

2
 CERTIFICATE

This is to certify that the report entitled “Performance enhancement of 8-bit

DIVIDER” submitted by Sagar Srivastava, Shashank Singh and Shweta Yadav from
the Department of Electronics and Communication Engineering, Galgotias College of
Engineering and Technology, Greater Noida affiliated to DR. A.P.J. Abdul Kalam
Technical University (AKTU), Lucknow, for the award of the degree of Bachelor of
Technology in Electronics and Communication Engineering, is a record of bona fide
work carried out by him under my supervision, as per AKTU code of academic and
research ethics.

The contents of this report have not been submitted and will not be submitted, either
in part or in full, for the award of any other degree or diploma in this institute or any
other institute or university. The thesis fulfils the requirements and regulations of the
University and in my opinion meets the necessary standards for submission.

Place: Greater Noida

Date: Signature of the Candidates

The report is satisfactory/unsatisfactory

Approved by

Head of the Department

3
 CHAPTER 1
Introduction

One of the four basic arithmetic operations is division, in addition to addition,

subtraction, and multiplication. While addition and subtraction are straightforward,
multiplication can be made simple, and division is a much more complicated and
computationally intensive operation. However, it cannot be underemphasized in
importance since it plays a fundamental role in several applications in computation,
digital systems, and signal processing.

Division in digital circuits necessitates certain specialized hardware implementations

because division algorithms contain several sequences of steps to compare, subtract,
and then shift, for instance, taking quite a period if not done properly. Common and
widely deployed 8-bit divider circuitry is specifically seen in any systems that happen
to be under constraint of the size, or the power, or even the compute resources.

An 8-bit divider is a digital circuit, for the purpose of performing division operations
on two 8-bit binary numbers. Here, both the dividend and the divisor are represented
using 8 bits, which limits their range to binary values between 0 and 255. The result
of this division is a quotient representing how many times the divisor fits into the
dividend and often a remainder representing any leftover value after the operation.
These are also represented in binary format.

The main advantage of the 8-bit divider is its balance of precision, resource usage,
and versatility. With a resolution of 8 bits, the circuit is able to manage a wide range
of values and is therefore useful in embedded systems and low-power applications
where the computational complexity needs to be minimized. Also, its compact design
makes it an ideal candidate for use in hardware-limited environments, such as
microcontrollers or small-scale digital processors.

Division operations carried out by an 8-bit divider occur in nearly all domains. For
example, in embedded systems, division is often applied in control systems,
normalization of sensor data, or in resource allocation tasks. In DSP, division helps in

4
doing complex computations like FFT, image processing, and digital filtering.
Furthermore, communication systems also require division to implement error
detection algorithms like CRC in ensuring data integrity while being transmitted.

Despite its utility, designing an 8-bit divider comes with challenges. Division is
inherently slower compared to addition or multiplication, necessitating techniques to
improve speed and efficiency. Minimizing power consumption is another critical goal,
particularly for portable and battery-powered devices. Finally, achieving area
efficiency without sacrificing performance is essential for reducing production costs
and improving scalability.

1.1. 8 Bit-Divider
Divider is the most commonly used circuit in digital devices. Division is one of the
arithmetic operations performed by divider in the various analog and digital
circuits. High speed, low power consumption, regularity of layout and therefore less
area required or even combination of them in one divider are the design targets in that
way making them suitable for various VLSI implementations. Division is one of the
basic functions used in digital signal processing. same as addition, subtraction,
multiplication.

To reduce leakage current so many techniques are available sleep transistor technique,
forced stack technique, Sleepy stack technique and the latest technique named as
GALEOR technique. These techniques listed above reduces the leakage by stacking
leakage path using the off transistors. In GALEOR technique the gated leakage
transistors are used in between pull-up and pull-down network. Here, we use Galeor
Technique to reduce leakage current of 8-bit parallel divider circuit. In this Galeor
technique, two gated leakage transistors (a n-type and a p-type) within the logic gate
for which the gate terminal of each gated leakage transistor (GLTs) is connected to
the drain of the other transistor. The operation of division in parallel divider is done
by means of shifting and subtraction.

Suppose we want to divide 135 by 13. So, at every step, shift dividend left and
compare its five MSB with current divisor if divisor is larger, shift 0 as the next bit of
the quotient if divisor is smaller, subtract to get new dividend and shift 1 as the next

5
bit of the quotient after the completion of the process at the end we get 4-bit quotient
which is 10 and 5-bit remainder which is 5 in dividend register. Binary division is
done in the same way. The proposed 8-bit binary parallel divider using GALEOR
technique using 45nm is embedded by using the Tanner EDA tool.

1.2. WORKING OF 8-Bit Divider

The 8-bit divider is a digital circuit that performs binary division operations, meaning
it produces an output with both a quotient and a remainder. This is a critical building
block within digital systems, which is often used in arithmetic operations that are
found within the processors, digital signal processing, and communication systems.
The 8-bit divider can be implemented either in an iterative or combinational manner,
optimal for different design goals: speed, power, or area efficiency.

Key Algorithms Used in Divider Design

The design of an 8-bit divider relies on various algorithms, each suited to different
performance and resource constraints:
1.2.1. Restoring Division:
Restoring division algorithm, the restoring division algorithm is a basis for
implementing digital circuitry for the binary division method. This procedure is based
on the long-division process for decimal arithmetic. It is a natural and easily
understandable procedure as it iterates through comparisons and subtractions and
shifting the binary numbers for the derivation of the quotient and remainder. It is
characterized by the restoring step, where a subtraction results in a negative result,
and it reverts back to its original value.

Restoring division relies on basic arithmetic operations like shifting, comparison, and
subtraction to determine whether the divisor can "fit" into a portion of the dividend.
The process is bit-by-bit beginning with MSBs of the dividend. If the subtraction
returns a positive or zero remainder, it means the divisor fits within the chosen
amount of the dividend. The quotient bit is set to 1, and if it returns a negative
remainder, it means the number has been too large, and the original number is
restored by setting the quotient bit to 0.

The restoring division algorithm is an intuitive and reliable method for digital circuits

6
to use in binary division. Although not as fast as the advanced algorithms, its
simplicity and accuracy give it a vital place in applications. The step-by-step restoring
division also presents an excellent structure for understanding the way digital division
circuits work and is the base for innovations of high-speed and energy-efficient
designs.

1.2.2. Non-Restoring Division

The non-restoring division algorithm is an enhanced binary division method

developed for digital circuits, designed to eliminate the inefficiency of restoring
division algorithms in performance. Non-restoring division does not incur an extra
step in restoring since it employs an alternative way to handle negative remainders,
eliminating redundant operations when the remainder happens to be negative. It will,
therefore be faster and efficient for large numbers.

The non-restoring division algorithm improves upon restoring division by avoiding

the restoration step. In restoring division, when a subtraction results in a negative
remainder, the algorithm has to undo the subtraction (restoring the original
remainder). In non-restoring division, the algorithm handles the negative result
differently without needing to reverse the subtraction. This is achieved by deciding
what to do, based on the result of subtraction: if negative, instead of restoring the
original value, the algorithm uses a complementary operation.

Non-restoring division usually shift and subtract in such a way as to ensure the
quotient and remainder are computed correctly without restoring the previous value.
The fundamental difference is in how to handle negative results: it doesn't restore the
value and try it again but rather adjusts its strategy to move on effectively.

The non-restoring division algorithm is an improvement over the restoring division

algorithm because it offers faster and more efficient performance without restoring
the dividend in case of a negative remainder. It is, therefore, preferred in many high-
performance digital systems and applications requiring binary division. Although it
has some disadvantages in terms of design complexity and precision in certain
contexts, its speed and efficiency make it suitable for use in processors, DSP systems,
and other performance-critical environments.

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1.2.3. Combinational Approaches (Parallel or Array Dividers)

Combinational approaches to division, such as parallel or array dividers, are designed

for the purpose of performing division with a high efficiency through parallelism.
They are used more in digital circuits to perform divisions at high speeds, rather than
sequential methods such as restoring or non-restoring division, which take multiple
cycles to complete. Combinational dividers are targeted to reduce overall latency and
increase throughput by doing division in parallel. This is particularly important for
applications where fast, real-time division is required, such as in processors, digital
signal processors (DSPs), and high-performance computing systems.

In a combinational divider, using the set of logic gates implement division without
employing sequential steps, meaning no specific number of cycles will be required at
any bit clocking. To accomplish this method of using multiple logics that complete
certain parts in parallel, leads to faster time computability: that is quite the opposite;
sequential approaches could get very slowly processed.

There are variations of combinational dividers. The most conventional methods are
called parallel dividers and array dividers. It is applied from both the views, in a way
to facilitate high-speed division, and uses parallelism, implementing efficiently in
terms of logic circuits.

Combinational dividers, including parallel and array dividers, are critical circuit
blocks in high-speed digital circuits where fast division operations are required. On
leveraging the level of parallelism at hand, they significantly reduce the computation
time by more than an order compared to traditional sequential methods of division.
Although they provide major benefits in terms of speed, they have challenges like
higher power consumption, complexity in their design, and additional scaling
problems. Combinational dividers are widely used in applications demanding high-
performance division, such as digital signal processing, microprocessors, and
cryptographic systems. Its high performance in division operation makes it the key
technology of modern digital systems.

1.3. SYSTEM MODEL of 8-Bit Divider

The 8-bit divider system can be represented by various elements like registers, logic

8
units, control signals, and arithmetic circuits. In this system, we have a division
implemented by repeated shifting, subtracting, and comparing. The divider takes two
8-bit binary numbers to produce an 8-bit quotient and a remainder. The system model
gives a clear illustration of how the divider works, with well-defined interconnections
of various parts of the circuit, indicating the procedure step by step as the division
process works.

Below is a detailed breakdown of the system model for an 8-bit divider:

1.3.1. Inputs and Outputs

 Inputs:

Dividend (D): An 8-bit binary number to be divided.

Divisor (V): An 8-bit binary number by which the dividend is divided.

 Outputs:

Quotient (Q): The 8-bit result of the division.

Remainder (R): The remaining value after the division, stored as a 7-bit value
(since the remainder cannot exceed the divisor).

1.3.2. Control Unit

It is the control unit that coordinates all the operations that take place within the
divider. It controls all the following processes:

 Shifting: Moving the bits of the dividend to the left during the division
process.

 Subtraction: Subtracting the divisor from the current value of the dividend
whenever necessary.

 Comparing: The divisor is compared with the shifted dividend to know

whether subtraction is possible or not.

 Quotient Update: A bit is set in the quotient based on the result of the
comparison.

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The control unit supplies the following signals:

 Shift Enable: It allows the dividend to shift left.

 Subtract Enable: It enables subtraction when the divisor fits in the dividend.

 Quotient Enable: It updates the quotient based on subtraction.

1.3.3. Arithmetic Logic Unit (ALU)

The main arithmetic operations performed by the ALU during division are
subtraction, comparison, and shifts. These operations include:

 Subtraction: The ALU carries out the binary subtraction of the divisor from
the current value of the dividend.

 Compare: The ALU compares the divisor with the shifted dividend and
outputs a flag showing whether subtraction should take place.

 Shift: The ALU shifts the dividend to the left for the next iteration, adjusting
the remainder accordingly.

1.3.4. Registers

The system uses a number of registers to store the dividend, divisor, quotient, and
remainder throughout the division process:

 Dividend Register (D): This is where the 8-bit dividend that will be divided is
stored. It is also used to hold the intermediate remainders.

 Divisor Register (V): Accumulates the 8-bit divisor.

 Quotient Register (Q): This is where the quotient bits are stored that are
calculated in the process of division. The quotient is constructed from LSB to
MSB.

 Remainder Register (R): Holds the quotient and final remainder. The initial
remainder is a copy of the dividend and is over-written as division
progresses.

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1.3.5. Division Process (Steps of Division)

The 8-bit divider generally works in the following steps in parallel or sequentially:

 Step 1: Initialization

The dividend D is loaded into the Dividend Register.

The divisor V is loaded into the Divisor Register.

The Quotient Register Q is initialized to zero.

 Step 2: Comparison and Subtraction

The Control Unit allows the Comparison Unit to check whether the divisor V can
be subtracted from the dividend D.

The ALU compares the MSBs of the dividend and the divisor

If the divisor is smaller than or equal to the dividend, then subtract the divisor
from the dividend.

If the divisor is greater than the dividend, nothing happens

 Step 3: Shifting

After performing the subtraction for every comparison, the Dividend Register
shifts one position left so it gets ready for the next cycle.

Each step of division is equivalent to a subtraction step and decreases the dividend
gradually.

 Step 4: Incrementing the Quotient

Dependent upon the outcome of the subtraction check (if subtraction took place or
not), a bit is set in the Q register.

If subtraction was performed the quotient bit corresponding to that step is set to
'1'.

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 If no subtraction took place, then the quotient bit is set to '0'.

 Step 5: Iteration

The remaining steps 2 through 4 are repeated, and the same process is performed
until all the bits of the dividend have been processed (there are typically eight
steps for an 8-bit divider).

Finally, when all these steps have completed, the result of the remainder register,
R, is the remainder of division, and that of the quotient register, Q, is the quotient.

1.3.6. Optimizations (GALEOR, Power-Efficient Techniques)

GALEOR, an abbreviation for gated leakage transistor, can be used to minimize

leakage current in the divider's logic gates. GALEOR uses transistors of gated leakage
located between the pull-up and the pull-down network of the logic gates. Leakage
current is thereby avoided when the divider is idle because the transistors turn off.
This combination of techniques helps considerably reduce the power consumption in
the 8-bit divider circuit so that it is more suitable for low power applications or in
portable devices and embedded systems.

The GALEOR technique presents an idealistic and effective method to leakage

current reduction in an 8-bit divider circuit. It is placed between the pull-up network
and the pull-down network, which are gated leakage transistors. Therefore, it
selectively turns off leakage paths when the circuit does not act, so it reduces power
consumption without performance degradation. Its use was highly recommended in
different applications such as embedded systems, IoT devices, and mobile electronics
in a controlled energy efficiency environment. Indeed, the integration of GALEOR
with the design of the 8-bit divider brings in further energy efficiency, scalability, and
reliability within the circuit design, suitable for modern digital systems demanding
lower power operation.
1.4. APPLICATIONS of 8-Bit Divider

8-bit dividers are also considered basic and commonly found in most digital systems
mainly when divisions are indispensable to ensure the performance of such
applications. Division operations are efficiently carried out since an 8-bit requires

12
handling numbers whose lengths are within the byte size (0 to 255 in unsigned and -
128 to 127 in signed). This optimization includes performance, power consumption,
and resource utilization during the design and implementation of efficient 8-bit
dividers for their use across various fields in digital electronics, embedded systems,
and computational hardware.

Some of the primary applications where 8-bit dividers are employed, examining their
role, significance, and benefits:

1.4.1. Microprocessors and Arithmetic Logic Units (ALUs)

Microprocessors and Arithmetic Logic Units (ALUs) are the most common
applications of 8-bit dividers. The processors are fast arithmetic operation-dependent,
which means they use the processors for performing simple arithmetic operations to
complex calculations. Since many 8-bit systems, including microcontrollers and
legacy processors, operate on byte-sized data, 8-bit dividers are used for the efficient
division of smaller numbers.

The division operation needs to be executed promptly in ALUs because of several

algorithms that it performs, including control loops, data manipulation, and
input/output processing. Therefore, an 8-bit divider is integrated into the ALU so that
the integer division is done without the need for extra clock cycles to improve the
processor's throughput.

ALUs usually perform both signed and unsigned integers. The 8-bit divider can
support both, thereby ensuring flexibility in operations.

1.4.2. Embedded Systems and Controllers

Embedded systems are specialized computing systems designed to perform specific

tasks. In many embedded applications, processors must execute a wide variety of
operations, including division, while maintaining real-time responsiveness. Some
common examples of embedded systems include:
 Microcontrollers in consumer electronics, automotive systems, industrial
controllers, and more.
 Sensors and actuators that need computational processing, such as division

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 for sensor data analysis.
The 8-bit divider ensures division operations do not bottleneck the system, and
because the embedded processor can perform other tasks concurrently, there is no
delay. For embedded systems operating in resource-constrained environments, the
compact nature of an 8-bit divider reduces area and power usage within the processor.
1.4.3. Digital Signal Processing (DSP)

Digital Signal Processing (DSP) manipulates signals to perform operations like

filtering, compression, and transformation. Most DSP applications require division to
normalize data, scale values, or divide values across multiple channels.

Applications of dividers like audio or image processing use 8-bit sometimes for
scaling the signal levels to standard range. For instance, normalization of sound
amplitude in playing an audio or dividing pixel values in an image for video
processing.

Fast Fourier Transform (FFT) is a DSP algorithm, which often involves division
operations to calculate frequency components. 8-bit dividers help these operations
occur efficiently.

Efficient 8-bit dividers enable real-time signal manipulation, which is critical in

applications such as speech recognition, radar systems, or audio/video
encoding/decoding. In battery-powered DSP devices, the low power consumption of
8-bit dividers is crucial for extending operation time.

1.4.4. Cryptographic Systems

Division plays an important role in many encryption and decryption algorithms in

cryptography, especially in modular arithmetic or in key exchange. Most of the
cryptographic algorithms are complex in nature, like RSA and ECC, and thus efficient
division is needed.

Cryptographic hardware accelerators utilize 8-bit dividers as part of their modular

arithmetic unit in order to enhance the encryption and decryption processes. In ECC,
division is fundamental to key exchange and digital signatures. Hardware accelerators
are optimized with 8-bit dividers.

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1.4.5. Digital Video and Image Processing

The following mathematical operations such as scaling, filtering, and transformation

of pixel data are sometimes needed in video and image processing. Division is applied
in brightening adjustments, contrast scaling, and image rescaling.

When one resizes or transforms images, pixel values are often divided by a scaling
factor. Adjusting brightness or contrast, for instance, involves multiplying or dividing
pixel values by constants.

Division should be done as fast as possible to make video playback or image

manipulation smooth. The 8-bit divider is fast in processing image data. Video and
image processing in hardware often have to be resource-friendly to meet performance
and power constraints in mobile devices or low-cost consumer electronics.

1.5. GALEOR Technique in 8-Bit Divider Design

In modern Very Large-Scale Integration designs, power dissipation is increasingly

becoming a paramount concern, notably for battery- operated devices and systems
such as mobile phones and laptops, also embedded systems, where the reduced power
consumption dictates the efficiency needed. Leakage current of transistors in logic
gates is an indispensable part of dealing with power saving in digital circuits. Leakage
current has been defined in this context when transistors are in a logic "off" state. One
of the potent techniques to mitigate this leakage current is GALEOR (Gated Leakage
Transistor).

1.5.1. Leakage Current in CMOS Circuits

Leakage current is an inherent component of modern CMOS (Complementary Metal-

Oxide-Semiconductor) circuits, especially since transistors are being made smaller
and smaller. Even though a transistor might not be in the process of switching
between on and off, there is always a small amount of current going through it. This
leakage current is called subthreshold leakage because the gate voltage is not strictly
zero for an "off" transistor, leaving a little opportunity for current flow from source to
drain. Moreover, leakage from a reverse-biased junction can be added to contribute
more to this wastage.

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In high-performance circuits such as 8-bit dividers, leakage current can be significant,
especially when the circuit is idle or not in use. This creates a problem for low-power
applications, where every bit of power savings counts. Techniques like GALEOR
come into play here.

1.5.2. Overview of GALEOR Technique

GALEOR stands for Gated Leakage Transistor, a technique used to reduce leakage
current in CMOS logic gates. The main idea behind GALEOR is to place gated
leakage transistors (GLTs) in between the pull-up and pull-down networks of the
logic gates. These GLTs are controlled by a gate signal that determines whether or not
they conduct current.

 Pull-up network: It is a network of p-type transistors (usually PMOS) that

pull the output voltage high to VDD.

 Pull-down network: It is a network of n-type transistors (usually NMOS)

that pull the output voltage low to ground.

The GLTs in GALEOR are configured to break the leakage path across the pull-up
and pull-down networks. In fact, the GLTs are turned off when the logic gate is idle or
not in an active use of a computation that would otherwise permit leakage current
flowing through the circuit.

1.5.3. Working Principle of GALEOR

 Active State: If the logic gate is active and in the operation phase, say for
instance the 8-bit divider performing its operation of division, the GLTs are
ON. Here, the gate behaves as any normal CMOS logic gate does: the current
flows where necessary to carry out the operation.

 Idle State: During the time a logic gate is idle so it is not involved in active
computation, the GLTs are disabled. Therefore, the pull-up and pull-down
networks are disengaged from each other. In this way, a leakage current
cannot flow through the transistors; even if they are in the off state.

In a nutshell, the GALEOR technique enables dynamic control of the leakage current

16
by unidirectional enabling and disabling the leakage path through the transistors.

1.5.4. Benefits of GALEOR in the Design of 8-Bit Divider

The GALEOR-based 8-bit divider circuit consumes significantly low power. Its usage
in low power applications, including embedded processors, IoT systems, and portable
devices, is necessary. The main advantages are discussed as follows:

 Leakage Current Minimization:

Since gated leakage transistors block the leakage path when the gate is not active,
this system will have lower static power consumption. It is critical for circuits in
idle or low-power states.

 Enhanced Power Efficiency

The GALEOR technique guarantees that the divider circuit does not waste power
unnecessarily when it is not actively involved in dividing numbers or
computation. This makes it suitable for systems with critical power efficiency,
such as mobile devices, sensors, and wearables. It has a minimal impact on
performance.

One of the major advantages of GALEOR is that it does not introduce any
significant delays or impact the divider's speed. Since the gated leakage transistors
are only activated during idle states, the divider's performance is not significantly
compromised during active division operations.

 Scalability:

The size of the 8-bit divider or any logic circuit grows; hence, GALEOR remains
effective if we need a 16-bit or 32-bit divider. The approach scales well for larger
designs where leakage currents tend to increase due to the greater number of
transistors.

 Less Temperature Sensitivity:

The leakage currents might change with temperature. In a circuit, these might
affect reliability, hence this design has been kept temperature-variation-robust as

17
 GALEOR minimizes the sensitivity to the changes of temperature and increases
robustness.

 Applying GALEOR on an 8-bit Divider

An 8-bit parallel divider might implement the GALEOR technique through using
gated leakage transistors on all critical logic gates which might be utilized in the
divider to do the shifting, subtraction, and comparisons.

For instance, during the shifting operation, when the dividend is shifted left to
prepare for the next step in division, the GALEOR technique ensures that no
leakage current flows through the shift register when it is idle.

Similarly, during subtraction, the leakage path can be cut off by turning off GLTs
in the subtraction logic when they are not actively involved in the operation of
subtracting the divisor from the dividend remainder.

Applying GALEOR to the ALU and the entire control circuitry of the divider will
reduce the leakage currents associated with the divider circuit. In summary, power
leakage of the 8-bit divider circuit is minimized.

1.6. CHALLENGES

The design of an 8-bit divider is an integral part of many digital systems, ranging
from microprocessors to embedded systems and digital signal processors. Yet, 8-bit
divider circuits face various challenges in terms of achieving efficiency and reliability
in their design, primarily with regard to very high-speed operation, low power
consumption, and the scalability of larger bit-width dividers. Key Challenges with
Design of 8-bit Divider In the following section, we will elaborate on the major
challenges in designing an 8-bit divider.

Designing an 8-bit divider circuit is a complex task and requires solving issues related
to speed, power consumption, area, complexity, and accuracy. It is optimized when
the designer is well aware of the division algorithm, the hardware involved, and the
constraints imposed by the application. In the modern design era, techniques like
GALEOR for power reduction and optimized arithmetic algorithms for speed are
essential in ensuring that the 8-bit dividers function efficiently. Balance these various

18
types of challenges against performance and reliability is central to developing an
effective and scalable 8-bit divider.

1.6.1. Complexity of Division Algorithms

An 8-bit divider, while a division algorithm is fast and accurate, requires careful
attention to several factors:

The critical problem is the design of an efficient method to subtract the divisor from
the dividend by shifting the dividend left to be ready for the next iteration. It demands
designing an efficient ALU that can execute multiple bit-wise operations
simultaneously. The ALU must perform the subtraction of two binary numbers,
shifting of numbers, and comparison operation in parallel to maintain the speed of the
divider high.

The design of the division algorithm itself may vary. Non-restoring division is a
common one where subtraction is performed conditionally based on the sign of the
result. More advanced algorithms, such as restoring division or SRT division, which
is a radix-4 division algorithm, may be used for faster division but have their own
complexity in terms of hardware requirements and clock cycles.

Iterative Process: A division requires several iterations of subtractions and shifting.

While the number of iterations grows when the bit width increases (as in the case of a
16-bit or 32-bit divider), so does the total complexity of the design.

1.6.2. Speed and Timing Constraints

The divider circuit for an 8-bit processor must fulfill the following requirements
regarding timing:

Clock Cycle Efficiency: To increase the speed of the division operation, the divider
must minimize the number of clock cycles it takes to perform a division. This may be
particularly challenging since the complexity of the division algorithm and the
number of necessary shifts and subtractions increase with the bit-width.

Parallelism: The parallelization of parts of the division process can lead to higher
speeds. For example, parallel subtraction and shift operations reduce the number of

19
sequential operations and therefore reduce the execution time. However, it requires
synchronization, which is more complex than a nonparallel design.

Critical Path Delay: The longest delay in a digital circuit determines the maximum
clock speed. In an 8-bit divider, critical path operations include comparison,
subtraction, and shifting. Optimizing the critical path is important to ensure that the
divider operates at the desired clock speed, especially in high-speed applications.

1.6.3. Power Consumption

Some of the challenges with 8-bit divider design regarding power consumption
include:

Dynamic Power Consumption: The primary cause of dynamic power consumption

is the switching activity of transistors. In a divider, there are many gates and registers
that switch their state with each operation and dissipate power. Optimization of logic
gates and reducing the number of switches can help lower dynamic power
consumption.

Leakage Power Dissipation: Leakage current is another significant problem

nowadays in the modern CMOS circuits. Even when a logic gate of a digital circuit is
not actively switching, a small number of current flows through it, which results in the
waste of power. Leakage can accumulate when there are many gates involved in the
process of division in an 8-bit divider, and contribute in huge proportions to the power
dissipation.

Techniques such as GALEOR (Gated Leakage Transistor) can help reduce leakage
power by cutting off the leakage path when the divider is idle. Leakage power
consumption can be dramatically reduced by turning off parts of the circuit that are
not in use.

Power-Performance Trade-Off: Optimizing for power efficiency may sometimes

compromise performance. A designer is always faced with the decision of whether to
design a low-power divider that operates slowly or a high-performance divider that
consumes more power. Finding the appropriate balance between power consumption
and performance is critical for systems where both constraints must be met.

20
1.6.4. Accuracy and Precision

While 8-bit dividers are intrinsically designed for binary division, the accuracy and
precision of the division results may be challenging to ensure, especially for non-ideal
or edge cases. Challenges associated with accuracy include:

Round-Off Errors: Division of binary numbers suffers from round-off errors

because the fractional parts cannot be represented with adequate precision, which is
truncated in most cases. Such errors add up when repeated division is involved,
making the quotient or remainder inaccurate. Therefore, the design should take into
account how it will deal with such errors for the division operation to be accurate.

Overflow and Underflow: An 8-bit divider needs to correctly deal with overflow and
underflow. Overflow happens when the quotient becomes larger than that which can
be represented by the quotient register of 8 bits, and underflow happens if the divisor
is larger than the dividend, thus making the result false. The design should have an
appropriate mechanism to detect overflow as well as the error correction in order to
prevent such occurrences.

Edge Case Handling: Special cases such as division by zero or very small numbers
must be addressed in the design of the divider. A good design should ensure that such
cases are handled gracefully either by throwing an error or returning a predefined
value, for example, "infinity" or "undefined."

CHAPTER 2
Literature Review

21
Recent developments in low-power divider design have been motivated by the
growing need for energy-efficient, compact, and high-performance digital circuits.
Traditional 8-bit divider designs are usually power-hungry and have complex routing,
which makes them unsuitable for modern applications where low power, high speed,
and compactness are crucial. A significant area of improvement in divider design is
reducing power consumption through novel techniques and circuit optimizations.

S. No. REFERENCES FINDINGS LIMITATIONS

1. Sharma, P., Gupta, A., & Introduced a hybrid The hybrid
Singh, R. (2021). sleep transistor technique increased
technique for
Title: "Design and Analysis of area overhead and
reducing both
Power-Efficient 8-Bit Divider dynamic and static slightly impacted
Circuits Using Advanced power consumption the operating
in divider circuits.
Leakage Reduction frequency.
Achieved a 40%
Techniques.” reduction in
Journal: IEEE Transactions on leakage current
compared to
VLSI Systems, Vol. 29, No. 4,
traditional CMOS-
pp. 1023-1031. based designs.
2. Natarajan, K., & Iyer, M Utilized Limited
(2020). approximate applicability in
computing to
Title: "High-Speed 8-Bit high-precision
enhance speed by
Divider Design Using allowing small applications due to
Approximate Computing errors in non- error tolerance.
critical division
Techniques."
operations,
Journal: Microelectronics reducing power
Journal, Vol. 104, pp. 78-86. consumption by
35%. Improved
performance in
multimedia
applications where
exact accuracy is
not mandatory.
3. Zhang, Y., Wang, H., & Liu, Used adaptive body Increased design
F. (2021). biasing to complexity due to
dynamically

22
 Title: "Adaptive Body Bias for control leakage the requirement for
Leakage Reduction in High- power, achieving a real-time body bias
30% reduction in
Performance 45nm Divider control circuits.
idle mode leakage.
Circuits." Demonstrated
Journal: Journal of Low Power robustness across
temperature
Electronics and Applications,
variations,
Vol. 11, No. 2, pp. 57-65. maintaining power
efficiency.
4. Khan, M., & Srivastava, S. Power gating and The technique
(2020). body biasing were increased design
combined to reduce
Title: "Leakage Current complexity and
leakage currents by
Reduction in 8-Bit Divider up to 50% in idle introduced a slight
Circuits Using Power Gating states. The dynamic performance
body biasing
and Body Biasing." penalty during
allowed for real-
Journal: IEEE Transactions on time adaptation to transitions between
Circuits and Systems II: operating active and idle
conditions,
Express Briefs, Vol. 67, No. 4, states.
enhancing overall
pp. 514-521. efficiency.
5. Nair, R., & Kumar, V. (2020). Utilized dual- The increased
Title: "Leakage Power threshold CMOS fabrication
technology to
Reduction in 8-Bit Divider complexity and
reduce leakage
Circuits Using Dual Vth current while control circuitry
Technology." maintaining high made this approach
performance during
Journal: IEEE Transactions on challenging to
active states.
Electron Devices, Vol. 67, No. Achieved up to implement in large-
7, pp. 2356-2363. 50% reduction in scale systems.
total power
consumption in
low-power modes.
6. Ahmed, F., & Zaman, T. The sleepy stack The circuit design
(2019). technique was showed increased
applied to divider
Title: "Design and complexity due to
circuits, reducing
Implementation of Leakage- both static and the introduction of
Tolerant 8-Bit Dividers Using dynamic leakage extra transistors.
power by 40%.
Sleepy Stack Techniques."

23
 Journal: International Journal The method was
of VLSI Design & particularly
effective in
Communication Systems, Vol.
minimizing power
10, No. 1, pp. 87-94. loss during idle
periods.
7. Desai, N., & Jain, A. (2018). Implemented The
Title: "High-Efficiency 8-Bit dynamic voltage implementation of
scaling (DVS) to
Divider Design for VLSI DVS introduced
adjust the power
Applications Using Dynamic supply based on delays when
Voltage Scaling." workload adjusting supply
requirements,
Journal: Microelectronics voltages, affecting
leading to
Reliability, Vol. 87, pp. 104- significant power response times in
112. savings. The high-speed
divider circuits
applications.
showed a 25%
improvement in
power efficiency
without a major
impact on speed.
8. Bhargava, R., & Mehra, R. Proposed a dual- The increased
(2019). supply voltage complexity in
technique to
Title: "Design of Low Leakage managing two
optimize power
Power 8-Bit Dividers Using consumption, different supply
Dual-Supply Voltage achieving up to voltages led to
35% power
Techniques." design overhead.
reduction in divider
Journal: Journal of circuits. Suitable
Semiconductor Technology and for low-power
applications such
Science, Vol. 19, No. 2, pp.
as mobile devices
193-201. and embedded
systems.
9. Ravi, V., & Srinivasan, K. Combined clock Increased
(2018). gating with sleep complexity in
transistor
Title: "Low Power 8-Bit controlling the
techniques to
Divider Using Clock Gating achieve a 40% clock gating logic
and Leakage Reduction reduction in and maintaining
dynamic power
Techniques." synchronization
consumption

24
 Journal: IEEE Access, Vol. 6, during idle periods. across different
pp. 14265-14273. Demonstrated modules.
improved
efficiency in
circuits with
fluctuating
workloads.
10. Mandal, A., & Das, P. (2019). Implemented The pipelining
Title: "Design of High-Speed pipelining technique increased
techniques to
8-Bit Dividers for VLSI the area and power
reduce division
Applications Using Pipelining time, enhancing the consumption,
Techniques." speed of the divider making it less
circuits by 30%.
Journal: International Journal suitable for low-
The method was
of Electronics and particularly useful power devices.
Communications, Vol. 103, pp. in high-
performance
81-89.
computing
applications.
11. Patel, S., & Rao, K. (2018). Introduced multi- Increased design
Title: "A Power-Efficient 8-Bit threshold CMOS complexity due to
technology in
Divider Using the Multi- the need for
divider circuits to
Threshold CMOS Technique." reduce leakage multiple threshold
Journal: Microelectronics power during idle voltage control
periods while
Journal, Vol. 85, pp. 54-61. circuits.
maintaining speed.
Achieved up to
45% power savings
without
compromising
throughput.
12. Chakraborty, D., & Dey, S. Employed the Increased delay due
(2020). GALEOR to the use of
technique to reduce
Title: "Reduction of Leakage additional
leakage power in
Power in VLSI Circuits Using the divider circuits, transistors in the
GALEOR Technique for particularly GALEOR
effective in deep
Divider Design." technique.
submicron
Journal: IEEE Transactions on technologies.
VLSI Systems, Vol. 28, No. 12, Demonstrated up to

25
 pp. 1265-1273. a 70% reduction in
leakage power in
45nm technology
nodes.
13. Singh, P., & Yadav, N. (2019). Implemented The circuit showed
Title: "Design of Low-Power 8- leakage control increased
mechanisms such
Bit Divider Circuit Using sensitivity to
as stack forcing and
Leakage Control Techniques." dual-Vth process variations,
Journal: Journal of Low Power techniques to impacting
minimize power
Electronics and Applications, consistency across
dissipation in 8-bit
Vol. 9, No. 3, pp. 32-41. dividers. Achieved different fabrication
significant runs.
reductions in
leakage power
while maintaining
operational speed.
14. Ali, A., & Khan, S. (2023). Employed dual Increased design
Title: "Design of a Low-Power supply voltages to complexity due to
reduce power
8-Bit Divider Using Dual the need for voltage
consumption,
Supply Voltages." achieving a 25% regulation circuits.
Journal: IEEE Transactions on improvement in
energy efficiency
Very Large-Scale Integration
compared to single
(VLSI) Systems, Vol. 31, No. 1, supply designs.
pp. 12-21. Maintained high
performance by
dynamically
adjusting the
supply voltage for
critical paths.
15. Dutta, P., & Bhattacharya, S. Presented a sleep Increased transistor
(2022). transistor method count leads to a
to minimize power
Title: "Leakage Power larger chip area.
leakage in divider
Reduction in 8-Bit Dividers circuits, achieving
Using Sleep Transistor a 35% reduction in
leakage power
Techniques."
during idle states.
Journal: Microelectronics Suitable for
Reliability, Vol. 123, pp. 40-50. portable and
battery-operated

26
 devices due to
minimal impact on
speed.
16. Roy, A., & Biswas, P. (2023). Approximate logic Limited to
Title: "High-Efficiency 8-Bit techniques were applications where
used to design an
Divider Circuit Using minor inaccuracies
efficient divider
Approximate Logic." circuit for signal are tolerable.
Journal: Journal of VLSI processing
applications,
Signal Processing, Vol. 99, No.
achieving a 20%
3, pp. 401-411. reduction in
computation time.
Reduced area and
power consumption
made it suitable for
mobile and
embedded
applications.
17. Singh, R., & Verma, A. Implemented multi- The design
(2021). threshold voltage complexity
transistors to
Title: "Low-Power 8-Bit increased
reduce leakage
Divider Design Using Multi- during idle periods significantly due to
Threshold CMOS while maintaining additional control
high-speed
Technology." circuitry.
performance.
Journal: IEEE Journal of Solid- Achieved up to
State Circuits, Vol. 56, No. 5, 60% reduction in
power consumption
pp. 1321-1330.
compared to single-
threshold designs.
18. Rahman, F., & Das, P. (2022). Used the GALEOR Increased delay in
Title: "Design and Simulation technique in switching
divider circuits
of a Power-Efficient Divider transitions due to
within ALUs,
Circuit for ALU Using achieving the additional
GALEOR Technique." substantial transistors in the
reductions in
Journal: Microprocessors and GALEOR setup.
leakage current
Microsystems, Vol. 80, pp. 85- without impacting
92. performance.
Demonstrated

27
 suitability for low-
power
microprocessor
designs.
19. Jain, S., Kundu, B., & Malik, Proposed a The performance
S. (2020). FinFET-based gain is constrained
Title: "Design of a Low- divider circuit that by process
Leakage 8-Bit Divider Using significantly variations inherent
FinFET Technology." reduces gate oxide to FinFET
Journal: International Journal leakage in sub- technology.
of VLSI Design & 22nm technologies.
Communication Systems, Vol. Achieved a 50%
11, No. 3, pp. 124-132. reduction in static
power consumption
compared to
traditional bulk
CMOS circuits.
20. Hossain, M. M., & Islam, N. Reviewed various Difficulty in
(2022). leakage reduction applying GALEOR
Title: "A Review of techniques, at high frequencies
Subthreshold Leakage including gate-level due to signal
Reduction Techniques in 8-Bit and circuit-level integrity issues.
Divider Design." strategies like the
Journal: ACM Journal on GALEOR
Emerging Technologies in technique.
Computing Systems, Vol. 18, Showcased the
No. 1, pp. 45-53. efficiency of
GALEOR in
reducing
subthreshold
leakage,
particularly in deep
submicron
processes.
21. Patil, S., & Kulkarni, D. Clock gating Complex
(2021). reduced dynamic implementation of
Title: "8-Bit Divider Design power consumption clock-gating
Using Clock-Gating for Power by up to 45% increases design
Reduction in VLSI." during idle periods, and verification
Journal: IEEE Access, Vol. 9, especially in time.
pp. 65700-65710. arithmetic units
like dividers.
Demonstrated
improved power

28
 efficiency in
applications with
variable workloads.
22. Chen, J., & Sun, Y. (2023). Proposed a novel Trade-off between
Title: "Dynamic Power leakage power efficiency
Reduction in 8-Bit Divider compensation and computational
Circuits Using Leakage Power technique using speed.
Compensation." dynamic power
Journal: IEEE Transactions on control, leading to
Circuits and Systems I, Vol. 70, a 25% reduction in
No. 2, pp. 343-351. total power
consumption.
Particularly
effective in circuits
operating at low
supply voltages.

One is to apply dynamic voltage scaling along with clock gating to reduce the power
consumption of the divider circuit. Several studies have shown that the key to such a
reduction in power dissipation is not any of the above but dynamic power
management strategies, including adjusting supply voltage and disabling unused
components during idle periods. The reduction of the switching activity in large bit-
width dividers is particularly important for lowering overall power consumption, most
notably in battery-powered devices for communication and portable systems. But still
challenges in the above issue remain to achieve these reductions in power usage while
maintaining performance [1].

Leakage Power Reduction Techniques have also been developed in low power divider
design. Technologies like body biasing, multi-threshold CMOS, and gate oxide
engineering have been proposed to minimize leakage currents, especially in sub-
micron technologies. These techniques reduce leakage-induced power losses but add
complexity in the design of the circuit and introduce possible delays in the operation.
Power reduction and delay optimization form a fine balance in the challenge for
implementing efficient 8-bit dividers in modern systems [2].

An altered algorithmic divider structure, based on digit recurrence methods and

restore-less algorithms, has become common for the purposes of speeding up and

29
saving energy. Such structures reduce the number of intermediate operations in
division and, hence, save energy. Moreover, the algorithmic methods combined with
hardware acceleration blocks, like parallel multiplication and shifting, can
significantly improve the performance of dividers without a significant increase in
area. However, the integration of these techniques with standard logic gates often
leads to a complex design process that may increase the overall layout time, especially
when simulating with tools like Cadence Virtuoso [3].

Technology-Dependent Optimizations. Contributions to modern semiconductor nodes

are also significant in the area of technology-dependent optimizations. In particular,
FinFET and Gate-All-Around (GAA) transistors are explored for improving the speed
and efficiency of arithmetic circuits, including dividers. These devices have lower
power consumption and higher performance due to reduced short-channel effects and
better scalability. Yet, these technologies are still in their development phase, and
while promising superior performance, fabrication processes and cost are still an issue
[4].

Furthermore, great effort has been focused on minimizing the area of the 8-bit divider
circuits, particularly in SoC design. Approximate computing techniques are
considered promising methods to reduce circuit area and power dissipation; this
technique trades off exactness with efficiency, particularly in signal processing and
error-tolerant systems. However, the use of approximations may reduce the accuracy
of the division, making these solutions unsuitable for applications requiring high
precision [5].

The Cadence Virtuoso platform, widely used for custom IC design, plays a crucial
role in simulating and optimizing these low-power 8-bit dividers. Advanced parasitic
extraction and signal integrity analysis capabilities of Virtuoso help ensure that
designs meet stringent performance criteria while reducing power losses. However,
the simulation time and optimization steps could be quite cumbersome, especially
with large, complex designs. It is therefore key to manage an efficient design flow and
make good use of Automated Layout Generation tools in order not to compromise on
performance [6].

30
The use of dynamic voltage scaling (DVS) has been of interest in optimizing 8-bit
divider circuits to be low in power. At present, this method aims to reduce leakage
currents with performance by dynamically adjusting the supply voltage according to
the computational needs. Hence, the power dissipation is reduced severally. The key
challenge would be to make sure that voltage scaling does not affect the operational
speed, especially in high-frequency designs, where real-time adjustments are vital [7].

Another widely used technique for reducing dynamic power consumption in digital
circuits, such as dividers, is clock gating. It reduces power usage during idle periods
by selectively turning off the clock signal to parts of the circuit that are not in use.
Incorporating clock gating in 8-bit divider designs has been proven to reduce overall
switching activity, hence reducing energy usage without affecting the functionality of
the divider [8].

Sub-threshold CMOS operation seems to be a promising path toward low-power

divider design, exploiting the region below the threshold voltage for power
consumption reduction. However, subthreshold operation often comes at the cost of
slower switching speeds and reduced noise margins. Techniques that address these
trade-offs, such as MTCMOS and body biasing, have been proposed to make
subthreshold circuits more robust without compromising performance [9].

Multi-threshold CMOS, MTCMOS is the most commonly used technique used for
leakage power mitigation in digital circuits. Through its application to have different
threshold voltages for different sections of the circuit, MTCMOS mitigates
subthreshold leakage in those non-critical areas while preserving the high-
performance area at the low voltage only. When this approach is adapted for 8-bit
divider circuits, MTCMOS promises an excellent power speed trade-off [10].

Leakage power is an increasing problem in divider circuits as CMOS technology

scales down. Sleep transistors, gate oxide engineering, and high-k dielectrics have
been investigated for their ability to reduce leakage currents. These techniques will
significantly improve the energy efficiency of 8-bit dividers, especially for mobile and
portable devices where battery life is crucial [11].

31
Hardware acceleration is used to speed up the division process by incorporating
accelerator techniques in divider circuits. Algorithmic modification and parallel
multiplication along with shifting speed up the computation and decrease the number
of cycles needed to complete the division. Although these techniques enhance the
performance, they are often enlarged area footprints, leading to the necessity of trade-
off between power, area, and performance [12].

The use of digit recurrence methods in divider algorithms improves both speed and
power efficiency. These methods reduce the number of operations needed to divide
large numbers by breaking the problem into smaller, more manageable pieces.
Implementing these methods in 8-bit dividers, however, requires advanced
algorithmic optimization and careful integration with logic gates to prevent excessive
delay [13].

Approximate computing is found to be one of the possible solutions to achieve

energy-efficient arithmetic circuits. For dividers, approximation techniques are
applied that balance accuracy and power consumption. This is especially helpful in
those applications where a small amount of error in division results can be tolerated.
This is useful in signal processing and machine learning applications, for example.
However, there are issues related to finding acceptable error bounds for different
applications [14].

The need for a balance between power consumption, speed, and accuracy is ever-
present in the design of 8-bit dividers. Although power consumption can be
minimized using dynamic voltage scaling and clock gating techniques, they do come
at a performance cost. Also, incorporating approximate computing or reducing bit-
widths can minimize area and power but at the expense of accuracy. Thus, there is a
trade-off in designing these circuits and achieving the desired optimality by
optimization algorithms [15].

Cadence Virtuoso has an all-encompassing package for custom IC design that

provides the means of simulating and optimizing divider circuits to operate with
minimal power but at a very high-performance level. Capabilities in this area include
parasitic extraction, signal integrity analysis, and automatic layout generation. These
32
aspects will definitely save on the design time while also ensuring the circuit satisfies
power and speed requirements. Custom IC design can, however be so complicated,
thereby giving way to simulation time and longer design cycles [16].

FinFET and Gate-All-Around (GAA) transistors provide much better performance

because of reduced short-channel effects and higher scalability. These technologies
can be used to improve the performance and reduce the power consumption of 8-bit
dividers. However, the manufacturing challenges and high cost of these advanced
devices are the major obstacles to their wide use in commercial products [17].

New challenges and opportunities in divider designs are presented with the advent of
sub-7nm semiconductor nodes. In these nodes, parasitic capacitance and resistance
have significant effects, making low power and high-performance challenging.
Advanced material systems and novel transistor architectures have been targeted to
satisfy the performance and power requirements of modern 8-bit dividers [18].

Techniques used for parallel computing are parallel multipliers and adders, and
divider designs typically include these in order to enhance performance. Simultaneous
performance of multiple steps in division helps increase the speed of the divider
significantly. Though it increases the performance, this technique usually consumes a
more complex design and greater area. Thus, this method is less preferable for small
compact devices where the area is minimal [19].

Area optimization in the design of low-power 8-bit dividers for System-on-Chip is a

crucial issue. Techniques applied for minimizing the area requirements of divider
circuits include the use of resource sharing, compact logic synthesis, and hierarchical
designs. The reduction in area not only diminishes power consumption but also allows
for additional components to be accommodated in a smaller chip area, which is a
characteristic of modern mobile and embedded systems [20].

Cadence Virtuoso is a great tool for creating custom IC designs, but it has its set of
challenges, such as 8-bit dividers design and simulation. In fact, designing an 8-bit
divider on Cadence Virtuoso includes integrating low power techniques, achieving
signal integrity, and managing parasitic in the high-speed designs. Optimization tends

33
to require iterations as well as combining both manual and automated layout
techniques toward meeting the needed performance and power goals [21].

Adaptive body biasing is a dynamic approach for optimizing the power consumption
and performance by altering the threshold voltage of transistors during runtime. This
is a very efficient approach to leakage current reduction in standby modes, but it helps
to increase speed in active modes. Research demonstrates the compatibility of ABB
with 8-bit divider circuits to make low-power applications flexible, with no impact on
computational accuracy [22].

CHAPTER 3
Work Completed in the 7th Semester

TTTLE OF THE BASE PAPER: 8 - Bit Parallel Divider using Galeor Technique
to reduce Leakage Current using 45nm technology
3.1. Base Paper Simulation

34
The simulation of the 8-bit parallel divider with the GALEOR technique aims to
determine the effectiveness of this technique in minimizing leakage current and power
consumption. The circuit design consists of different combinational and sequential
logic elements, such as a 5-bit subtractor, 2:1 multiplexer, D flip-flops, a 5-bit
comparator, a 9-bit parallel-in-parallel-out (PIPO) shift-left register, and multiplexers
of different widths. All these elements combine to perform binary division through
shifting and subtraction operations.

The simulation process was performed in Tanner EDA tools to evaluate the
performance of the divider by using the 45nm CMOS technology node. The technique
GALEOR is used through the integration of both n-type and p-type GLTs between
pull-up and pull-down networks for the circuit under consideration. Thereby, in these
transistors, both the gates connect to the terminals of each drain, thus increasing
resistance and reducing the leakage current on idle states. This overlap effect ensures
that leakage current is substantially reduced since at least one of the GLTs enters the
cut-off region, hence suppressing the leakage paths.

Fig.1 Block diagram of 8 bit parallel divider

35
 Fig. 2 Schematic of 8-bit divider using galeor technique.

3.2. Operation Description:

Division Procedure: The circuit carries out division of the dividend by the divisor
using repeated shifts and subtractions. For each step:
 The dividend register is shifted one bit left.
 Comparator checks if the divisor is smaller than or equal to the leftmost bits
of the dividend.
 If the condition is true, then subtraction operation is performed, and the
corresponding quotient bit is set to 1.
 Otherwise, the quotient bit is set to 0, and the loop continues to the next bit.

3.3. Results and Performance:

The simulation compares the performance of the 8-bit divider with and without the
GALEOR technique. The important results are listed below:
Parameter Without GALEOR With GALEOR
Leakage Current 10 µA 40 nA
Power Consumption 2.72 mW 0.12 µW
Delay 0.15 µs 0.19 µs

 Leakage Current: GALEOR transistors decreased leakage current by a

significant amount, from 10 µA to 40 nA, and thus proved to be an efficient
method for controlling leakage in CMOS circuits.
 The power consumption was decreased significantly to a level as low as 0.12
µW, compared to an original value of 2.72 mW. This improvement is critical

36
 in low-power applications, especially for portable and embedded systems.
 Delay: The GALEOR-enhanced circuit has a slightly increased delay from
0.15 µs to 0.19 µs. This is a trade-off of the gated leakage transistors, which
adds a bit of resistance to the circuit, thereby slowing it down.

3.4. Waveform Analysis:

Waveform analysis is an essential step in ensuring the functionality and accuracy of
the performance of any digital circuit design, such as the 8-bit divider GALEOR
enhanced. It brings out how it behaves when operated; it will make known the effects
such as leakage currents reduction and increased power efficiency introduced by the
proposals. The waveform analysis was focused on the two main points: the
correctness of the division results at the output and leakage current reduction based on
the GALEOR technique.
3.4.1. Output Waveforms for Division Operation
The functionality of the circuit, which was to perform binary division, was tested
using simulated test cases. For instance, the division of 135 by 13 was selected as a
representative test case. Here's a step-by-step breakdown of how the output
waveforms illustrated the correctness of the circuit:

In the simulation, the 8-bit dividend was represented as 10000111 (135 in decimal),
and the 8-bit divisor was represented as 00001101 (13 in decimal). These binary
values were loaded into their respective registers at the start of the operation.

 Division Process Visualization:

The waveforms show how the circuit performed the division through repeated
shifting and subtraction operations:
o At each clock cycle, the comparator checked whether the divisor
could fit into the MSBs of the shifted dividend.
o If the condition was satisfied, the subtractor performed the subtraction
required, and the corresponding bit in the quotient register was set to
1.
o If the condition was not satisfied, the quotient bit was set to 0, and the
process continued.
 Quotient and Remainder:

37
 The waveforms clearly showed the gradual construction of the quotient in the
quotient register. After the final step, the quotient was 00001010 (10 in decimal),
and the remainder in the remainder register was 00000101 (5 in decimal). These
values matched the expected results of the division operation, verifying the
circuit's accuracy.

 Timing Analysis:
The waveforms showed that the circuit had completed the division process in 8
clock cycles, as expected for an 8-bit divider. The propagation delays introduced
by the logic gates and registers were consistent with the design specifications.

Fig. 3 Leakage current waveforms of 8-bit parallel divider using galeor technique

3.4.2. Leakage Current Waveforms

The leakage current waveforms were crucial in demonstrating the effectiveness of the
GALEOR technique in reducing static power dissipation. Key observations included:
 Comparison with Conventional Design:
o In the conventional 8-bit divider circuit, leakage current values
remained consistently high throughout the simulation, even during
idle periods when no active computation was performed. The
waveform showed a typical leakage current of around 10 µA in idle

38
 states.
o In contrast, the GALEOR-enhanced circuit exhibited significantly
reduced leakage currents during idle states, with the waveform
showing values as low as 40 nA, representing a reduction of over
99.5%.
 Active States Behaviour:
When the circuit was under active computation, the two circuits showed a similar
current, since GALEOR transistors are fully functional during active
computation. This ensured that the GALEOR technique didn't degrade the circuit
performance during its active operation period.
 Idle States:
Leakage current waveforms in the GALEOR circuit indicate that near zero
currents occurred for the time intervals of non-operation states of the divider.
This supports the effectiveness of gated leakage transistors as leakage paths for
the idle state.

Fig. 4 Leakage current waveforms of 8-bit parallel divider without galeor technique

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39
1. Ji, S., Dong, Y., & Fan, Y. "Bandpass Filter Prototype Inspired Filtering Patch
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