tl052

TL05x, TL05xA
ENHANCED-JFET LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003
D Direct Upgrades to TL07x and TL08x BiFET D On-Chip Offset-Voltage Trimming for
Operational Amplifiers Improved DC Performance and Precision
D Faster Slew Rate (20 V/µs Typ) Without Grades Are Available (1.5 mV, TL051A)
Increased Power Consumption
TL051 TL052 TL054

D OR P PACKAGE D, P, OR PS PACKAGE D, DB, N, OR NS PACKAGE
(TOP VIEW) (TOP VIEW) (TOP VIEW)
OFFSET N1 1 8 NC 1OUT 1 8 VCC+ 1OUT 1 14 4OUT

IN– 2 7 VCC+ 1IN– 2 7 2OUT 1IN– 2 13 4IN–
IN+ 3 6 OUT 1IN+ 3 6 2IN– 1IN+ 3 12 4IN+
VCC– 4 5 OFFSET N2 VCC– 4 5 2IN+ VCC+ 4 11 VCC–
2IN+ 5 10 3IN+
2IN– 6 9 3IN–
2OUT 7 8 3OUT
description/ordering information
The TL05x series of JFET-input operational amplifiers offers improved dc and ac characteristics over the TL07x
and TL08x families of BiFET operational amplifiers. On-chip Zener trimming of offset voltage yields precision
grades as low as 1.5 mV (TL051A) for greater accuracy in dc-coupled applications. Texas Instruments improved
BiFET process and optimized designs also yield improved bandwidth and slew rate without increased power
consumption. The TL05x devices are pin-compatible with the TL07x and TL08x and can be used to upgrade
existing circuits or for optimal performance in new designs.
BiFET operational amplifiers offer the inherently higher input impedance of the JFET-input transistors, without
sacrificing the output drive associated with bipolar amplifiers. This makes them better suited for interfacing with
high-impedance sensors or very low-level ac signals. They also feature inherently better ac response than
bipolar or CMOS devices having comparable power consumption.
The TL05x family was designed to offer higher precision and better ac response than the TL08x, with the low
noise floor of the TL07x. Designers requiring significantly faster ac response or ensured lower noise should
consider the Excalibur TLE208x and TLE207x families of BiFET operational amplifiers.
Because BiFET operational amplifiers are designed for use with dual power supplies, care must be taken to
observe common-mode input voltage limits and output swing when operating from a single supply. DC biasing
of the input signal is required, and loads should be terminated to a virtual-ground node at mid-supply. Texas
Instruments TLE2426 integrated virtual ground generator is useful when operating BiFET amplifiers from single
supplies.
The TL05x are fully specified at ±15 V and ±5 V. For operation in low-voltage and/or single-supply systems,
Texas Instruments LinCMOS families of operational amplifiers (TLC-prefix) are recommended. When moving
from BiFET to CMOS amplifiers, particular attention should be paid to the slew rate and bandwidth
requirements, and also the output loading.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright  2003, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

TL05x, TL05xA
ORDERING INFORMATION
VIOmax ORDERABLE TOP-SIDE
TA PACKAGE†
AT 25°C PART NUMBER MARKING
TL051ACP TL051ACP
PDIP (P) Tube of 50
TL052ACP TL052ACP
800 µV Tube of 75 TL051ACD 051AC
SOIC (D) Tube of 75 TL052ACD
052AC
Reel of 2500 TL052ACDR
TL051CP TL051CP
PDIP (P) Tube of 50
TL052CP TL052CP
PDIP (N) Tube of 25 TL054ACN TL054ACN
Tube of 75 TL051CD
TL051C
Reel of 2500 TL051CDR
0°C to 70°C
1.5 mV Tube of 75 TL052CD
SOIC (D) TL052C
Tube of 50 TL054ACD
TL054C
Reel of 2500 TL054ACDR
SOP (PS) Reel of 2000 TL052CPSR TL052
SSOP (DB) Reel of 2000 TL054CDBR TL054
PDIP (N) Tube of 25 TL054CN TL054CN
Tube of 50 TL054CD
4 mV SOIC (D) TL054C
SOP (NS) Reel of 2000 TL054CNSR TL054
PDIP (P) Tube of 50 TL052AIP TL052AI
800 µV Tube of 75 TL052AID
SOIC (D) 052AI
Reel of 2500 TL052AIDR
PDIP (N) Tube of 25 TL054AIN TL054AIN
TL051IP TL051IP
PDIP (P) Tube of 50
TL052IP TL052IP
Tube of 75 TL051ID TL051I
–40°C
40°C to 85°C 1 5 mV
1.5
Tube of 75 TL052ID
TL052I
SOIC (D) Reel of 2500 TL052IDR
Tube of 50 TL054AID
TL054AI
Reel of 2500 TL054AIDR
PDIP (N) Tube of 25 TL054IN TL054IN
4 mV Tube of 50 TL054ID
SOIC (D) TL054I
Reel of 2500 TL054IDR
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL05x, TL05xA
symbol (each amplifier)
IN–
–
OUT
+
IN+
equivalent schematic (each amplifier)

VCC+
Q10
Q2 Q15
JF3
Q3
Q7
Q6 Q16
Q11 Q13
IN+
Q12 R7
D1 R9
IN– R5 OUT
JF1 JF2
R8
C1
Q4 Q14 Q17
Q8
Q1
Q5 Q9
OFFSET N1 R10 D2
See Note A OFFSET N2 R4
R6
R1 R2 R3
VCC–
NOTE A: OFFSET N1 and OFFSET N2 are available only on the TL051x.
ACTUAL DEVICE COMPONENT COUNT†

COMPONENT TL051 TL052 TL054
Transistors 20 34 62
Resistors 10 19 37
Diodes 2 3 5
Capacitors 1 2 4
† These figures include all four amplifiers and all ESD, bias, and trim circuitry.

TL05x, TL05xA
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VCC+ (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V
Supply voltage, VCC– (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 V
Differential input voltage (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±30 V
Input voltage range, VI (any input, see Notes 1 and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±15 V
Input current, II (each input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±1 mA
Output current, IO (each output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±80 mA
Total current into VCC+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 mA
Total current out of VCC– . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 mA
Duration of short-circuit current at (or below) 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unlimited
Package thermal impedance, θJA (see Notes 4 and 5): D package (8 pin) . . . . . . . . . . . . . . . . . . . . . . 97°C/W
D package (14 pin) . . . . . . . . . . . . . . . . . . . . . 86°C/W
DB package (14 pin) . . . . . . . . . . . . . . . . . . . 96°C/W
N package (14 pin) . . . . . . . . . . . . . . . . . . . . . 80°C/W
NS package (14 pin) . . . . . . . . . . . . . . . . . . . 76°C/W
P package (8 pin) . . . . . . . . . . . . . . . . . . . . . . 85°C/W
PS package (8 pin) . . . . . . . . . . . . . . . . . . . . 95°C/W
Operating virtual junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Lead temperature 1,6 mm (1/16inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential voltages, are with respect to the midpoint between VCC+ and VCC–.
2. Differential voltages are at IN+ with respect to IN–.
3. The magnitude of the input voltage must never exceed the magnitude of the supply voltage or 15 V, whichever is less.
4. Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable
ambient temperature is PD = (TJ(max) – TA)/θJA. Operating at the absolute maximum TJ of 150°C can impact reliability.
5. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions

C SUFFIX I SUFFIX
UNIT
MIN MAX MIN MAX
VCC± Supply voltage ±5 ±15 ±5 ±15 V
VCC± = ±5 V –1 4 –1 4
VIC Common mode input voltage
Common-mode V
VCC± = ±15 V –11 11 –11 11
TA Operating free-air temperature 0 70 –40 85 °C

TL05x, TL05xA
TL051C and TL051AC electrical characteristics at specified free-air temperature

TL051C, TL051AC
PARAMETER TEST CONDITIONS TA† VCC± = ±5 V VCC± = ±15 V UNIT
MIN TYP MAX MIN TYP MAX
25°C 0.75 3.5 0.59 1.5
TL051C
Full range 4.5 2.5
VIO Input offset voltage mV
25°C 0.55 2.8 0.35 0.8
TL051AC
Full range 3.8 1.8
VO = 0
0,
VIC = 0, 25°C to
TL051C 8 8
Temperature coefficient RS = 50 Ω 70°C
aV µV/°C
IO of input offset voltage‡ 25°C to
TL051AC 8 8 25
70°C
Input offset-voltage
25°C 0.04 0.04 µV/mo
long-term drift§
VO = 0, VIC = 0, 25°C 4 100 5 100 pA
IIO Input offset current
See Figure 5 70°C 0.02 1 0.025 1 nA
VO = 0, VIC = 0, 25°C 20 200 30 200 pA
IIB Input bias current
See Figure 5 70°C 0.15 4 0.2 4 nA
–1 –2.3 –11 –12.3
25°C to to to to
Common-mode input 4 5.6 11 15.6
VICR V
voltage range –1 –11
Full range to to
4 11
25°C 3 4.2 13 13.9
RL = 10 kΩ
Maximum positive peak Full range 3 13
VOM
OM+ V
output voltage swing 25°C 2.5 3.8 11.5 12.7
RL = 2 kΩ
Full range 2.5 11.5
25°C –2.5 –3.5 –12 –13.2
RL = 10 kΩ
Maximum negative
g peak Full range –2.5 –12
VOM
OM– V
output voltage swing 25°C –2.3 –3.2 –11 –12
RL = 2 kΩ
Full range –2.3 –11
25°C 25 59 50 105
Large-signal
L i l differential
diff ti l
AVD RL = 2 kΩ 0°C 30 65 60 129 V/mV
lification¶
amplification
voltage am
70°C 20 46 30 85
ri Input resistance 25°C 1012 1012 Ω
ci Input capacitance 25°C 10 12 pF
25°C 65 85 75 93
Common-mode
Common mode VIC = VICRmin,
min
CMRR 0°C 65 84 75 92 dB
rejection ratio VO = 0
0, RS = 50 Ω
70°C 65 84 75 91
25°C 75 99 75 99
Supply voltage rejection
Supply-voltage
kSVR VO = 0, RS = 50 Ω 0°C 75 98 75 98 dB
ratio (∆VCC±/∆VIO)
70°C 75 97 75 97
25°C 2.6 3.2 2.7 3.2
ICC Supply
y current VO = 0, No load 0°C 2.7 3.2 2.8 3.2 mA
70°C 2.6 3.2 2.7 3.2
† Full range is 0°C to 70°C.
‡ This parameter is tested on a sample basis for the TL051A. For other test requirements, please contact the factory. This statement has no bearing
on testing or nontesting of other parameters.
§ Typical values are based on the input offset-voltage shift observed through 168 hours of operating life test at TA = 150°C, extrapolated to
TA = 25°C using the Arrhenius equation, and assuming an activation energy of 0.96 eV.
¶ For VCC± = ±5 V, VO = ±2.3 V, or for VCC± = ±15 V, VO = ±10 V.

TL05x, TL05xA
TL051C and TL051AC operating characteristics at specified free-air temperature

TL051C, TL051AC
25°C 16 13 20
Positive
P iti slew
l rate
t
SR+ Full
at unity gain‡ 16.4 11 22.6
RL = 2 kΩ,, CL = 100 pF,, range
V/µs
See Figure 1 25°C 15 13 18
Negative
N ti slew
l rate
t
SR– Full
at unity gain‡ 16 11 19.3
range
25°C 55 56
tr Rise time 0°C 54 55
70°C 63 63
ns
VI(PP) = ±10 mV, 25°C 55 57
RL = 2 kΩ,
kΩ
tf Fall time 0°C 54 56
CL = 100 pFF,
See Figures
g 1 and 2 70°C 62 64
25°C 24 19
Overshoot factor 0°C 24 19 %
70°C 24 19
Equivalent
q input noise f = 10 Hz 25°C 75 75
Vn nV/√Hz
voltage§ RS = 20 Ω, f = 1 kHz 25°C 18 18 30
Peak-to-peak equivalent See Figure 3 f = 10 Hz to
VN(PP) 25°C 4 4 µV
input noise voltage 10 kHz
Equivalent input
In f = 1 kHz 25°C 0.01 0.01 pA/√Hz
noise current
RS = 1 kΩ, RL = 2 kΩ,
THD Total harmonic distortion¶ 25°C 0.003 0.003 %
f = 1 kHz
25°C 3 3.1
VI = 10 mV,
V RL = 2 kΩ,
kΩ
B1 Unity-gain bandwidth 0°C 3.2 3.3 MHz
CL = 25 pF
F, See Figure 4
70°C 2.7 2.8
25°C 59 62
Phase margin at unity VI = 10 mV,
mV RL = 2 kΩ,
kΩ
φm 0°C 58 62 deg
gain CL = 25 pF,
F, See Figure 4
70°C 59 62
‡ For VCC± = ±5 V, VI(PP) = ±1 V; for VCC± = ±15 V, VI(PP) = ±5 V.
§ This parameter is tested on a sample basis for the TL051A. For other test requirements, please contact the factory. This statement has no bearing
¶ For VCC± = ±5 V, VO(RMS) = 1 V; for VCC± = ±15 V, VO(RMS) = 6 V.

TL05x, TL05xA
TL051I and TL051AI electrical characteristics at specified free-air temperature

TL051I, TL051AI
25°C 0.75 3.5 0.59 1.5
TL051I
Full range 5.3 3.3
25°C 0.55 2.8 0.35 0.8
TL051AI
Full range 4.6 2.6
VO = 0
0,
25°C to
VIC = 0, TL051I 7 8
85°C
aV Temperature coefficient of RS = 50 Ω µV/°C
IO input offset voltage‡ 25°C to
TL051AI 8 8 25
85°C
25°C 0.04 0.04 µV/mo
long-term drift§
VO = 0, VIC = 0, 25°C 4 100 5 100 pA
See Figure 5 85°C 0.06 10 0.07 10 nA
VO = 0, VIC = 0, 25°C 20 200 30 200 pA
See Figure 5 85°C 0.6 20 0.7 20 nA
–1 –2.3 –11 –12.3
25°C to to to to
VICR V
Full range to to
4 11
25°C 3 4.2 13 13.9
RL = 10 kΩ
VOM + V
RL = 2 kΩ
Full range 2.5 11.5
25°C –2.5 –3.5 –12 –13.2
RL = 10 kΩ
Maximum negative
VOM – V
RL = 2 kΩ
25°C 25 59 50 105
Large-signal
L i l differential
diff ti l
AVD RL = 2 kΩ –40°C 30 74 60 145 V/mV
lification¶
amplification
voltage am
85°C 20 43 30 76
VIC = VICRmin, 25°C 65 85 75 93
Common mode
Common-mode
CMRR VO = 0, –40°C 65 83 75 90 dB
rejection ratio
RS = 50 Ω 85°C 65 84 75 93
25°C 75 99 75 99
Supply-voltage
Supply voltage rejection VO = 0,
0
kSVR –40°C 75 98 75 98 dB
ratio (∆VCC±/∆VIO) RS = 50 Ω
85°C 75 99 75 99
25°C 2.6 3.2 2.7 3.2
ICC Supply current VO = 0, No load –40°C 2.4 3.2 2.6 3.2 mA
85°C 2.5 3.2 2.6 3.2
† Full range is –40°C to 85°C
‡ This parameter is tested on a sample basis for the TL051A. For other test requirements, please contact the factory. This statement has no bearing
¶ For VCC± = ±5 V, VO = ±2.3 V, or for VCC± = ±15 V, VO = ±10 V.

TL05x, TL05xA
TL051I and TL051AI operating characteristics at specified free-air temperature

TL051I, TL051AI
25°C 16 13 20
Positive
P iti slew
l rate
t
SR+ Full
at unity gain‡ 11
RL = 2 kΩ,, CL = 100 pF,, range
V/µs
See Figure 1 25°C 15 13 18
Negative
N ti slew
l rate
t
SR– Full
at unity gain‡ 11
range
25°C 55 56
tr Rise time –40°C 52 53
85°C 64 65
ns
( ) = ±10 mV,
VI(PP) 25°C 55 57
RL = 2 kΩ,
kΩ
tf Fall time –40°C 51 53
CL = 100 pFF,
See Figures
g 1 and 2 85°C 64 65
25°C 24 19
Overshoot factor –40°C 24 19 %
85°C 24 19
Equivalent
Vn nV/√Hz
VN(PP) 25°C 4 4 µV
Equivalent input
In f = 1 kHz 25°C 0.01 0.01 pA/√Hz
noise current
RS = 1 kΩ, RL = 2 kΩ,
f = 1 kHz
25°C 3 3.1
VI = 10 mV,
V RL = 2 kΩ,
kΩ
B1 Unity-gain bandwidth –40°C 3.5 3.6 MHz
CL = 25 pF
F, See Figure 4
85°C 2.6 2.7
25°C 59 62
Phase margin at unity VI = 10 mV,
mV RL = 2 kΩ,
kΩ
φm –40°C 58 61 deg
gain CL = 25 pF,
F, See Figure 4
85°C 59 62
† Full range is –40°C to 85°C.
§ This parameter is tested on a sample basis for the TL051A. For other test requirements, please contact the factory. This statement has no bearing

TL05x, TL05xA

TL052C, TL052AC
25°C 0.73 3.5 0.65 1.5
TL052C
Full range 4.5 2.5
25°C 0.51 2.8 0.4 0.8
VO = 0,
0 TL052AC
Full range 3.8 1.8
VIC = 0
0,
RS = 50 Ω 25°C to
TL052C 8 8
Temperature coefficient 70°C
aV µV/°C
IO of input offset voltage‡ 25°C to
TL052AC 8 6 25
70°C
Input offset-voltage VO = 0,
VIC = 0, 25°C 0.04 0.04 µV/mo
long-term drift§ RS = 50 Ω
VO = 0,, 25°C 4 100 5 100 pA

IIO Input offset current VIC = 0
0,
See Figure 5 70°C 0.02 1 0.025 1 nA
VO = 0,, 25°C 20 200 30 200 pA
IIB Input bias current VIC = 0
0,
See Figure 5 70°C 0.15 4 0.2 4 nA
–1 –2.3 –11 –12.3
25°C to to to to
VICR V
Full range to to
4 11
25°C 3 4.2 13 13.9
RL = 10 kΩ
VOM
OM+ V
RL = 2 kΩ
Full range 2.5 11.5
25°C –2.5 –3.5 –12 –13.2
RL = 10 kΩ
Maximum negative
VOM
OM– V
RL = 2 kΩ
25°C 25 59 50 105
Large-signal
L i l diff
differential
ti l
AVD RL = 2 kΩ 0°C 30 65 60 129 V/mV
voltage am lification¶
amplification
70°C 20 46 30 85
25°C 65 85 75 93
Common mode
Common-mode min
VIC = VICRmin,
CMRR RS = 50 Ω 0°C 65 84 75 92 dB
rejection ratio VO = 0,
70°C 65 84 75 91
‡ This parameter is tested on a sample basis. For other test requirements, please contact the factory. This statement has no bearing on testing
or nontesting of other parameters.
¶ For VCC± = ±5 V, VO = ±2.3 V; at VCC± = ±15 V, VO = ±10 V.

TL05x, TL05xA
TL052C and TL052AC electrical characteristics at specified free-air temperature (continued)

TL052C, TL052AC
PARAMETER TEST CONDITIONS TA VCC± = ±5 V VCC± = ±15 V UNIT
25°C 75 99 75 99
Supply-voltage
S l lt rejection
j ti
kSVR VO = 0, RS = 50 Ω 0°C 75 98 75 98 dB
70°C 75 97 75 97
25°C 4.6 5.6 4.8 5.6
S l currentt
Supply
ICC VO = 0, No load 0°C 4.7 6.4 4.8 6.4 mA
(two amplifiers)
am lifiers)
70°C 4.4 6.4 4.6 6.4
VO1/VO2 Crosstalk attenuation AVD = 100 25°C 120 120 dB

TL052C, TL052AC
25°C 17.8 9 20.7
SR+ Slew rate at unity gain
RL = 2 kΩ, CL = 100 pF, Full range 8
V/µs
Negative
g slew rate See Figure 1 25°C 15.4 9 17.8
SR
SR–
at unity gain‡ Full range 8
25°C 55 56
70°C 63 63
ns
( ) = ±10 mV,
VI(PP) 25°C 55 57
RL = 2 kΩ,
kΩ
CL = 100 pFF,
See Figures
g 1 and 2 70°C 62 64
25°C 24 19
Overshoot factor 0°C 24 19 %
70°C 24 19
Equivalent
Vn nV/√Hz
VN(PP) 25°C 4 4 µV
input noise current 10 kHz
Equivalent input
In f = 1 kHz 25°C 0.01 0.01 pA/√Hz
noise current
RS = 1 kΩ, RL = 2 kΩ,
f = 1 kHz
25°C 3 3
VI = 10 mV,
V RL = 2 kΩ,
kΩ
B1 Unity-gain bandwidth 0°C 3.2 3.2 MHz
CL = 25 pF
F, See Figure 4
70°C 2.6 2.7
25°C 60 63
Phase margin at unity mV
VI = 10 mV, kΩ
RL = 2 kΩ,
φm 0°C 59 63 deg
gain CL = 25 pF,
F, See Figure 4
70°C 60 63
§ This parameter is tested on a sample basis. For other test requirements, please contact the factory. This statement has no bearing on testing

TL05x, TL05xA

TL052I, TL052AI
25°C 0.73 3.5 0.65 1.5
TL052I
Full range 5.3 3.3
25°C 0.51 2.8 0.4 0.8
VO = 0,
0 TL052AI
Full range 4.6 2.6
VIC = 0,
RS = 50 Ω 25°C to
TL052I 7 6
85°C
aV T
Temperature
t ffi i t‡
coefficient µV/°C
IO 25°C to
TL052AI 6 6 25
85°C
Input offset-voltage VO = 0,
VIC = 0, 25°C 0.04 0.04 µV/mo
long-term drift§ RS = 50 Ω
VO = 0,, VIC = 0,, 25°C 4 100 5 100 pA

See Figure 5 85°C 0.06 10 0.07 10 nA
VO = 0,, VIC = 0,, 25°C 20 200 30 200 pA
See Figure 5 85°C 0.6 20 0.7 20 nA
–1 –2.3 –11 –12.3
25°C to to to to
VICR V
Full range to to
4 11
25°C 3 4.2 13 13.9
RL = 10 kΩ
VOM
OM+ V
RL = 2 kΩ
Full range 2.5 11.5
25°C –2.5 –3.5 –12 –13.2
RL = 10 kΩ
Maximum negative
VOM
OM– V
RL = 2 kΩ
25°C 25 59 50 105
Large-signal
L i l diff
differential
ti l
AVD RL = 2 kΩ –40°C 30 74 60 145 V/mV
voltage am lification¶
amplification
85°C 20 43 30 76
25°C 65 85 75 93
Common-mode
min
CMRR RS = 50 Ω –40°C 65 83 75 90 dB
rejection ratio VO = 0,
85°C 65 84 75 93
‡ This parameter is tested on a sample basis. For other test requirements, please contact the factory. This statement has no bearing on testing
or nontesting of other parameters
¶ At VCC± = ±5 V, VO = ±2.3 V; at VCC± = ±15 V, VO = ±10 V.

TL05x, TL05xA
TL052I and TL052AI electrical characteristics at specified free-air temperature (continued)

TL052I, TL052AI
PARAMETER TEST CONDITIONS TA VCC± = ±5 V VCC± = ±15 V UNIT
25°C 75 99 75 99
Supply-voltage
S l lt rejection
j ti
kSVR VO = 0, RS = 50 Ω –40°C 75 98 75 98 dB
85°C 75 99 75 99
25°C 4.6 5.6 4.8 5.6
S l currentt
Supply
ICC VO = 0, No load –40°C 4.5 6.4 4.7 6.4 mA
(two amplifiers)
am lifiers)
85°C 4.4 6.4 4.6 6.4

TL052I, TL052AI
25°C 17.8 9 20.7
SR+ Sl
Slew rate
t att unity i ‡
it gain
RL = 2 kΩ,, CL = 100 pF,, Full range 8
V/µs
Negative
g slew rate at See Figure 1 25°C 15.4 9 17.8
SR
SR–
unity gain‡ Full range 8
25°C 55 56
85°C 64 65
ns
VI(PP) = ±10 mV, 25°C 55 57
tf Fall time RL = 2 kΩ, CL = 100 pF, –40°C 51 53
See Figures 1 and 2 85°C 64 65
25°C 24% 19%
Overshoot factor –40°C 24% 19% %
85°C 24% 19
Equivalent
Vn nV/√Hz
VN(PP) 25°C 4 4 µV
input noise current 10 kHz
Equivalent input noise
In f = 1 kHz 25°C 0.01 0.01 pA/√Hz
current
RS = 1 kΩ, RL = 2 kΩ,
f = 1 kHz
25°C 3 3
VI = 10 mV,
V RL = 2 kΩ,
kΩ
CL = 25 pF
F, See Figure 4
85°C 2.5 2.6
25°C 60 63
Phase margin at unity mV
VI = 10 mV, kΩ
RL = 2 kΩ,
φm –40°C 58 61 deg
gain CL = 25 pF,
F, See Figure 4
85°C 60 63

TL05x, TL05xA

TL054C, TL054AC
25°C 0.64 5.5 0.56 4
TL054C
Full range 7.7 6.2
25°C 0.57 3.5 0.5 1.5
TL054AC
Full range 5.7 3.7
VO = 0
0,
VIC = 0, 25°C to
TL054C 25 23
Temperature coefficient RS = 50 Ω 70°C
aV µV/°C
IO of input offset voltage 25°C to
TL054AC 24 23
70°C
25°C 0.04 0.04 µV/mo
long-term drift‡
VO = 0, VIC = 0, 25°C 4 100 5 100 pA
See Figure 5 70°C 0.02 1 0.025 1 nA
VO = 0, VIC = 0, 25°C 20 200 30 200 pA
See Figure 5 70°C 0.15 4 0.2 4 nA
–1 –2.3 –11 –12.3
25°C to to to to
VICR V
Full range to to
4 11
25°C 3 4.2 13 13.9
RL = 10 kΩ
VOM
OM+ V
RL = 2 kΩ
Full range 2.5 11.5
25°C –2.5 –3.5 –12 –13.2
RL = 10 kΩ
Maximum negative
VOM
OM– V
RL = 2 kΩ
25°C 25 72 50 133
Large-signal
L i l differential
diff ti l
AVD RL = 2 kΩ 0°C 30 88 60 173 V/mV
voltage am lification§
amplification
70°C 20 57 30 85
25°C 65 84 75 92
Common-mode
min
CMRR 0°C 65 84 75 92 dB
0, RS = 50 Ω
70°C 65 84 75 93
25°C 75 99 75 99
Supply-voltage
Supply voltage rejection VCC± = ±5 V to ±15 V,
V
kSVR 0°C 75 99 75 99 dB
ratio (∆VCC±/∆VIO) VO = 0
0, RS = 50 Ω
70°C 75 99 75 99
25°C 8.1 11.2 8.4 11.2
Supply current
ICC VO = 0, No load 0°C 8.2 12.8 8.5 12.8 mA
am lifiers)
(four amplifiers)
70°C 7.9 11.2 8.2 11.2
‡ Typical values are based on the input offset-voltage shift observed through 168 hours of operating life test at TA = 150°C, extrapolated to
§ For VCC± = ±5 V, VO = ±2.3 V, at VCC± = ±15 V, VO = ±10 V.B

TL05x, TL05xA

TL054C, TL054C
Positive slew rate 25°C 15.4 10 17.8
SR+
at unity gain 0°C 15.7 8 17.9
RL = 2 kΩ, CL = 100 pF, 70°C 14.4 8 17.5
V/µs
Negative
g slew rate at See Figure 1 and Note 7 25°C 13.9 10 15.9
SR
SR–
unity gain‡ 0°C 14.3 8 16.1
70°C 13.3 8 15.5
25°C 55 56
70°C 63 63
VI(PP) = ±10 mV, ns
25°C 55 57
RL = 2 kΩ,
kΩ
CL = 100 pFF,
25°C 24% 19%
Overshoot factor 0°C 24% 19% %
70°C 24% 19
Equivalent
Vn nV/√Hz
VN(PP) 25°C 4 4 µV
Equivalent input
In f = 1 kHz 25°C 0.01 0.01 pA/√Hz
noise current
Total harmonic RS = 1 kΩ, RL = 2 kΩ,
THD 25°C 0.003 0.003 %
distortion¶ f = 1 kHz
25°C 2.7 2.7
VI = 10 mV,
mV RL = 2 kΩ,
kΩ
B1 Unity-gain bandwidth 0°C 3 3 MHz
CL = 25 pF
F, See Figure 4
70°C 2.4 2.4
25°C 61 64
Phase margin at VI = 10 mV,
mV RL = 2 kΩ
kΩ,
φm 0°C 60 64 deg
unity gain CL = 25 pF
F, See Figure 4
70°C 61 63

TL05x, TL05xA

TL054I, TL054AI
25°C 0.64 5.5 0.56 4
TL054I
Full range 8.8 7.3
VIO Input
In ut offset voltage mV
25°C 0.57 3.5 0.5 1.5
TL054AI
Full range 6.8 4.8
VO = 0
0,
VIC = 0, 25°C to
TL054I 25 24
Temperature coefficient of RS = 50 Ω 85°C
aV input offset voltage
µV/°C
IO 25°C to
TL054AI 25 23
85°C
Input offset voltage
25°C 0.04 0.04 µV/mo
long-term drift‡
VO = 0, VIC = 0, 25°C 4 100 5 100 pA
See Figure 5 85°C 0.06 10 0.07 10 nA
VO = 0, VIC = 0, 25°C 20 200 30 200 pA
See Figure 5 85°C 0.6 20 0.7 20 nA
–1 –2.3 –11 –12.3
25°C to to to to
VICR V
Full range to to
4 11
25°C 3 4.2 13 13.9
RL = 10 kΩ
VOM
OM+ V
RL = 2 kΩ
Full range 2.5 11.5
25°C –2.5 –3.5 –12 –13.2
RL = 10 kΩ
Maximum negative
VOM
OM– V
RL = 2 kΩ
25°C 25 72 50 133
Large-signal
L i l differential
diff ti l
AVD RL = 2 kΩ –40°C 30 101 60 212 V/mV
voltage am lification§
amplification
85°C 20 50 30 70
25°C 65 84 75 92
Common mode
Common-mode min
VIC = VICRmin,
CMRR –40°C 65 83 75 92 dB
0, RS = 50 Ω
85°C 65 84 75 93
25°C 75 99 75 99
Supply-voltage
Supply voltage rejection VCC± = ±5 V to ±15 V,
V
kSVR –40°C 75 98 75 99 dB
ratio (∆VCC±/∆VIO) VO = 0
0, RS = 50 Ω
85°C 75 99 75 99
25°C 8.1 11.2 8.4 11.2
Supply current
ICC VO = 0, No load –40°C 7.9 12.8 8.2 12.8 mA
am lifiers)
(four amplifiers)
85°C 7.6 11.2 7.9 11.2
‡ Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150°C, extrapolated to
§ For VCC± = ±5 V, VO = ±2.3 V, at VCC± = ±15 V, VO = ±10 V.

TL05x, TL05xA

TL054I, TL054AI
Positive slew rate 25°C 15.4 10 17.8
SR+
at unity gain –40°C 16.4 8 18
RL = 2 kΩ, CL = 100 pF, 85°C 14 8 17.3
V/µs
Negative
g slew rate at See Figure 1 25°C 13.9 10 15.9
SR
SR–
unity gain‡ –40°C 14.7 8 16.1
85°C 13 8 15.3
25°C 55 56
85°C 64 65
ns
VI(PP) = ±10 mV, RL = 2 kΩ, 25°C 55 57
tf Fall time CL = 100 pF, –40°C 51 53
25°C 24 19
Overshoot factor –40°C 24 19 %
85°C 24 19
Equivalent
Vn nV/√Hz
VN(PP) 25°C 4 4 µV
Equivalent input
In f = 1 kHz 25°C 0.01 0.01 pA/√Hz
noise current
RS = 1 kΩ, RL = 2 kΩ,
THD Total harmonic distortion¶ 25°C 0.003% 0.003% %
f = 1 kHz
25°C 2.7 2.7
mV
VI = 10 mV, kΩ
RL = 2 kΩ,
CL = 25 pF
F, See Figure 4
85°C 2.3 2.4
25°C 61 64
Phase margin at VI = 10 mV,
mV RL = 2 kΩ
kΩ,
φm –40°C 59 62 deg
unity gain CL = 25 pF
F, See Figure 4
85°C 61 64

TL05x, TL05xA
PARAMETER MEASUREMENT INFORMATION
VCC+
– Overshoot
+ VO
VI 90%
VCC–
CL RL
(see Note A)
10%
NOTE A: CL includes fixture capacitance. tr
Figure 1. Slew Rate, Rise/Fall Time, Figure 2. Rise-Time and Overshoot

and Overshoot Test Circuit Waveform
2 kΩ 10 kΩ
VCC+ VCC+
–
– VI
+ VO 100 Ω + VO
VCC– VCC–
RS RS CL RL
(see Note A)
NOTE A: CL includes fixture capacitance.

Figure 4. Unity-Gain Bandwidth and
Figure 3. Noise-Voltage Test Circuit Phase-Margin Test Circuit
typical values VCC+

Ground Shield
–
Typical values, as presented in this data sheet +
represent the median (50% point) of device
parametric performance.
VCC–
pA pA
input bias and offset current
At the picoamp-bias-current level typical of the
TL05x and TL05xA, accurate measurement of the Figure 5. Input-Bias and Offset-Current Test Circuit
bias current becomes difficult. Not only does this
measurement require a picoammeter, but
test-socket leakages easily can exceed the actual device bias currents. To accurately measure these small
currents, Texas Instruments uses a two-step process. The socket leakage is measured using picoammeters
with bias voltages applied, but with no device in the socket. The device then is inserted in the socket, and a
second test that measures both the socket leakage and the device input bias current is performed. The two
measurements then are subtracted algebraically to determine the bias current of the device.
noise
Because of the increasing emphasis on low noise levels in many of today’s applications, the input noise voltage
density is sample tested at f = 1 kHz. Texas Instruments also has additional noise-testing capability to meet
specific application requirements. Please contact the factory for details.

TL05x, TL05xA
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
VIO Input offset voltage Distribution 6–11
aV Temperature coefficient of input offset voltage Distribution 12, 13, 14
IO
vs Common-mode input voltage 15
vs Free-air temperature 16
IIO Input offset current vs Free-air temperature 16
vs Supply voltage 17
VIC Common-mode input voltage range limits
VO Output voltage vs Differential input voltage 19, 20
VOM Maximum peak output voltage vs Output current 25, 26
vs Free-air temperature 27, 28
VO(PP) Maximum peak-to-peak output voltage vs Frequency 22, 23, 24
vs Load resistance 29
AVD Large-signal differential voltage amplification vs Frequency 30
vs Free-air temperature 31, 32, 33
vs Frequency 34, 35
CMRR Common-mode rejection ratio
zo Output impedance vs Frequency 37
kSVR Supply-voltage rejection ratio vs Free-air temperature 38
IOS Short-circuit output current vs Time 40
vs Supply voltage 42, 43, 44
ICC Supply current
vs Load resistance 48–53
SR Slew rate
vs Free-air temperature 54–59
Overshoot factor vs Load capacitance 60
Vn Equivalent input noise voltage vs Frequency 61, 62
THD Total harmonic distortion vs Frequency 63
B1 Unity-gain bandwidth
φm Phase margin vs Load capacitance 73, 74, 75
Phase shift vs Frequency 30
Voltage-follower small-signal pulse response vs Time 79
Voltage-follower large-signal pulse response vs Time 80

TL05x, TL05xA
DISTRIBUTION OF TL051 DISTRIBUTION OF TL051A

INPUT OFFSET VOLTAGE INPUT OFFSET VOLTAGE
16 20
ÎÎÎÎÎÎÎÎÎÎ
433 Units Tested From 1 Wafer Lot 393 Units Tested From 1 Wafer Lot
VCC± = ±15 V VCC± = ±15 V
12
TA = 25°C
P Package
16
TA = 25°C
P Package
Percentage of Units – %
12
4
4
0 0
–1.5 –1.1 –0.9 –0.6 –0.3 0 0.3 0.6 0.9 1.1 1.5 –900 –600 –300 0 300 600 900
VIO – Input Offset Voltage – mV VIO – Input Offset Voltage – µV
Figure 6 Figure 7

15 20
476 Amplifiers Tested From 1 Wafer Lot 403 Amplifiers Tested From 1 Wafer Lot
VCC± = ±15 V VCC± = ±15 V
TA = 25°C TA = 25°C
12 P Package
Percentage of Amplifiers – %
P Package 15
10
5
3
0 0
–1.5 –1.2 –0.9 –0.6 –0.3 0 0.3 0.6 0.9 1.2 1.5 –900 –600 –300 0 300 600 900
VIO – Input Offset Voltage – mV VIO – Input Offset Voltage – µV
Figure 8 Figure 9

TL05x, TL05xA

30 15
1140 Amplifiers Tested From 3 Wafer Lots 1048 Amplifiers Tested From 3 Wafer Lots
VCC± = ±15 V VCC± = ±15 V
25 TA = 25°C TA = 25°C
12 N Package
N Package
20
9
15
6
10
3
5
0 0
–4 –3 –2 –1 0 1 2 3 4 –1.8 –1.2 –0.6 0 0.6 1.2 1.8
VIO – Input Offset Voltage – mV VIO – Input Offset Voltage – mV
Figure 10 Figure 11
DISTRIBUTION OF TL051 DISTRIBUTION OF TL052

ÎÎÎÎÎÎÎÎÎÎÎ
TEMPERATURE COEFFICIENT TEMPERATURE COEFFICIENT
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ
20 20
172 Amplifiers Tested From 2 Wafer Lots
120 Units Tested From 2 Wafer Lots VCC± = ±15 V
VCC± = ±15 V TA = 25°C to 125°C
TA = 25°C to 125°C
16 P Package
P Package 15 Outlier: One Unit at –34.6 µV/°C

12
10
8
5
4
0
–25 –20 –15 –10 –5 0 5 10 15 20 25 0
–30 –20 –10 0 10 20 30
aV – Temperature Coefficient – µV/°C a V – Temperature Coefficient – µV/°C
IO IO
Figure 12 Figure 13

TL05x, TL05xA
DISTRIBUTION OF TL054 INPUT BIAS CURRENT

INPUT OFFSET VOLTAGE vs
ÎÎÎÎÎÎÎÎÎÎÎÎ
TEMPERATURE COEFFICIENT COMMON-MODE INPUT VOLTAGE
ÎÎÎÎÎÎÎÎÎÎÎÎ
50 10
324 Amplifiers Tested From 3 Wafer Lots
VCC± = ±15 V VCC± = ±15 V
TA = 25°C to 125°C TA = 25°C
40 N Package
IB – Input Bias Current – nA

5
30
20
–5
I
10
0 –10
–60 –40 –20 0 20 40 60 –15 –10 –5 0 5 10 15
aV – Temperature Coefficient – µV/°C VIC – Common-Mode Input Voltage – V
IO
Figure 14 Figure 15
INPUT BIAS CURRENT AND COMMON-MODE

INPUT OFFSET CURRENT† INPUT VOLTAGE RANGE LIMITS
vs vs
FREE-AIR TEMPERATURE SUPPLY VOLTAGE
16
IB and IO – Input Bias and Offset Currents – nA
100
VCC± = ±15 V TA = 25°C
VO = 0 12
VIC – Common-Mode Input Voltage – V
VIC = 0
10
ÎÎÎÎÎ
8
Positive Limit
IIB
4
1
ÎÎÎÎÎ
0
IIO
Negative Limit
0.1 –4
–8
0.01
I
–12
I
0.001 –16
25 45 65 85 105 125 0 2 4 6 8 10 12 14 16
TA – Free-Air Temperature – °C |VCC±| – Supply Voltage – V
Figure 16 Figure 17
† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.

TL05x, TL05xA
COMMON-MODE
INPUT VOLTAGE RANGE LIMITS† OUTPUT VOLTAGE
vs vs
FREE-AIR TEMPERATURE DIFFERENTIAL INPUT VOLTAGE
ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎ
20 5
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
VCC± = ±15 V VCC± = ±5 V
4 TA = 25°C
ÎÎÎÎÎ
15
VIC – Common-Mode Input Voltage – V
Positive Limit 3
10
2
VO – Output Voltage – V
5 1
0
ÎÎÎÎ
0
ÎÎÎÎ
–1 RL = 600 Ω
ÎÎÎÎÎ ÎÎÎÎ
–5
RL = 1 kΩ
ÎÎÎÎÎ ÎÎÎÎÎ
–2
–10 Negative Limit
ÎÎÎÎÎ
–3 RL = 2 kΩ
–15 RL = 10 kΩ
–4
–5
–20
–75 –50 –25 0 25 50 75 100 125 –200 –100 0 100 200
TA – Free-Air Temperature – °C VID – Differential Input Voltage – µV
Figure 18 Figure 19
OUTPUT VOLTAGE
MAXIMUM PEAK OUTPUT VOLTAGE
vs
vs
ÎÎÎÎÎ
DIFFERENTIAL INPUT VOLTAGE
SUPPLY VOLTAGE
15
ÎÎÎÎÎ
ÎÎÎÎ
16
VCC± = ±15 V TA = 25°C VOM+
TA = 25°C
VOM – Maximum Peak Output Voltage – V
10 12
RL = 10 kΩ
8
5 RL = 2 kΩ
4
ÁÁÁÁ
0
0
ÁÁÁÁ
ÎÎÎÎ
RL = 600 Ω –4
ÁÁÁÁ
ÎÎÎÎ
–5
RL = 1 kΩ RL = 2 kΩ
ÁÁÁÁ
ÎÎÎÎ
RL = 2 kΩ –8
–10 RL = 10 kΩ RL = 10 kΩ
–12
VOM–
–15
–16
–400 –200 0 200 400 0 2 4 6 8 10 12 14 16
VID – Differential Input Voltage – µV |VCC±| – Supply Voltage – V
Figure 20 Figure 21

TL05x, TL05xA
MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE

MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE†
vs
vs
ÁÁÁÁ
FREQUENCY
FREQUENCY
VO(PP) – Maximum Peak-to-Peak Output Voltage – V

30
ÁÁÁÁÁ ÁÁÁÁ
30
ÁÁÁÁÁ ÁÁÁÁ
VCC± = ±15 V VCC± = ±15 V
TA = 25°C
25
25
20 20
15
15
ÁÁÁÁÁ
TA = 125°C
TA = –55°C
ÁÁÁÁÁ
10
10
VCC± = ±5 V VCC± = ±5 V
5 5
0
0 10 k 100 k 1M 10 M
10 k 100 k 1M 10 M
f – Frequency – Hz f – Frequency – Hz
Figure 22 Figure 23
MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE MAXIMUM PEAK OUTPUT VOLTAGE
ÁÁÁÁÁ
vs vs
FREQUENCY OUTPUT CURRENT
ÁÁÁÁ ÁÁÁÁÁ
30
5
VCC± = ±5 V
ÁÁÁÁ ÁÁÁÁÁ
RL = 10 kΩ
RL = 10 kΩ
|VOM| – Maximum Peak Output Voltage – V
TA = 25°C
ÁÁÁÁÁ ÁÁÁÁÁ
25 TA = 25°C
ÁÁÁÁÁ
4
VCC± = ±15 V
20
3
ÁÁÁ
ÁÁÁ
15 VOM+
ÁÁÁ
ÁÁÁÁÁ ÁÁÁ
2
10 VOM–
5 ÁÁÁÁÁ VCC± = ±5 V
1
0
0
10 k 100 k 1M 10 M 0 2 4 6 8 10 12 14 16 18 20
f – Frequency – Hz |IO| – Output Current – mA
Figure 24 Figure 25

TL05x, TL05xA
MAXIMUM PEAK OUTPUT VOLTAGE MAXIMUM PEAK OUTPUT VOLTAGE†

vs vs
ÁÁÁÁÁ
OUTPUT CURRENT FREE-AIR TEMPERATURE
ÁÁÁÁÁ
16 5
VOM+ RL = 10 kΩ
VCC± = ±15 V
ÁÁÁÁÁ
4
|VOM| – Maximum Peak Output Voltage – V
V OM – Maximum Peak Output Voltage – V

14 RL = 10 kΩ
ÁÁÁÁÁ
RL = 2 kΩ
TA = 25°C 3
ÁÁÁÁ
12
2
ÁÁÁÁ
VOM+
10
ÁÁÁ
1
VCC± = ±5 V
ÁÁÁ
8 0
VOM–
6
–1
ÁÁÁ
4
–2
–3
ÁÁÁ VOM–
RL = 2 kΩ
2 –4
RL = 10 kΩ
0 –5
0 5 10 15 20 25 30 35 40 45 50 –75 –50 –25 0 25 50 75 100 125
|IO| – Output Current – mA TA – Free-Air Temperature – °C
Figure 26 Figure 27
LARGE-SIGNAL DIFFERENTIAL VOLTAGE

MAXIMUM PEAK OUTPUT VOLTAGE† AMPLIFICATION
vs vs
FREE-AIR TEMPERATURE LOAD RESISTANCE
16 250
RL = 10 kΩ
VO = ±1 V
A VD – Differential Voltage Amplification – V/mV
ÁÁÁ
TA = 25°C
V OM – Maximum Peak Output Voltage – V
12
ÁÁÁ
VOM+ RL = 2 kΩ
200
8 VCC± = ±15 V
4
150
VCC± = ±15 V
0
VCC± = ±5 V
100
–4
ÁÁÁ
ÁÁÁ
–8
VOM– RL = 2 kΩ 50
–12
RL = 10 kΩ
–16 0
–75 –50 –25 0 25 50 75 100 125 0.4 1 4 10 40 100
TA – Free-Air Temperature – °C RL – Load Resistance – kΩ
Figure 28 Figure 29

TL05x, TL05xA
AMPLIFICATION AND PHASE SHIFT
vs
FREQUENCY
106

VCC± = ±15 V
105 RL = 2 kΩ 0°
CL = 25 pF
TA = 25°C
104 30°
AVD
φ m – Phase Shift
103 60°
102 90°
Phase Shift
101 120°
1 150°
0.1 180°
10 100 1k 10 k 100 k 1M 10 M
f – Frequency – Hz
Figure 30
TL051 AND TL052 TL054

LARGE-SIGNAL DIFFERENTIAL LARGE-SIGNAL DIFFERENTIAL
VOLTAGE AMPLIFICATION† VOLTAGE AMPLIFICATION†
vs vs
FREE-AIR TEMPERATURE FREE-AIR TEMPERATURE
1000 1000
VCC± = ±5 V VCC± = ±5 V
VO = ±2.3 V VO = ±2.3 V
400 400
RL = 10 kΩ
RL = 10 kΩ
100 100
RL = 2 kΩ
RL = 2 kΩ
40 40
10 10
–75 –50 –25 0 25 50 75 100 125 –75 –50 –25 0 25 50 75 100 125
TA – Free-Air Temperature – °C TA – Free-Air Temperature – °C
Figure 31 Figure 32

TL05x, TL05xA

AMPLIFICATION† COMMON-MODE REJECTION RATIO
vs vs
FREE-AIR TEMPERATURE FREQUENCY
1000
ÁÁÁÁÁ 100
ÁÁÁÁÁ
VCC± = ±15 V VCC± = ±5 V
CMRR – Common-Mode Rejection Ratio – dB

VO = 10 V 90 TA = 25°C
400 RL = 10 kΩ 80
70
60
100 50
RL = 2 kΩ
40
40 30
20
10
10 0
–75 –50 –25 0 25 50 75 100 125 10 100 1k 10 k 100 k 1M 10 M
TA – Free-Air Temperature – °C f – Frequency – Hz
Figure 33 Figure 34
COMMON-MODE REJECTION RATIO COMMON-MODE REJECTION RATIO†

vs vs
FREQUENCY FREE-AIR TEMPERATURE
100 100
VCC± = ±15 V
VIC = VICRMin
90
TA = 25°C
95
80 VCC± = ±15 V
70
90
60
50 85
VCC± = ±5 V
40
80
30
20
75
10
0 70
10 100 1k 10 k 100 k 1M 10 M –75 –50 –25 0 25 50 75 100 125
f – Frequency – Hz TA – Free-Air Temperature – °C
Figure 35 Figure 36

TL05x, TL05xA
OUTPUT IMPEDANCE SUPPLY-VOLTAGE REJECTION RATIO†

vs vs
FREQUENCY FREE-AIR TEMPERATURE
100 110
VCC± = ±5 V to ±15 V
SVR – Supply-Voltage Rejection Ratio – dB

40 AVD = 100
106
zo – Output Impedance – Ω
10
AVD = 10 102
4
98
1
ÁÁ
AVD = 1
0.4 94
ÁÁ
VCC± = ±15 V
kkSVR
TA = 25°C
0.1
1k 10 k
ro (open loop) ≈ 250 Ω
100 k 1M
ÁÁ 90
–75 –50 –25 0 25 50 75 100 125
f – Frequency – Hz TA – Free-Air Temperature – °C
Figure 37 Figure 38
SHORT-CIRCUIT OUTPUT CURRENT SHORT-CIRCUIT OUTPUT CURRENT

vs vs
SUPPLY VOLTAGE TIME
60 60
VO = 0 VID = 100 mV
OS – Short-Circuit Output Current – mA
I OS – Short-Circuit Output Current – mA
TA = 25°C
40 40
VID = 100 mV
20 20
0 –20
–20 –40
VID = –100 mV
ÁÁ VID = –100 mV
ÁÁ –40
ÁÁ –60
IIOS
ÁÁ ÁÁ
IOS
VCC± = ±15 V
TA = 25°C
–60 0
0 2 4 6 8 10 12 14 16 0 10 20 30 40 50 60
|VCC±| – Supply Voltage – V t – Time – s
Figure 39 Figure 40

TL05x, TL05xA
TL051
SHORT-CIRCUIT OUTPUT CURRENT† SUPPLY CURRENT†
vs vs
60 3
VCC± = ±15 V
ÎÎÎÎÎ
OS – Short-Circuit Output Current – mA
40 2.5
ÎÎÎÎÎ
VID = 100 m V
TA = 25°C
CC – Supply Current – mA
VCC± = ±5 V
20 2 TA = –55°C
TA = 125°C
0 1.5
VCC± = ±5 V
–20
ÎÎÎÎÎÎ ÁÁ 1
ÁÁ
VID = –100 m V
IICC
ÁÁ ÁÁ
VCC± = ±15 V
0.5
ÁÁ
–40
IIOS
VO = 0
VO = 0 No Load
–60 0
–75 –50 –25 0 25 50 75 100 125 0 2 4 6 8 10 12 14 16
Figure 41 Figure 42
TL052
TL054
SUPPLY CURRENT†
SUPPLY CURRENT†
vs
vs
SUPPLY VOLTAGE
SUPPLY VOLTAGE
5
10
4 8
ÎÎÎÎÎ
TA = 25°C
TA = –55°C TA = 25°C
3
TA = 125°C
6
ÎÎÎÎÎ
TA = –55°C
TA = 125°C
ÁÁ
2 4
ÁÁ ÁÁ
IICC
ÁÁ ÁÁ
IICC
1 2
VO = 0 VO = 0
No Load No Load
0 0
0 2 4 6 8 10 12 14 16 0 2 4 6 8 10 12 14 16
|VCC±| – Supply Voltage – V |VCC±| – Supply Voltage – V
Figure 43 Figure 44

TL05x, TL05xA
TL052
TL051
SUPPLY CURRENT†
SUPPLY CURRENT†
vs
vs
FREE-AIR TEMPERATURE
5
3
2.5 4
VCC± = ±15 V
VCC± = ±15 V
2 VCC± = ±5 V
VCC± = ±5 V 3
1.5
ÁÁ
2
ÁÁ ÁÁ
1
ÁÁ ÁÁ IICC
IICC
1
0.5
VO = 0 VO = 0
No Load No Load
0 0
–75 –50 –25 0 25 50 75 100 125 –75 –50 –25 0 25 50 75 100 125
Figure 45 Figure 46
TL054 TL051
SUPPLY CURRENT† SLEW RATE
vs vs
FREE-AIR TEMPERATURE LOAD RESISTANCE
ÎÎÎÎÎÎ
10 25
ÎÎÎÎÎÎ
VCC± = ±15 V SR+
8
ÎÎÎÎÎÎ 20
ÎÎÎÎÎÎ
VCC± = ±5 V
SR – Slew Rate – V/µs
SR–
6 15
10
4
ÁÁ
ÁÁ
IICC
VCC± = ±5 V
ÁÁ
2 5
CL = 100 pF
VO = 0 TA = 25°C
No Load See Figure 1
0 0
–75 –50 –25 0 25 50 75 100 125 0.4 1 4 10 40 100
TA – Free-Air Temperature – °C RL – Load Resistance – kΩ
Figure 47 Figure 48

TL05x, TL05xA
TL052 TL054
SLEW RATE SLEW RATE
vs vs
LOAD RESISTANCE LOAD RESISTANCE
25 25
ÎÎ
SR+
20 20 SR+

SR–
15 15
SR–
10
10
VCC± = ±5 V VCC± = ±5 V
5 5
CL = 100 pF CL = 100 pF
TA = 25°C TA = 25°C
See Figure 1 See Figure 1
0 0
0.4 1 4 10 40 100 0.4 1 4 10 40 100
RL – Load Resistance – kΩ RL – Load Resistance – kΩ
Figure 49 Figure 50
TL051 TL052
SLEW RATE SLEW RATE
vs vs
LOAD RESISTANCE LOAD RESISTANCE
30 25
SR+
SR+
25 20
SR–
SR–
20
15
15
10
10
VCC± = ±15 V VCC± = ±15 V
CL = 100 pF 5 CL = 100 pF
5 TA = 25°C
TA = 25°C
0 0
0.4 1 4 10 40 100 0.4 1 4 10 40 100
RL – Load Resistance – kΩ RL – Load Resistance – kΩ
Figure 51 Figure 52

TL05x, TL05xA
TL054 TL051
SLEW RATE SLEW RATE†
vs vs
LOAD RESISTANCE FREE-AIR TEMPERATURE
25 30
SR+
25
20
SR+

SR– 20
15
15 SR–
10
10
VCC± = ±5 V
VCC± = ±5 V
5 CL = 100 pF
5 RL = 2 kΩ
TA = 25°C
See Figure 1
0 0
0.4 1 4 10 40 100 –75 –50 –25 0 25 50 75 100 125
RL – Load Resistance – kΩ TA – Free-Air Temperature – °C
Figure 53 Figure 54
TL052 TL054
SLEW RATE† SLEW RATE†
vs vs
25 20
SR+
20
SR+
15
SR–
15
SR–
10
10
VCC± = ±5 V 5 VCC± = ±5 V
5 RL = 2 kΩ RL = 2 kΩ
CL = 100 pF CL = 100 pF
0 0
–75 –50 –25 0 25 50 75 100 125 –75 –50 –25 0 25 50 75 100 125
Figure 55 Figure 56

TL05x, TL05xA
TL051 TL052
SLEW RATE† SLEW RATE†
vs vs
30 25
SR+ SR+
25
20

20 SR–
SR– 15
15
10
10
VCC± = ±15 V VCC± = ±15 V

5
5 RL = 2 kΩ RL = 2 kΩ
CL = 100 pF CL = 100 pF
0 0
–75 –50 –25 0 25 50 75 100 125 –75 –50 –25 0 25 50 75 100 125
Figure 57 Figure 58
TL054
SLEW RATE† OVERSHOOT FACTOR
vs vs
FREE-AIR TEMPERATURE LOAD CAPACITANCE
20 50
SR+
ÎÎÎÎ
SR– 40
ÎÎÎÎ
15
Overshoot Factor – %
VCC± = ±5 V
30
10
ÎÎÎÎÎ VCC± = ±15 V
ÎÎÎÎÎ
20
ÎÎÎÎÎ VI(PP) = ±10 mV
ÎÎÎÎÎ
5 RL = 2 kΩ
VCC± = ±15 V 10
ÎÎÎÎÎ
RL = 2 kΩ TA = 25°C
CL = 100 pF See Figure 1
See Figure 1
0 0
–75 –50 –25 0 25 50 75 100 125 0 50 100 150 200 250 300
TA – Free-Air Temperature – °C CL – Load Capacitance – pF
Figure 59 Figure 60

TL05x, TL05xA
TL052 AND TL054

TL051
EQUIVALENT INPUT NOISE VOLTAGE
EQUIVALENT INPUT NOISE VOLTAGE
vs
vs
FREQUENCY
ÁÁÁÁÁ
FREQUENCY
100
ÁÁÁÁÁ
100
Vn – Equivalent Input Noise Voltage – nV/ Hz

Vn – Equivalent Input Noise Voltage – nV/ Hz
VCC± = ±15 V
ÁÁÁÁÁ
VCC± = ±15 V
RS = 20 Ω 70 RS = 20 Ω
ÁÁÁÁÁ
70 TA = 25°C
TA = 25°C
50
50
40
40
30
30
20
20
10
10 10 100 1k 10 k 100 k
10 100 1k 10 k 100 k
Figure 61 Figure 62
TL051
TOTAL HARMONIC DISTORTION
UNITY-GAIN BANDWIDTH
vs
vs
FREQUENCY
SUPPLY VOLTAGE
1
3.2
VCC± = ±15 V
0.4 AVD = 1
THD – Total Harmonic Distortion – %
VO(RMS) = 6 V
B1 – Unity-Gain Bandwidth – MHz
TA = 25°C 3.1
0.1
3
0.04
2.9
0.01
VI = 10 mV
RL = 2 kΩ
0.004 CL = 25 pF
2.8
TA = 25°C
See Figure 4
0.001
100 1k 10 k 100 k 2.7
0 2 4 6 8 10 12 14 16
|VCC±| – Supply Voltage – V
Figure 63 Figure 64

TL05x, TL05xA
TL052 TL054
UNITY-GAIN BANDWIDTH UNITY-GAIN BANDWIDTH
vs vs
SUPPLY VOLTAGE SUPPLY VOLTAGE
3.2 2.9
3.1 2.8

3 2.7
2.9
ÁÁÁÁ 2.6
ÎÎÎÎ
ÁÁÁÁÁ
ÁÁÁÁ
VI = 10 mV
ÁÁÁÁÁ
ÎÎÎÎ
ÎÎÎÎÎ VI = 10 mV
ÁÁÁÁ ÁÁÁÁÁ
ÎÎÎÎÎÎ
ÎÎÎÎÎ
ÁÁÁÁ ÁÁÁÁÁ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎ
CL = 25 pF CL = 25 pF
2.8 2.5
TA = 25°C TA = 25°C
ÁÁÁÁ ÁÁÁÁÁ
ÎÎÎÎÎÎÎ
2.7 2.4
4 6 8 10 12 14 16 0 2 4 6 8 10 12 14 16
Figure 65 Figure 66
TL051 TL052
UNITY-GAIN BANDWIDTH† UNITY-GAIN BANDWIDTH†
vs vs
4 4
VCC± = ±15 V
3 3
VCC± = ±5 V
2 2
VCC± = ±5 V to ±15 V
VI = 10 mV
VI = 10 mV RL = 2 kΩ
1 1
RL = 2 kΩ CL = 25 pF
CL = 25 pF TA = 25°C
0 0
–75 –50 –25 0 25 50 75 100 125 –75 –50 –25 0 25 50 75 100 125
Figure 67 Figure 68

TL05x, TL05xA
TL054 TL051
UNITY-GAIN BANDWIDTH† PHASE MARGIN
vs vs
4 65°
63°
3
φ m – Phase Margin
61°
59°
VCC± = ±5 V to ±15 V
VI = 10 mV
VI = 10 mV
1 RL = 2 kΩ
57° RL = 2 kΩ
CL = 25 pF
CL = 25 pF
TA = 25°C
TA = 25°C
See Figure 4
See Figure 4
0 55°
–75 –50 –25 0 25 50 75 100 125 0 2 4 6 8 10 12 14 16
Figure 69 Figure 70
TL052 TL054
PHASE MARGIN PHASE MARGIN
vs vs
SUPPLY VOLTAGE SUPPLY VOLTAGE
65° 65°
63° 63°
61° 61°
ÁÁÁÁÁ
59° 59°
VI = 10 mV
ÁÁÁÁÁVI = 10 mV
57°
RL = 2 kΩ
57°
ÁÁÁÁÁRL = 2 kΩ
ÁÁÁÁÁ
CL = 25 pF CL = 25 pF
TA = 25°C TA = 25°C
55°
4 6 8 10
See Figure 4
12 14 16
55°
0 2 4 6 8
ÁÁÁÁÁ
10
See Figure 4
12 14 16
Figure 71 Figure 72

TL05x, TL05xA
TL051 TL052
PHASE MARGIN† PHASE MARGIN†
vs vs
LOAD CAPACITANCE LOAD CAPACITANCE
70° 70°
VI = 10 mV VI = 10 mV
65° TA = 25°C TA = 25°C
See Figure 4 65° See Figure 4
ÎÎÎÎÎ
60°
VCC± = ±15 V 60° VCC± = ±15 V

See Note A See Note A
ÎÎÎÎÎ
55°
ÎÎÎÎÎ
VCC± = ±5 V 55° VCC± = ±5 V
50°
50°
45°
40° 45°
0 10 20 30 40 50 60 70 80 90 100 0 10 20 30 40 50 60 70 80 90 100
CL – Load Capacitance – pF CL – Load Capacitance – pF
Figure 73 Figure 74
TL054
PHASE MARGIN†
vs
LOAD CAPACITANCE
70°
VI = 10 mV
RL = 2 kΩ
TA = 25°C
65° See Figure 4
ÎÎÎÎÎ
60°
See Note A
ÎÎÎÎÎ VCC± = ±15 V
55°
ÎÎÎÎÎ
VCC± = ±5 V
50°
45°
0 10 20 30 40 50 60 70 80 90 100
CL – Load Capacitance – pF
Figure 75
† Values of phase margin below a load capacitance of 25 pF were estimated.

TL05x, TL05xA
TL051 TL052
PHASE MARGIN† PHASE MARGIN†
vs vs
65° 65°
VI = 10 mV
VI = 10 mV
RL = 2 kΩ
RL = 2 kΩ
CL = 25 pF
CL = 25 pF
63° See Figure 4 63°
VCC± = ±15 V See Figure 4 VCC± = ±15 V
61° 61°
VCC± = ±5 V
59° 59°
VCC± = ±5 V
57° 57°
55° 55°
–75 –50 –25 0 25 50 75 100 125 –75 –50 –25 0 25 50 75 100 125
Figure 76 Figure 77
TL054
PHASE MARGIN†
vs
65°
63°
VCC± = ±15 V
φ m– Phase Margin
61°
59°
VCC± = ±5 V
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
VI = 10 mV
57° RL = 2 kΩ
ÁÁÁÁÁ
CL = 25 pF
See Figure 4
55°
–75 –50 –25 0 25 50 75 100 125
TA – Free-Air Temperature – °C
Figure 78

TL05x, TL05xA
VOLTAGE-FOLLOWER VOLTAGE-FOLLOWER
SMALL-SIGNAL LARGE-SIGNAL
PULSE RESPONSE PULSE RESPONSE
16 8
12 6
ÁÁÁÁÁ
8
VO – Output Voltage – mV
4
ÁÁÁÁÁ 2
ÁÁÁÁÁ
VCC± = ±15 V
VCC± = ±15 V
RL = 2 kΩ
RL = 2 kΩ
0 0 CL = 100 pF
CL = 100 pF
TA = 25°C
TA = 25°C
–4 –2 See Figure 1
See Figure 1
–8 –4
–12 –6
–16 –8
0 0.2 0.4 0.6 0.8 1.0 1.2 0 1 2 3 4 5 6
t – Time – µs t – Time – µs
Figure 79 Figure 80

TL05x, TL05xA
APPLICATION INFORMATION
output characteristics
All operating characteristics (except bandwidth and phase margin) are specified with 100-pF load capacitance.
The TL05x and TL05xA drive higher capacitive loads; however, as the load capacitance increases, the resulting
response pole occurs at lower frequencies, causing ringing, peaking, or even oscillation. The value of the load
capacitance at which oscillation occurs varies with production lots. If an application appears to be sensitive to
oscillation due to load capacitance, adding a small resistance in series with the load should alleviate the
problem. Capacitive loads of 1000 pF, and larger, may be driven if enough resistance is added in series with
the output (see Figure 81 and Figure 82).
(a) CL = 100 pF, R = 0 (b) CL = 300 pF, R = 0 (c) CL = 350 pF, R = 0
(d) CL = 1000 pF, R = 0 (e) CL = 1000 pF, R = 50 Ω (f) CL = 1000 pF, R = 2 kΩ
Figure 81. Effect of Capacitive Loads
15 V
–
R
VO
5V +
–5 V
–15 V
CL 2 kΩ
(see Note A)
NOTE A: CL includes fixture capacitance.
Figure 82. Test Circuit for Output Characteristics

TL05x, TL05xA
input characteristics
The TL05x and TL05xA are specified with a minimum and a maximum input voltage that, if exceeded at either
input, could cause the device to malfunction.
Because of the extremely high input impedance and resulting low-bias current requirements, the TL05x and
TL05xA are well suited for low-level signal processing; however, leakage currents on printed-circuit boards and
sockets easily can exceed bias current requirements and cause degradation in system performance. It is good
practice to include guard rings around inputs (see Figure 83). These guards should be driven from a
low-impedance source at the same voltage level as the common-mode input.
Unused amplifiers should be connected as grounded unity-gain followers to avoid possible oscillation.
VI +
VO
– VI –
–
VO
+ VO
+
VI
(a) NONINVERTING AMPLIFIER (b) INVERTING AMPLIFIER (c) UNITY-GAIN AMPLIFIER
Figure 83. Use of Guard Rings
noise performance
The noise specifications in operational amplifier circuits are greatly dependent on the current in the first-stage
differential amplifier. The low input-bias current requirements of the TL05x and TL05xA result in a very low
current noise. This feature makes the devices especially favorable over bipolar devices when using values of
circuit impedance greater than 50 kΩ.

TL05x, TL05xA
phase meter
The phase meter in Figure 84 produces an output voltage of 10 mV per degree of phase delay between the two
input signals VA and VB. The reference signal VA must be the same frequency as VB. The TLC3702 comparators
(U1) convert these two input sine waves into ±5-V square waves. Then, R1 and R4 provide level shifting prior
to the SN74HC109 dual J-K flip flops.
Flip-flop U2B is connected as a toggle flip-flop and generates a square wave at one-half the frequency of VB.
Flip-flop U2A also produces a square wave at one-half the input frequency. The pulse duration of U2A varies
from zero to one-half the period, where zero corresponds to zero phase delay between VA and VB and one-half
the period corresponds to VB lagging VA by 360 degrees.
The output pulse from U2A causes the TLC4066 (U3) switch to charge the TL05x (U4) integrator capacitors C1
and C2. As the phase delay approaches 360 degrees, the output of U4A approximates a square wave, and U2A
has an output of almost 2.5 V. U4B acts as a noninverting amplifier with a gain of 1.44 in order to scale the
0- to 2.5-V integrator output to a 0- to 3.6-V output range.
R8 and R10 provide output gain and zero-level calibration. This circuit operates over a 100-Hz to 10-kHz
frequency range.
+5 V
R2 C2
100 kΩ +5 V 0.016 µF
S R6 R7
VA 1J U2A U3 +
R1 10 kΩ 10 kΩ
U1A C1 U4A +
100 kΩ C1 – U4B VO
1K NC R5
10 kΩ 0.016 µF –
R
R9
20 kΩ
R3
100 kΩ S NC R8
2J U2B 50 kΩ
C1 Gain
+5 V
2K
R4
R R10
100 kΩ
10 kΩ
VB Zero
U1B
–5 V
NOTE A: U1 = TLC3702; VCC± = ±5 V

U2 = SN74HC109
U3 = TLC4066
U4, U5 = TL05x; VCC± = ±5 V
Figure 84. Phase Meter

TL05x, TL05xA
precision constant-current source over temperature

A precision current source (see Figure 85) benefits from the high input impedance and stability of Texas
Instruments enhanced-JFET process. A low-current shunt regulator maintains 2.5 V between the inverting input
and the output of the TL05x. The negative feedback then forces 2.5 V across the current-setting resistor R;
therefore, the current to the load simply is 2.5 V divided by R.
Possible choices for the shunt regulator include the LT1004, LT1009, and LM385. If the regulator’s cathode
connects to the operational amplifier output, this circuit sources load current. Similarly, if the cathode connects
to the inverting input, the circuit sinks current from the load. To minimize output current change with temperature,
R should be a metal film resistor with a low temperature coefficient. Also, this circuit must be operated with
split-voltage supplies.
150 pF 150 pF
U2 U2
+15 V +15 V
100 kΩ – 100 kΩ
–
U1 U1
+ +
IO
–15 V II –15 V
Load Load
R R
V = 0 to 10 V V = 0 to –10 V
(a) SOURCE CURRENT LOAD (b) SINK CURRENT LOAD
NOTE A: U1 = 1/2 TL05x

U2 = LM385, LT1004, or LT1009 voltage reference
2.5 V , R = Low-temperature-coefficient metal-film resistor
I=
R
Figure 85. Precision Constant-Current Source

TL05x, TL05xA
instrumentation amplifier with adjustable gain/null

The instrumentation amplifier in Figure 86 benefits greatly from the high input impedance and stable input offset
voltage of the TL05xA. Amplifiers U1A, U1B, and U2A form the actual instrumentation amplifier, while U2B
provides offset null. Potentiometer R1 provides gain adjustment. With R1 = 2 kΩ, the circuit gain equals 100,
while with R1 = 200 kΩ, the circuit gain equals two. The following equation shows the instrumentation amplifier
AV + )
1 ǒ
gain as a function of R1:
R2 R3
R1
) Ǔ
Readjusting the offset null is necessary when the circuit gain is changed. If U2B is needed for another
application, R7 can be terminated at ground. The low input offset voltage of the TL05xA minimizes the dc error
of the circuit. For best matching, all resistors should be one-percent tolerance. The matching between R4, R5,
R6, and R7 controls the CMRR of this application.
The following equation shows the output voltages when the input voltage equals zero. This dc error can be
nulled by adjusting the offset null potentiometer; however, any change in offset voltage over time or temperature
also creates an error. To calculate the error from changes in offset, consider the three offset components in the
equation as delta offsets, rather than initial offsets. The improved stability of Texas Instruments enhanced JFETs
minimizes the error resulting from change in input offset voltage with time. Assuming VI equals zero, VO can
ƪǒ Ǔ ǒ ) Ǔ ǒ ) Ǔ ) ǒ Ǔ ƫ
be shown as a function of the offset voltage:
V + VIO2 1 ) R3 R7 1 R6 R2 R6
ƪ ǒ ) Ǔ ǒ ) Ǔ ) ǒ ) Ǔƫ ) ǒ ) Ǔ
O R1 R5 R7 R4 R1 R4
–V R3 R7 1 R6 R6 1 R2 V 1 R6
IO1 R1 R5 R7 R4 R4 R1 IO3 R4
VI– +
R4 R6
U1A
– 10 kΩ 10 kΩ
100 kΩ
R2
–
200 kΩ
10 MΩ U2A VO
10 turn
+
AV = 2 to 100 10 MΩ
2 kΩ R1
VCC+
R3
100 kΩ
– – 82 kΩ
R5 R7
U1B U2B Offset Null
+
VI+
+ 10 kΩ 10 kΩ 1 kΩ
0.1 µF
82 kΩ
NOTE A: U1 and U2 = TL05xA; VCC± = ±15 V. VCC–
Figure 86. Instrumentation Amplifier

TL05x, TL05xA
high input impedance log amplifier

The low input offset voltage and high input impedance of the TL05xA creates a precision log amplifier (see
Figure 87). IC1 is a 2.5-V, low-current precision, shunt regulator. Transistors Q1 and Q2 must be a closely
matched npn pair. For best performance over temperature, R4 should be a metal-film resistor with a low
temperature coefficient.
In this circuit, U1A serves as a high-impedance unity-gain buffer. Amplifier U1B converts the input voltage to
a current through R1 and Q1. Amplifier U1C, IC1, and R4 form a 1-µA temperature-stable current source that
sets the base-emitter voltage of Q2. U1D amplifies the difference between the base-emitter voltage of Q1 and
ƪ ƫ ȱȧȲ ǒ ȳȧ
Q2 (see Figure 88). The output voltage is given by the following equation:
+ + 1.602
+ – 1 ) R6 Ǔȴ
V
V kT In I where k 1.38 10 –23, q 10 –19,
O R5 q
R1 1 10 –6 and T is Kelvin temperature
Q1 Q2
R4
2.5 MΩ
2N2484
+
R2 +
15 V 10 kΩ _U1C U1D VO
+ R1 _ (see equation above)
U1A + C1
_ R6
VI 10 kΩ U1B
_
150 pF 10 kΩ
R3 R5
10 kΩ
270 kΩ
–15V IC1
NOTE A: U1A through U1D = TL05xA. IC1 = LM385, LT1004, or LT1009 voltage reference
Figure 87. Log Amplifier
–0.1
AVD – Differential Voltage Amplification – dB
–0.15
–0.2
–0.25
–0.3
ÁÁ –0.35
ÁÁ
ÁÁ –0.4
0 1 2 3 4 5
6 7 8 9 10
Figure 88. Output Voltage vs Input Voltage for Log Amplifier

TL05x, TL05xA
analog thermometer
By combining a current source that does not vary over temperature with an instrumentation amplifier, a precise
analog thermometer can be built (see Figure 89). Amplifier U1A and IC1 establish a constant current through
the temperature-sensing diode D1. For this section of the circuit to operate correctly, the TL05x must use split
supplies, and R3 must be a metal-film resistor with a low temperature coefficient.
The temperature-sensitive voltage from the diode is compared to a temperature-stable voltage reference set
by IC2. R4 should be adjusted to provide the correct output voltage when the diode is at a known temperature.
Although this potentiometer resistance varies with temperature, the divider ratio of the potentiometer remains
constant.
Amplifiers U1B, U2A, and U2B form the instrumentation amplifier that converts the difference between the diode
and reference voltage to a voltage proportional to the temperature. With switch S1 closed, the amplifier gain
equals 5 and the output voltage is proportional to temperature in degrees Celsius. With S1 open, the amplifier
gain is 9 and the output is proportional to temperature in degrees Fahrenheit. Every time S1 is changed, R4 must
be recalibrated. By setting S1 correctly, the output voltage equals 10 mV per degree (C or F).
IC1
+ R9 R12
C1 U1B
– 10 kΩ 10 kΩ
150 pF R6
R1 – 10 kΩ
+15 V
100 kΩ U1A
+ R5 R7
5 kΩ 5 kΩ –
R3 10 kΩ
(see Note B) S1 U2B VO
+
(see Note C) (see Note D)
D1
(see Note A) +15 V –15 V
R2 100 kΩ R8
10 kΩ
–
R10
U2A
IC2
+ 10 kΩ
R4
R11
50 kΩ 10 kΩ
NOTES: A. Temperature-sensing diode ≈ (–2 mV/°C)

B. Metal-film resistor (low temperature coefficient)
C. Switch open for °F and closed for °C
D. VO α temperature; 10 mV/°C or 10 mV/°F
E. U1, U2 = TL05x. IC1, IC2 = LM385, LT1004, or LT1009 voltage reference
Figure 89. Analog Thermometer

TL05x, TL05xA
voltage-ratio-to-dB converter
The application in Figure 90 measures the amplitude ratio of two signals, then converts the ratio to decibels (see
Figure 91). The output voltage provides a resolution of 100 mV/dB. The two inputs can be either dc or sinusoidal
ac signals. When using ac signals, both signals should be the same frequency or output glitches will occur. For
measuring two input signals of different frequencies, extra filtering should be added after the rectifiers.
The circuit contains three low-offset TL05xA devices. Two of these devices provide the rectification and
logarithmic conversion of the inputs. The third TL05xA forms an instrumentation amplifier. The stage performing
the logarithmic conversion also requires two well-matched npn transistors.
The input signal first passes through a high-impedance unity-gain buffer U1A (U2A). Then U1B (U2B) rectifies
the input signal at a gain of 0.5, and U1C (U2C) provides a noninverting gain of 2, so that the system gain is
still one. U1D (U2D), R6 (R13), and Q1 (Q2) perform the logarithmic conversion of the rectified input signal. The
instrumentation amplifier formed by U3A, U3B, U3D scales the difference of the two logarithmic voltages by a
gain of 33.6. As a result, the output voltage equals 100 mV/dB. The 1-kΩ potentiometer on the input of U3C
calibrates the zero-dB reference level. The following equations are used to derive the relationship between the
ƪƫ ȱȧ ǒ Ǔ ǒ Ǔȳȧ
input voltage ratio, expressed in decibels, and the output voltage.
+ 20 log
Ȳ + 20
ȴ
V In V – V
A A B
X dB
V In (10)
ƪ ǒ Ǔ ǒ Ǔƫ
B
+ 8.686
ƪ ƫ ƪ ƫ
X dB In V – In V
A B
V
BE(Q1)
+ kTq In
V
A
R I
V
BE(Q2)
+ kTq In
R
V
B
I
ƪ ǒ Ǔ ǒ Ǔƫ
S S
DVBE + VBE(Q1) –VBE(Q2) + kT In V – In V
ƪ ƫ+ ƪ ƫ
q A B
X dB + 8.686
kTńq
V
BE(Q1)
–V
BE(Q2)
336 V
BE(Q1)
–V
BE(Q2)
at 25°C
where
k + 1.38 10 –23, q + 1.602 10 –19, and T is Kelvin temperature

This gives a resolution of 1 V/dB. Therefore, the gain of the instrumentation amplifier is set at 33.6 to obtain
100 mV/dB.

TL05x, TL05xA
R2 2N2484 Q1
VA + R1 10 kΩ
U1A
_ +
20 kΩ U1B + R6
_ R7
D1 U1C
_ +
+ R18 R20
10 kΩ _U1D
R5 10 kΩ U3A
_
10 kΩ 10 kΩ
10 kΩ R16
+
R3 R4 U3D VO
16.3 kΩ _
30 kΩ 10 kΩ
R9 R76
2N2484
VB + R8 10 kΩ 16.3 kΩ
U2A
_ +
20 kΩ U2B + R13 + R19
_ Q2
U2C
_ + R14 U3B
_
D2 10 kΩ U2D 10 kΩ
_
R12 10 kΩ
15 V R21
10 kΩ 10 kΩ
R10 R11 82 kΩ
30 kΩ 10 kΩ +
U3C
_
1 kΩ
C1
82 kΩ
–15 V
NOTE A: U1A through U3D = TL05xA, VCC± = ±15 V. D1 and D2 = 1N914.
Figure 90. Voltage Ratio-to-dB Converter
1
–1
–2
0 1 2 3 4 5 6 7 8 9 10
Ratio – VA/VB
Figure 91. Output Voltage vs the Ratio of the Input Voltages for Voltage-to-dB Converter

TL05x, TL05xA
macromodel information
Macromodel information provided was derived using Microsim Parts, the model-generation software used
with Microsim PSpice. The Boyle macromodel (see Note 6 and subcircuit Figure 92) are generated using the
TL05x typical electrical and operating characteristics at TA = 25°C. Using this information, output simulations
of the following key parameters can be generated to a tolerance of 20% (in most cases):
D Maximum positive output voltage swing D Unity-gain frequency
D Maximum negative output voltage swing D Common-mode rejection ratio
D Slew rate D Phase margin
D Quiescent power dissipation D DC output resistance
D Input bias current D AC output resistance
D Open-loop voltage amplification D Short-circuit output current limit
NOTE 6: G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, “Macromodeling of Integrated Circuit Operational Amplifiers”, IEEE Journal
of Solid-State Circuits, SC-9, 353 (1974).
99
DLN
3 EGND +
VCC+
9 92
FB
+ – 90 91
RSS ISS
RO2 + DLP + –
VB
RP HLIM VLP VLN
+ –
2 10 – – +
IN– VC R2
J1 J2 – C2
DP 6 7
IN+ 53 +
3 11 VLIM
12 DC GCM GA
–
C1 8
RD1 RD2
60 RO1
+ DE
VAD 5
– 54
VCC–
4 – +
VE OUT
.SUBCKT TL05x 1 2 3 4 5 RD1 4 11 3.422E3
C1 11 12 3.988E–12 RD2 4 12 3.422E3
C2 6 7 15.00E–12 R01 8 5 125
DC 5 53 DX R02 7 99 125
DE 54 5 DX RP 3 4 11.11E3
DLP 90 91 DX RSS 10 99 666.7E6
DLN 92 90 DX VB 9 0 DC 0
DP 4 3 DX VC 3 53 DC 3
EGND 99 0 POLY (2) (3,0) (4,0) 0 .5 .5 VE 54 4 DC 3.7
FB 7 99 POLY (5) VB VC VE VLP VLIM 7 8 DC 0
+ VLN 0 2.875E6 –3E6 3E6 3E6 –3E6 VLP 91 0 DC 28
GA 6 0 11 12 292.2E–6 VLN 0 92 DC 28
GCM 0 6 10 99 6.542E–9 .MODEL DX D (IS=800.0E–18)
ISS 3 10 DC 300.0E–6 .MODEL JX PJF (IS=15.00E–12 BETA=185.2E–6
HLIM 90 0 VLIM 1K + VTO=–.1)
J1 11 2 10 JX .ENDS
J2 12 1 10 JX
R2 6 9 100.0E3
Figure 92. Boyle Macromodel and Subcircuit
PSpice and Parts are trademarks of MicroSim Corporation.
Macromodels, simulation models, or other models provided by TI,

directly or indirectly, are not warranted by TI as fully representing all
of the specification and operating characteristics of the
semiconductor product to which the model relates.

PACKAGE OPTION ADDENDUM
www.ti.com 28-Aug-2024
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
TL051ACP OBSOLETE PDIP P 8 TBD Call TI Call TI 0 to 70 TL051ACP

TL051CDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TL051C Samples
TL051CP ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 TL051CP Samples
TL051CPE4 ACTIVE PDIP P 8 50 TBD Call TI Call TI 0 to 70 Samples
TL052ACDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 052AC Samples
TL052ACP ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 TL052ACP Samples
TL052AID OBSOLETE SOIC D 8 TBD Call TI Call TI -40 to 85 052AI

TL052AIDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 052AI Samples
TL052AIP ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 TL052AIP Samples
TL052CD OBSOLETE SOIC D 8 TBD Call TI Call TI 0 to 70 TL052C

TL052CDRE4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TL052C Samples
TL052CDRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TL052C Samples
TL052CP ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 TL052CP Samples
TL052CPSR ACTIVE SO PS 8 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 T052 Samples
TL052ID OBSOLETE SOIC D 8 TBD Call TI Call TI -40 to 85 TL052I

TL052IDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TL052I Samples
TL052IP ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 TL052IP Samples
TL054ACD OBSOLETE SOIC D 14 TBD Call TI Call TI 0 to 70 TL054AC

TL054ACDR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TL054AC Samples
TL054ACN ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 TL054ACN Samples
TL054AID OBSOLETE SOIC D 14 TBD Call TI Call TI -40 to 85 TL054AI
Addendum-Page 1
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
TL054AIDR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TL054AI Samples
TL054CD OBSOLETE SOIC D 14 TBD Call TI Call TI 0 to 70 TL054C

TL054CN ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 TL054CN Samples
TL054CNSR ACTIVE SO NS 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TL054 Samples
TL054ID OBSOLETE SOIC D 14 TBD Call TI Call TI -40 to 85 TL054I

TL054IDR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TL054I Samples
TL054IN ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 TL054IN Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 2
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com 31-Oct-2024
TAPE AND REEL INFORMATION
REEL DIMENSIONS TAPE DIMENSIONS

K0 P1
B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers
Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2 Q1 Q2
Q3 Q4 Q3 Q4 User Direction of Feed
Pocket Quadrants
*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TL051CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TL051CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TL052ACDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TL052ACDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TL052AIDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TL052AIDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TL052CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TL052CPSR SO PS 8 2000 330.0 16.4 8.35 6.6 2.4 12.0 16.0 Q1
TL052IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TL054ACDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
TL054AIDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
TL054CDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
TL054CNSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
TL054IDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
Pack Materials-Page 1
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TL051CDR SOIC D 8 2500 356.0 356.0 35.0
TL051CDR SOIC D 8 2500 353.0 353.0 32.0
TL052ACDR SOIC D 8 2500 356.0 356.0 35.0
TL052ACDR SOIC D 8 2500 353.0 353.0 32.0
TL052AIDR SOIC D 8 2500 353.0 353.0 32.0
TL052AIDR SOIC D 8 2500 356.0 356.0 35.0
TL052CDR SOIC D 8 2500 356.0 356.0 35.0
TL052CPSR SO PS 8 2000 356.0 356.0 35.0
TL052IDR SOIC D 8 2500 356.0 356.0 35.0
TL054ACDR SOIC D 14 2500 356.0 356.0 35.0
TL054AIDR SOIC D 14 2500 356.0 356.0 35.0
TL054CDR SOIC D 14 2500 356.0 356.0 35.0
TL054CNSR SO NS 14 2000 356.0 356.0 35.0
TL054IDR SOIC D 14 2500 356.0 356.0 35.0
TUBE
T - Tube
height L - Tube length
W - Tube
width
B - Alignment groove width

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
TL051CP P PDIP 8 50 506 13.97 11230 4.32
TL052ACP P PDIP 8 50 506 13.97 11230 4.32
TL052AIP P PDIP 8 50 506 13.97 11230 4.32
TL052CP P PDIP 8 50 506 13.97 11230 4.32
TL052IP P PDIP 8 50 506 13.97 11230 4.32
TL054ACN N PDIP 14 25 506 13.97 11230 4.32
TL054CN N PDIP 14 25 506 13.97 11230 4.32
TL054IN N PDIP 14 25 506 13.97 11230 4.32
PACKAGE OUTLINE
D0014A SCALE 1.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
C
6.2
TYP SEATING PLANE
5.8
A PIN 1 ID 0.1 C
AREA
12X 1.27
14
1
8.75 2X
8.55 7.62
NOTE 3
7
8
0.51
14X
4.0 0.31
B 1.75 MAX
3.8 0.25 C A B
NOTE 4
0.25
TYP
0.13
SEE DETAIL A
0.25
GAGE PLANE
0.25
0 -8 1.27 0.10
0.40
DETAIL A
TYPICAL
4220718/A 09/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm, per side.
5. Reference JEDEC registration MS-012, variation AB.
www.ti.com
EXAMPLE BOARD LAYOUT
D0014A SOIC - 1.75 mm max height
14X (1.55) SYMM

1
14
14X (0.6)
12X (1.27)
SYMM
7 8
(R0.05)
TYP
(5.4)
LAND PATTERN EXAMPLE

SCALE:8X
SOLDER MASK METAL UNDER SOLDER MASK

METAL OPENING
OPENING SOLDER MASK
0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND
NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
SOLDER MASK DETAILS
4220718/A 09/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
14X (1.55) SYMM
1
14
14X (0.6)
12X (1.27)
SYMM
7 8
(5.4)
SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:8X
4220718/A 09/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
D0008A SCALE 2.800
SOIC - 1.75 mm max height
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1
.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]
4X (0 -15 )
4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
8X (.061 )
[1.55]
SYMM SEE
DETAILS
1
8
8X (.024)
[0.6] SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK SOLDER MASK

METAL METAL UNDER
OPENING OPENING SOLDER MASK
EXPOSED
METAL EXPOSED
METAL
.0028 MAX .0028 MIN
[0.07] [0.07]
ALL AROUND ALL AROUND
NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
8X (.061 )
[1.55] SYMM
1
8
8X (.024)
[0.6] SYMM
(R.002 ) TYP
5 [0.05]
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
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TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
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TL05x, TL05xA

TL051 TL052 TL054

OFFSET N1 1 8 NC 1OUT 1 8 VCC+ 1OUT 1 14 4OUT

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

symbol (each amplifier)

equivalent schematic (each amplifier)

NOTE A: OFFSET N1 and OFFSET N2 are available only on the TL051x.

ACTUAL DEVICE COMPONENT COUNT†

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

recommended operating conditions

4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL051C and TL051AC electrical characteristics at specified free-air temperature

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

TL051C and TL051AC operating characteristics at specified free-air temperature

6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL051I and TL051AI electrical characteristics at specified free-air temperature

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7

TL051I and TL051AI operating characteristics at specified free-air temperature

8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL052C and TL052AC electrical characteristics at specified free-air temperature

VO = 0,, 25°C 4 100 5 100 pA

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9

TL052C and TL052AC electrical characteristics at specified free-air temperature (continued)

TL052C and TL052AC operating characteristics at specified free-air temperature

10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL052I and TL052AI electrical characteristics at specified free-air temperature

VO = 0,, VIC = 0,, 25°C 4 100 5 100 pA

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11

TL052I and TL052AI electrical characteristics at specified free-air temperature (continued)

TL052I and TL052AI operating characteristics at specified free-air temperature

12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL054C and TL054AC electrical characteristics at specified free-air temperature

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13

TL054C and TL054AC operating characteristics at specified free-air temperature

14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL054I and TL054AI electrical characteristics at specified free-air temperature

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15

TL054I and TL054AI operating characteristics at specified free-air temperature

16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

Figure 1. Slew Rate, Rise/Fall Time, Figure 2. Rise-Time and Overshoot

NOTE A: CL includes fixture capacitance.

typical values VCC+

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17

18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

DISTRIBUTION OF TL051 DISTRIBUTION OF TL051A

DISTRIBUTION OF TL052 DISTRIBUTION OF TL052A

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 19

DISTRIBUTION OF TL054 DISTRIBUTION OF TL054A

DISTRIBUTION OF TL051 DISTRIBUTION OF TL052

P Package 15 Outlier: One Unit at –34.6 µV/°C

20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

DISTRIBUTION OF TL054 INPUT BIAS CURRENT

IB – Input Bias Current – nA

INPUT BIAS CURRENT AND COMMON-MODE

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 21

22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE

VO(PP) – Maximum Peak-to-Peak Output Voltage – V