Scribd
Upload
25 views

SR Flipflop

Uploaded by

dkkeyan
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
25 views

SR Flipflop

Uploaded by

dkkeyan
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 3

Synchronous Sequential Logic 3.

3
3.4 SR FLIP-FLOP
The SR flip-flop has two inputs: S(set) and R(reset) and
two outputs: Q(normal output) and Q (inverted output). The
symbol of SR flip-flop is shown in Figure 3.5. The NOR SR
flip-flop is shown in Figure 3.6. The cross coupled connections
from the output of one NOR gate to the input of the other Fig. 3.5: Symbol of SR flip-flop
NOR gate form a feedback path.

Fig. 3.6: S - R flip-flop

When S = 0 and R = 0, the output, Qn + 1 remains in its present state, Qn.


When S = 0 and R = 1, the flipflop reset to 0.
When S = 1 and R = 0, the flipflop set to 1.

When S = 1 and R = 1, the output of both gates will produce 0. Qn   Q n    .


The truth table of NOR based SR flip-flop is shown in Table 3.2.
TABLE 3.2: Truth Table of SR flip-flop

Inputs Outputs
S R Qn + 1 Q n+ 1 State

0 0 Qn Qn No change
0 1 0 1 Reset
1 0 1 0 Set
1 1 X X Forbidden

Qn  Present State ; Qn + 1  Next State

The SR flip-flop can be also implemented using NAND gates. The inputs of this flip-flop are S
and R .
3.4 Digital Principles and System Design

When S = R = 0, Outputs Qn + 1 = Q n  = 1.

When S = 0, R = 1, the flip-flop output Qn + 1 = 1 (set).


When S = 1, R = 0, the flip-flop output Qn + 1 = 0 (reset).
When S = R = 1, the output remains in its prior state.
The NAND based SR flip-flop is shown in Figure 3.7 and the truth table is given in Table 3.3.

S Q

Q
R
Fig. 3.7: NAND based SR flip-flop

TABLE 3.3: Truth Table of S R flipflop

Inputs Outputs

S R Qn + 1 Q n  State

0 0 X X Forbidden
0 1 1 0 Set
1 0 0 1 Reset
1 1 Qn Qn No change

3.4.1 Characteristic Table and Characteristic Equation


The characteristic table shows the operation of the flip-flop in tabular form. Q is the present state
(Qn) and Qn + 1 stands for next state. The characteristic table of SR flip-flop is shown in Table 3.4.

The characteristic equation is an algebraic expression for the binary information of the characteristic
table. This equation is derived from K-map. This equation specifies the value of the next state as a
function of the present state and the inputs.
Synchronous Sequential Logic 3.5
TABLE 3.4: Characteristic Table
Q S R Qn + 1
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 Forbidden
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 Forbidden
SR 00 01 11 10
Q
0 X 1
1 1 X 1

Characteristic equation: Qn   S  QR

3.5 CLOCKED SR FLIP-FLOP


Synchronous circuits change their states only when clock pulses are present. The clocked SR flip-
flop is shown in Figure 3.8. It consists of a basic SR flipflop circuit and two additional NAND gates.
The pulse input acts as an enable signal (EN) for the other two inputs. The outputs of NAND gates 3
and 4 stay at the logic level 1 as long as the clock pulse input remains 0. When the pulse input goes to
1, information from the S or R input is allowed to reach the output.
S S Q

EN

R Q
R

S Q

EN

Q
R
Fig. 3.8 : Clocked S-R flip-flop

You might also like

pFad - Phonifier reborn

Pfad - The Proxy pFad of © 2024 Garber Painting. All rights reserved.

Note: This service is not intended for secure transactions such as banking, social media, email, or purchasing. Use at your own risk. We assume no liability whatsoever for broken pages.


Alternative Proxies:

Alternative Proxy

pFad Proxy

pFad v3 Proxy

pFad v4 Proxy