Introduction to HDL

VHDL can describe a digital system at several different levels- Behavioral, Data-flow and Structural.

A. Behavioral description: A digital circuit can be described at the behavioral level in terms of its
function or behavior, without giving any implementation details.

B. Data-flow description: A digital circuit can be described at the data-flow level by giving the
logic equation of that circuit.

C. Structural/gate level description: A digital circuit can be described at the structural level by
specifyingthe interconnection of the gates or flip-flops that comprise the circuit.

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PROCEDURE:

The Procedure to be followed for Software and Hardware Programs are as follows:

Step 1: Go to Start Menu All Programs Xilinx ISE 9.1i and Select Project
Navigator.

Step 2: Go to File Menu and select Close project to close previously opened project if any, and then
Select New Project.

Step 3: Enter the Project name and location and Select the Top level module type as HDL.

Step 4: Select the Device family and Device name as Spartan3 and xc3s50, pin density pq208, -5 for
FPGA.

Step 5: Right click on the source file and select new source followed by VHDL module and Give the
file name same as the name of the entity.

Step 6: Define the ports used and their respective directions in the next window that opens.

Step 7: Write the architecture body and the generics etc. in the incomplete VHDL code that opens
and save the file after completion of editing.

Step 8: Go to the Process view window and right click on the Synthesize - XST and Select Run. Correct
the errors if any.

Step 9: Select and Right click the source file and click on the New Source tab and then select the
Test Bench Waveform and give the appropriate file name for the same.

Step 10: Make the alterations in the Clock information and initial length of the test bench if
needed.

Step 11: Set or Reset the inputs as required and save the test bench waveform file.

Step 12: Go to Process view and under Xilinx ISE Simulator Right click on the Simulate Behavioral
model to see the output for the input conditions.

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Step 13: Make the appropriate connections between the PC and the FPGA kit for the observation of
outputs in the FPGA kit and for other Hardware Programming.

Step 14: Select and Right click the source file and click on the New Source tab and then select the
Implementation Constraints file and give the appropriate file name for the same.
Step 15: Go to Process view and under User Constraints, double click on the Edit Constraints
(Text).

Step 16: Write the code for the user constraints file as required and save the same.

Step 17: Select the main source file and right click on the Implement design in the process view
window and select run.

Step 18: Right click on the Generate Programming file in the process view window and select run.

Step 19: Under the Generate Programming file tab, right click on the Configure device (Impact) and
click on the Run option.

Step 20: Select the appropriate mode and make changes in the jumper settings of the FPGA Kit as
required, select the appropriate.BIT extension file in the pop up window.

Step 21: Right click on the Chip picture in the pop up window and Select “Program”. Debug the errors
if it is there. Set the conditions for the inputs using Dip switch and observe the outputs.

**************

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Experiment No. 9

Write a VHDL and Verilog code to describe the functions of a FULL ADDER using following
modeling styles.

Block Diagram:

Truth Table:
Ain Bin Cin Sum Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

Logic Diagram:

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1) DATAFLOW Description:

VHDL Code
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity full_adder is
Port ( a,b,cin: in std_logic;
sum,cout: out std_logic);
end full_adder;
architecture dataflow of full_adder is
begin
sum<=a xor b xor cin;
cout<=(a and b) or (b and cin) or (cin and a);
end dataflow;

VERILOG CODE:
module fad(a,b,cin, sum,cout);
input a,b,cin;
output sum,cout;
assign sum = a ^ b ^ cin;
assign cout = (a & b) | (b & cin) | (a &
cin); endmodule

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BEHAVIORAL VHDL CODE

library ieee ;
use ieee.std_logic_1164.all;
entity fad is
port(a,b,cin: in std_logic;
sum, cout : out std_logic);
end fad;
architecture beh of fad is
begin
process(a,b,cin)
begin
if (a = ‘0’ and b =’0’ and cin = ‘0’) then
sum <= ‘0’; cout <= ‘0’;
elsif (a = ‘0’ and b =’0’ and cin = ‘1’) then
sum <= ‘1’; cout <= ‘0’;
elsif (a = ‘0’ and b =’1’ and cin = ‘0’) then
sum <= ‘1’; cout <= ‘0’;
elsif (a = ‘0’ and b =’1’ and cin = ‘1’) then
sum <= ‘0’; cout <= ‘1’;
elsif (a = ‘1’ and b =’0’ and cin = ‘0’) then
sum <= ‘1’; cout <= ‘0’;
elsif (a = ‘1’ and b =’0’ and cin = ‘1’) then
sum <= ‘0’; cout <= ‘1’;
elsif (a = ‘1’ and b =’1’ and cin = ‘0’) then
sum <= ‘0’; cout <= ‘1’;
elsif (a = ‘1’ and b =’1’ and cin = ‘1’) then
sum <= ‘1’; cout <= ‘1’;
endif;
end process;
end beh;

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VERILOG CODE:
module nm(a,b,cin, sum, cout);
input a,b,cin;
output sum, cout;
reg sum, cout;
always @ (a,b, cin)
begin
if(a==0 & b==0 & cin==0)
begin
sum = 0; cout =0;
end
else if(a==0 & b==0 & cin==1)
begin
sum = 1; cout =0;
end
else if(a==0 & b==1 & cin==0)
begin
sum = 1; cout =0;
end
else if(a==0 & b==1 & cin==1)
begin
sum = 0; cout =1;
end
else if(a==1 & b==0 & cin==0)
begin
sum = 1; cout =0;
end
else if(a==1 & b==0 & cin==1)
begin
sum = 0; cout =1;

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end
else if(a==1 & b==1 & cin==0)
begin
sum = 0; cout =1;
end
else if(a==1 & b==1 & cin==1)
begin
sum = 1; cout =1;
end
end
endmodule
Logic Diagram:

STRUCTURAL Description:
VHDL CODE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity FullAdder is
Port ( Ain, Bin, Cin : in std_logic;
Sum, Cout : out std_logic);
end FullAdder;
architecture structl of FullAdder is
Component Halfadder
Port ( a, b : in std_logic; Sum, Carry : out std_logic);
end Component;

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Component orgate
Port ( a, b : in std_logic; y : out std_logic);
end Component;
Signal temp1, temp2, temp3: std_logic; -- Signal Declaration
begin
L1: Halfadder port map ( Ain, Bin,temp1,temp2);
L2: Halfadder port map ( temp1,Cin,Sum,temp3);
L3: orgate port map (temp2, temp3,Cout);
end struct;
Half Adder circuit
--Low level modules—
--component halfadder--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Halfadder is
Port (a,b : in std_logic; Sum, Carry: out std_logic);
end Halfadder;
architecture dataflow of Halfadder is
begin
Sum <= a xor b;
Carry<= a and b;
end dataflow;
---- component orgate----
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity orgate is
Port ( a, b : in std_logic; y : out std_logic);
end orgate;
architecture dataflow of orgate is
begin
y<= a or b;
end dataflow;

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VERILOG CODE:
module Fulladd (x,y,cin,sum,carry);
input x,y,cin;
output sum,carry;
HA H1(y,cin,s0,c0);
HA H2(x,s0,sum,c1);
or (carry,c0,c1);
endmodule
module HA (a,b,s,c);
input a,b;
output s,c;
xor(s,a,b);
and (c,a,b);
endmodule

OUTPUT:

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RESULT: Three modeling styles of full adder have been realized and simulated using HDL codes.
APPLICATIONS: Adders and Subtractors can be used in op amp circuits, that is as comparators or
differentiators. Arithmetic operations are extensively used in many VLSI applications such as signal
processing, and digital communication. Adders are basically used in calculators. They are used in all
processors – micrprocessors and microcontrollers and also DSP processors.

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