A New Calibration Method for SAR Analog-to-Digital Converters

Based on All Digital Dithering

Shabnam Rahbar
Department of Electrical, Faculty of Engineering, Shahid Chamran University of Ahvaz, Ahvaz, Iran
Sh_rahbar@hotmail.com
Ebrahim Farshidi*
Department of Electrical, Faculty of Engineering, Shahid Chamran University of Ahvaz, Ahvaz, Iran
farshidi@scu.com

Received: 11/Feb/2015 Revised: 07/Jan/2017 Accepted: 07/Mar/2017

Abstract
In this paper a new digital background calibration method for successive approximation register analog to digital
converters is presented. For developing, a perturbation signal is added and also digital offset is injected. One of the main
advantages of this work is that it is completely digitally and eliminates the nonlinear errors between analog capacitor and
array capacitors due to converter‟s capacitors mismatch error by correcting the relative weights. Performing of this digital
dithering method does not require extra capacitors or double independent converters and it will eliminate mismatches
caused by these added elements. Also, No extra calibration overhead for complicated mathematical calculation is needed.
It unlike split calibration, does not need two independent converters for production of two specified paths and it just have
one capacitor array which makes it possible with simple architecture. Furthermore, to improve DNL and INL and correct
the missing code error, sub radix-2 is used in the converter structure. Proposed calibration method is implemented by a 10
bit, 1.87-radix SAR converter. Simulation results with MATLAB software show great improvement in static and dynamic
characteristics in applied analog to digital converter after calibration. So, it can be used in calibration of successive
approximation register analog to digital converters.

Keywords: SAR; Converter; Calibration; Perturbation; Radix-2; DNL and INL.

1. Introduction In this work, a new SAR ADC digital calibration

technique with offset injecting perturbation signal in
Today, due to the combination of analog and digital digital domain is presented. In the proposed method, and
integrated circuits, having the appropriate speed and in two steps, this offset will be injected in the two least
accuracy in data conversion is very important. Hence, significant capacitors in the basic capacitor array,
successive-approximation-register (SAR) analog-to- separately. Also, sub radix-2 architecture [14, 17] is
digital converters (ADCs) because of establishing a good utilized in order to not to lose any code and prevent
balance between speed and accuracy as well as lower redundancy.
complexity of circuits than sigma delta converters, flash The advantages of this method is that: firstly, for
and other types that either lower speed or accuracy and applying the perturbation signal extra analog capacitor
high circuits complexity and volume, have been [15], which leads to new uncompensated mismatching
considered [1-18]. SAR ADC due to good tradeoffs between this analog capacitor and array capacitors, is not
between speed and accuracy. However, capacitor required. Secondly, comparing to preceding digital
mismatch in the SAR converters limits the accuracy and dithering method [16, 19, 20], it doesn‟t need complicated
resolution of the converter. Commonly, the main factor mathematical calculation. Thirdly, unlike split calibration,
that limits the linearity in these converters is capacitor that requires two independent converters for production of
mismatch error in digital-to-analog converter (DAC) [10]. two specified paths [17, 18], it just employs basic
Some SAR ADC calibration methods perform the capacitor array which makes it possible with simple
calibration in the analog domain, which requires extra architecture.
analog circuits [14, 17, 18]. This extra analog will cause This paper organizes the following chapters: in the
additional mismatches between them and capacitors of second chapter a review on procedure of SAR ADS
core array. Also, they need higher circuit complexity. In converters has been provided. In third chapter, calibration
[15, 19, 20] some SAR ADC digital calibration technique architecture and error correction procedure is introduced.
with the dithering method have been proposed. The In the fourth and fifth chapters simulation and conclusion
disadvantage of this technique is that, it is analyzed based are provided.
on complicated mathematical calculations using matrix
and inversing of them, therefore, its implementation
require very complex circuit in digital calibration part.

* Corresponding Author
2 Rahbar & Farshidi, A New Calibration Method for SAR Analog-to-Digital Converters Based on All Digital Dithering

2. Basic Principle of SAR binary-scaled DAC [14]: Fig. 2a shows nominal curve, Fig.
2b shows curve in case of a positive DNL error in the MSB,
2.1 Binary SAR Architecture and Fig. 2c shows curve in case of a negative DNL error in
the MSB[14]. While considering the MSB only in this
In Fig. 1, a conventional form of SAR analog-to-digital example, a comparable situation can occur with the other
converters has been showed. Commonly, it includes a capacitors of the DAC. The large DNL error produced for
DAC with binary weight therein each capacitor with more DNL>0 cannot be reduced with calibration, as calibration
valuable weight is equal to total low-valuable capacitors. can only re-map the input code to an existing combination
Analog input will be converted in N clock cycles to N-bit of capacitors that approximates the desired output level.
digital output. In first phase all capacitors are connected to However, for DNL>0, there is no combination of
input sample , then capacitor is connected to capacitors available to fill the gap in the output range. On
capacitor and the remaining capacitors connect to the other hand, the large DNL error for DNL<0 can be
. By redistribution of capacitor charges, total node corrected with calibration, as there is a „gap-free‟
voltage is obtained as below [10, 14, 17]: consecutive of output levels. By digital re-mapping, the
∑ overlap of the curve can be removed to obtain a slick
⁄ (1) transfer curve. However, as a side effect of the overlap, the
full-scale range of this converter will be slightly smaller
∑ (2) than usual that is compensated by redundancy bit [13, 14].
Considering sign, the comparer specifies Concisely, for the digital calibration to operate
bit. If is zero and otherwise will be 1. properly gaps (DNL>0) are not allowed but overlap
This process is repeated in N clock pulse and for N bit: (DNL<0) is allowed. By means of redundancy, the
probability of a „gap‟ can be reduced to an arbitrary low
∑ (3) value by design: instead of designing the nominal transfer
curve as in Fig. 2a (x=y), it is designed as in Fig. 2c. Thus,
In (3), it is observed that the share of each digital redundancy introduces intentional overlap (DNL<0) of
output bit is determined by a weight that is equal to the nominal transfer curve to guarantee that the consecutive
⁄ . In ideal mode, the weights are equal to ⁄ (i is of the output range remains, also in case of mismatch.
While the figure illustrates redundancy for the MSB only,
the number of relative bit). In this mode, converter
in reality this redundancy requirement needs to be
transfer curve is as linear function x=y [13].
implemented for each bit of the converter [13, 14, 17].
Although binary algorithm is more efficient as respect to
For the case that the more valuable weight is smaller
the conversion stages but is exposed to the analog disorders
than total capacitors, probably a code is lost.
while implementing the actual circuit. Mismatch of
capacitor in binary SAR ADC is static error resources (DNL,
INL). For reducing these errors, often ADC including unit
elements and capacitive divisions is used that is cause of
circuits complexity in logic part such as binary to
thermometry decoder circuit that ultimately results in speed
drops of converter. In the mode of having error due to the
mismatch of capacitors, the decision-making surfaces may
not be distributed equally all over the input range. This
distortion may lead in losing some codes, but that missing
code maybe improved by digital calibration [13]. Fig. 2. Transfer curves for a 5-bit binary-scaled DAC:
left) Nominal curve middle) Curve case of a positive DNL error in the
MSB right) Curve case of a negative DNL error in the MSB [14]

3. Calibration Method
Perturbation-based calibration algorithm has been
introduced in [15]. In [15], perturbation signal in analog
domain has been inserted to the inlet by two small
capacitors. These capacitors increase the chip area.
Fig. 1. SAR ADC structure Furthermore, mismatch error between these inserted
capacitors and the capacitors of SAR ADC cannot be
2.2 Sub Radix-2 Architecture DAC compensated. Dithering method is used in [16], by
If binary architecture without any modification is used, applying a PN signal on the weights, the error is corrected
digital calibration cannot correct all types of mismatch by matrix and very complicated calculations which will
errors. Fig. 2 illustrates several transfer curves for a 5-bit lead to high amount of circuit a low speed in the
 Journal of Information Systems and Telecommunication, Vol. 5, No. 1, January-March 2017 3

calibration unit. In this paper, the error has been Adding and subtracting has been done by forward and
compensated by adding two lower weights to the input. reverse switching sequence of this capacitor, respectively
In this paper a new structure of sub radix-2 algorithm [16]. So it can be said that:
has been used that reduces the complexity of circuit
∑ (7)
structure, in which by using the added weights and
to the converter. Capacitor mismatch errors are corrected where is the analog sample, is the quantization
in digital domain. noise and weight of the i‟th bit.
Fig. 3 exhibits the first step of background calibration In the second step calibration engine, and for updating
design of SAR ADC. As can be seen, to perturbation , the weight of are added to input (similar to
signal injection, the weight of lowest bit of the first ) and the error is obtained by calculating the difference
stage is applied by , in which the sum/subtract of these of outputs and reducing 2 as shown in Fig. 5 error is
two makes the ADC input. used to calibrate the weight of in terms of the
The operation is described as follows: a single SAR following equation:
ADC digitizes each analog sample twice, with two offsets,
where is the weight of lowest bit . SAR ADC provides ⏟ ⏟ (8)
two outputs for each sample of analog input. is produced
in lieu for input and in lieu for . and
According to Fig. 3, the main output of ADC is (9)
produced out of the average of both outputs. The error is
calculated by subtracting the outputs through reducing 2
. So it can be written as:
⏟ ⏟ (4)

(5)

where is the final output of ADC.

Update equation of weights is obtained according to Fig. 5. Updating with injecting
LMS method as following [15]:
For the signal injection of second dither and for
(6) adding to , as can be seen in the Fig. 6 digital
Where is the convergence coefficient. offset is injected through the second lowest-valuable
By this equation, all weights except will be weight capacitor in capacitor banks of Fig. 1(similar to
updated and improved. preceding step). So it can be written as:
∑ (10)
Complete algorithm for the proposed calibration
method is shown in Fig. 7. So it concluded that the
proposed technique has several advantages: comparing
with some preceding dithering method [15], for
perturbation signal, this method does not use extra
capacitor and employs same basic capacitor array.
Furthermore, unlike [16,19,20], complicated mathematical
Fig. 3. Calibration diagram with injecting w0 and matrix calculation is not required. Also, unlike split
calibration [17,18], double independent converters paths
In order to facilitate the signal injection of dither, as
are not used.
can be seen in the Fig. 4, the digital offset is injected
through the lowest-valuable weight capacitor in capacitor
banks of Fig. 1.

Fig. 6. Injecting to input

Fig. 4. Injecting to input

4 Rahbar & Farshidi, A New Calibration Method for SAR Analog-to-Digital Converters Based on All Digital Dithering

4. Simulation Results of DNL and INL is completely evident. After calibration

DNL and INL reduced from [-1, +12] LSB to [-0.1, +0.1]
A 10-bit SAR ADC has been simulated and calibrated LSB and [-14.2, +14.2] LSB to [-0.34, +0.23] LSB,
by background digital calibration procedure and aiding respectively. It should be pointed out that the effective
MATLAB software. The capacity of capacitors in ADC number of bit is approximately is 10bit (which has
has been specified according to sub radix-2 algorithm and maximum length of 210=1024 multiplied by LSB) and
mismatch 5% and with the base of 1.87, in accordance before calibration maximum length of DNL is about
with first line of table I. The stability coefficients of LMS 14LSB. So DNL is less than 1.5% of maximum length in
loop is chosen. INL and DNL a 10bit converter. Upon reaching DNL to [-0.5, 0.5] LSB,
diagrams before and after calibration modes are observed missing code error is improved. Fig. 10 shows frequency
respectively in Fig. 8 and 9. response diagram before and after calibration. Static and
Fig. 8a and Fig. 8b show DNL diagrams and Fig. 9a dynamic specifications are shown in table II. After
and Fig. 9b show INL diagrams before and after calibration, static and dynamic specifications have
calibration, respectively. In this figures the improvement noticeable Improvement.

Fig. 7. Flowchart of calibration procedure

Fig. 8. DNL Diagrams: a) Before calibration b) After calibration

 Journal of Information Systems and Telecommunication, Vol. 5, No. 1, January-March 2017 5

Fig. 9. INL Diagrams: a) Before calibration b) After calibration

Fig. 10. Output PSD diagram: a) Before calibration b) After calibrat

Table 1. Static and dynamic specifications SAR ADC

improved by means of calibration method. Upon applying
sub radix-2, no adaptation to the unit capacitor is required
Before Calibration After Calibration Improvement Rate
DNL(LSB) 12 0.21 11.76 and it causes the simplicity of analog circuit and
INL(LSB) 14.2 0.57 13.63 improvement of converter efficiency. Innovative result of
SNR (dB) 32.52 60.56 28.04 this work is that perturbation signal is injected by the two
SFDR (dB) 48.61 69.53 20.92 least significant of existing elements in array capacitor of
ENOB (Bits) 5.11 9.91 4.8 converter. So, this method does not need extra capacitor,
so, related issue of mismatch between added element and
existing elements in array capacitor will be eliminated.
5. Conclusion Furthermore, compared to the preceding works, it does
not require complex mathematical calculations.
A SAR ADC by digital background calibration
method as well as sub radix-2 algorithm was presented.
The dominant error in this converter was studied and

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digital background calibration technique for successive Shabnam Rahbar was born in Brogerd, Iran, in 1984. She
approximation analog-to-digital converters,” in ASIC, received the B.Sc degree in 2008 from Shiraz University, Shiraz,
2007. ASICON'07. 7th International Conference on, pp. Iran, and the M.Sc degree in 2012 from Shahid Chamran
University of Ahvaz, Ahvaz, Iran. Her main research area is
289-292, 2007.
calibration of data converters.
[14] P. Harpe, H. Hegt, and A. Roermund, Smart AD and DA
Conversion: Springer, 2010. Ebrahim Farshidi was born in Shoushtar, Iran, in 1973. He
[15] W. Liu, P. Huang, and Y. Chiu, “A 12-bit, 45-MS/s, 3-mW received the B.Sc degree in 1995 from Amir Kabir University,
Redundant Successive-Approximation-Register Analog-to- Iran, the M.Sc degree in 1997 from Sharif University, Iran and the
Digital Converter With Digital Calibration,” IEEE Journal Ph.D degree in 2008 from electrical engineering at IUT, Iran, all in
of Solid-State Circuits, vol. 46, pp. 2661-2672, 2011. electronic engineering. He worked for Karun Pulp and Paper
[16] R. Xu, B. Liu, and J. Yuan, “Digitally Calibrated 768-kS/s Company during 1997–2002. From 2002 he has been with shahid
chamran university, Ahvaz, where he is currently Professor of
10-b Minimum-Size SAR ADC Array With Dithering,”
electrical engineering department. He is author of more than 100
IEEE Journal of Solid-State Circuits, vol. 47, pp. 2129- technical papers in electronics. His areas of interest include
2140, 2012. current-mode circuits design, and data converters.
[17] S. Rahbar and E. Farshidi “Digital Background Calibration
of Radix 1.83 Successive Approximations Register
Analog-to-Digital Converter using the Split Architecture,”