IHuC62BOI~

CMOS 8-bit Microprocessor

HARDWARE MANUAL
I
 TABLE OF CONTENTS

1. DESCRIPTION ................................................................................................................................... H8-1

1.1 Features ..................................................................................................................................... H8-1

2. FUNCTIONS ...................................................................................................................................... H8-2

2.1 Register Set .............................................................................................................................. H8-2
2. 1.1 Accumulator (ACC) ...................................................................................................... H8-2
2.1.2 Registers X and ¥ ........................................................................................................ H8-2
2.1. 3 Program Counters (PCH, PCL) .................................................................................. H8-3
2.1. 4 Stack Pointer (S) .......................................................................................................... H8-3
2.1 .5 Status Register (P) ....................................................................................................... H8-4
2.1 .6 Registers SH, DH and LH .......................................................................................... HS-6
2.2 Mapping Register (MPR) ........................................................................................................ HB-7
2.3 Memory Space ......................................................................................................................... HS-1 0
2.4 Interrupt and Break ................................................................................................................. HB-12
2.4. 1 Nonmaskable Interrupt (NMI Input) ........................................................................ HB-12
2.4.2 Interrupt Requests 1 and 2 (IRQ1, IR02) .............................................................. H8-13
2.4.3 Timer lnterrupt ............................................................................................................. H8-14
2.4 .4 Organization and Functions of Interrupt Request Register .............................. H8-15
2.4 .5 Organization and Functions of Interrupt Disable Register ............................... H8-16
2.4. 7 Break (BRK) ................................................................................................................... H8-17
2. 5 System Reset ......................................................................................................................... H 8-1 8
2.6 I/O ............................................................................................................................................. H8-19
2.6.1 Port K......................................................................................................................... HS-19
2.6.2 PortO ........................................................................................................................ H8-19

H8-i
 2. 7 Timer ........................................................................................................................................ HB-20
2. 8 Programmable Sound Generator (PSG) .......................................................................... HB-23
2. 9 Device/Register Addresses ................................................................................................ HB-24

3. INSTRUCTION MAP ........................................................................................................................ HB-25

4. INSTRUCTION SET SUMMARY ................................................................................................... HB-26

HB-ii
1. DESCRIPTION
The HuC6280 is a CMOS 8-bit microprocessor which contains an 8-bit parallel processing ALU,
eight mapping registers for address expansion, a 7-bit interval timer, an 8-bit input port, an 8-bit
output port, and a programmable sound generator (PSG) on a single chip. It has 2M bytes of
address space, and operates at a speed as high as a 138 nsec bus cycle.

1.1 Features

e Monolithic CMOS 8-bit parallel processing micro-processor

• Operating frequency ................................. 3.58-21.48 MHz (actual)
• Minimum instruction cycle time ............ 276 nsec
• Instruction set ............................................. 234 instructions in 89 groups
• 1/0 ports ....................................................... Input port: 1 port X 8 bits
Output port: 1 port X 8 bits
• Interrupts ...................................................... External: NMI , IRQ 1, IRQ2
Internal: Timer interrupt and BRK instruction
• On-chip 7-bit interval timer
e Stack area .................................................... 256 bytes (maximum)
• Single power supply ................................. 5V
• Package ........................................................ 80-pin plastic flat package
• Address space ............................................ Controlled by eight mapping registers
(2M bytes for physical addresses and 64K bytes for
logical addresses)

HB-1
2. FUNCTIONS
2.1 Register Set
The HuC6280 has a total of ten 8-bit registers:
CD Accumulator (general-purpose) (ACC)
® Register X (X)
® Register Y (Y)
0 Program counter high (PCH)
® Program counter low (PCL)
NOTE: PCH and PCL make up a complete program counter.
® Stack pointer (S)
0 Status register (P)
® Source high (SH)
® Destination high (DH)
@ Length high (LH)
NOTE: SH, DH and LH are used when a block transfer instruction is executed.

2.1 .1 Accumulator (ACC)

The ACC is an 8-bit general-purpose register. When the memory operation flag (T) is set to "0",
most ALU operations are performed by the ACC. The contents of the ACC are loaded into the
ALU, and the result of an operation is stored in the ACC.
The ACC also is used for the transfer of data from memory to memory, or between memory and
a peripheral circuit.
When a block transfer instruction (TII-TDD) is executed, the ACC saves the current data into the
stack and functions as a length low register for counting the block length.

2.1.2 Registers X and Y

Both X and Y registers are an 8-bit general-purpose register that works mainly for index
addressing.
With the memory operation flag (T) set to "1", register X is used to specify a memory address
on page 0 which is the destination of an operation.
When a block transfer instruction (TII-TDD) is executed, register X saves the current data into
the stack and functions as a source low register for specifying the source address.
When a block transfer instruction (TII-TDD) is executed, register Y saves the current data into
the stack and functions as a destination low register for specifying the destination address.

HB-2
2.1.3 Program Counter (PCH, PCL)
The program counter is a 16bit upcounter which consists of a program counter high (PCH) and
a program counter low (PCL).
Each time an instruction is executed, the program counter is automatically incremented and
specifies the address of the next instruction to execute or the address of its operand.
When a system reset occurs, the CPU loads low byte of address data into the PCL from physical
address 001 FFE,s and high byte into the PCH from physical address 001 FFF,6, then starts.
e Save or Restore Operations of Program Counter
(a) BSR or JSR instruction
When a BSR or JSR instruction is executed, the contents of the program counter are saved
into the stack with the PCH preceding the PCL. The saved data in the stack points the address
of the last byte of the BSR or JSR instruction.
When an RTS instruction is executed, the program counter loads the address data from the
stack and increments by 1. Then the program returns from the subroutine.
(b) Interrupt
When an interrupt occurs, the contents of the program counter are also saved into the stack.
(The PCH, PCL and P are pushed into the stack in that order.) The data thus pushed in the
stack points the address of the instruction that follows the interrupt handling routine
inserted. When an RTI instruction is executed, the program counter loads the address data
from the stack and the program returns from the interrupt handling routine. At the same time,
the value of the status register (P) is also restored from the stack.
(c) BRK instruction
When a BRK instruction is executed, the contents of the program counter are saved into the
stack after completion of the instruction. The saved data in the stack points the address of
the BRK instruction + 2. (The PCH, PCL and P are pushed into the stack in that order.)
When an RTI instruction is executed, the program returns to the address "BRK + 2". At the
same time, the value of the status register (P) is also restored from the stack.

2.1 .4 Stack Pointer (S)

The stack pointer (S) is an 8bit register which contains the loworder 8 bits of the highest address
of a free stack area. The stack pointer is decremented after the data is pushed into the stack,
and incremented before it is pulled from the stack. After a system reset occurs, the contents
of the stack pointer become invalid. The initial routine must set appropriate data in the stack
pointer. When the stack pointer is output onto the address bus, the high byte should always
be 21 ,s. Therefore, the stack area of the HuC6280 consists of up to 256 bytes at logical
addresses from 2 1FF,s to 2 1OO,s.

H8-3
2. 1.5 Status Register (P)
The status register (P) is an 8bit register. Its bit organization is shown in Fig. 2-1-1.

MSB LSB

IN v T 8 D I z c
I
I Carry flag
Zero flag
Interrupt Disable
Decimal flag
Break command
Memory operation flag
Overflow flag
Negative flag

Fig. 2-1-1 Bit Organization of Status Register (P)

The status register, as its name implies, shows the status of the CPU. Each bit shows different
status and is independent from each other. For instructions that affect these bits, see Section
6 INSTRUCTION SET SUMMARY.
The contents of the status register are automatically pushed into the stack when an interrupt
occurs or a BRK instruction is executed. The RTI instruction causes the status register to be
restored from the stack.
( 1) Carry Flag (C)
The Carry flag (C) is set if a carry occurs out of the MSB of the result for ADC, or if a borrow
occurs during SBC, CMP, CPX or CPY. Otherwise, it is cleared.
The Carry flag is also affected by a shift or rotate instruction.
The Carry flag is set by the SEC instruction, and reset by the CLC instruction.
(2) Zero Flag (Z)
The Zero flag (Z) is set if the result of an ALU operation equals zero or the data of a transfer
instruction equals zero.
(3) Interrupt Disable (I)
The Interrupt Disable (I) is set when the system is reset, an interrupt occurs, or a BRK
instruction is executed. It is set by the SEI instruction, and reset by the CLI instruction.
When the Interrupt Disable is" 1", an interrupt by IRQ 1 or IRQ2, or by the timer cannot occur.
(4) Decimal Flag (D)
The Decimal flag (D) is reset when the system is reset, an interrupt occurs, or a BRK instruction
is executed. It is set by the SED instruction, and reset by the CLD instruction.
When the Decimal flag is" 1", an ADC or an SBC instruction performs a decimal operation.
In this case, the instruction cycle is supplemented by one additional cycle for decimal
adjustment.
(5) Break Command (B)
The Break Command (B) is a status which is valid only when an interrupt occurs by IRQ2
or a BRK instruction is executed.

HB-4
 When an IRQ2 interrupt occurs or a BRK instruction is executed, the CPU reads the low byte
vector address at logical address FFF6,s and the high byte vector address at logical address
FFF7,s, then executes a subroutine. In this case, the Break Command in the status register
(P) to be saved into the stack is set to "0" for the IR02 interrupt or to "1" for the BRK
instruction.
The Break Command has no meaning except in the above cases, but is set to "1" if read
with the PHP or the PLA instruction.
(6) Memory Operation Flag (T)
The Memory Operation flag (T) is set by the SET instruction. The flag affects the next
instruction.
If the instruction following the SET is AND, OR, EOR or ADC, its operation is performed for
the memory area on page 0 which is addressed indirectly by register X. If the instruction
following the SET is any other than these four, the SET has no meaning.
The Memory Operation flag is set by the SET instruction, and reset in the fetch cycle of the
next instruction.
The Memory Operation flag is saved into the stack when an interrupt occurs. Therefore, even
if the interrupt handling routine is placed between the SET and the next instruction, the ALU
instruction works as a memory operation instruction.
When the status register is read with a PHP or PLA instruction, the Memory Operation flag
is set to "0". The flag saved in the stack is set to "1" only when a special interrupt occurs
(see above).
(7) Overflow Flag (V)
When an operation with a sign is performed, the Overflow flag (V) is available. The HuC6280
uses the adder in the ALU to perform all kinds of add and subtract operations. In a subtract
operation, the two's complement of the minuend is placed into the adder. If one of the two
values that are placed into the adder is positive and the other negative, then the Overflow
flag is reset. If both values are positive, the flag is set when bit 7 of the result of the add
operation is ''1'', and reset when it is "0". If both values are negative, the flag is set when
bit 7 of the result of the add operation is "0", and reset when it is "1".
The Overflow flag is reset by the CLV instruction.
When a BIT, TRB, TSB or TST instruction is executed, the data in bit 6 of memory is set in
the Overflow flag.
(8) Negative Flag (N)
The Negative flag (N) is set or reset depending on bit 7 of the result of an ALU instruction.
It is set if bit 7 is "1", and reset if it is "0".
When the BIT, TRB, TSB or TST instruction is executed, the data in bit 7 of the memory is
set in the Negative flag.

HB-5
2.1.6 Registers SH, DH and LH
The source high (SH), destination high (DH) or length high (LH) is a specialpurpose register which
functions only when a block transfer instruction (Til-TOO) is executed. None of them can be read
or written by any HuC6280 instruction.
The source high register is paired with register X as the low byte of a 16bit source address.
The destination high register is paired with register Y as the low byte of a 16-bit destination
address.
The length high register is paired with the ACC as the low byte of a 16-bit downcounter which
counts the length of a block to be transferred. Counting is on a byte basis.
e Operation with block transfer instructions
At the beginning of a block data transfer instruction, the contents of the ACC, register X and
register Y are saved in the stack. Then the source address, destination address and length
of the target block are loaded to the (SH, X), (DH, Y) and (LH, ACC), respectively.
The source address and the destination address used in the block transfer mode are specified
for each instruction (Til-TOO) as described in Table 2-5-1. The transfer block length is
specified by the length parameter. If length = OOOO,s, 65536 bytes of data are transferred.

While a block transfer instruction is executing, one byte of data is transferred from the source
address to the destination address in six bus cycles. The number of cycles required for
execution of a block transfer instruction is ( 17 + 6x), where x is the length.
At the end of the block transfer instruction, the contents of the ACC, register X and register
Y are returned from the stack.
A block transfer instruction uses 3 bytes of stack as mentioned above.

Table 2-1-1 Source Address and Destination Address in Block Transfer Instructions

Mnemonic Source address (SH, X) Destination address (DH, Y)

Til Post-increment Post-increment

TIN Post-increment Fixed

TIA
Post-increment
CD Post-increment }
Alternated
NOTE
® Post-decrement

TAl CD Post-increment }
Alternated
NOTE
Post-increment
® Post-decrement

TOO Post-decrement Post-decrement

NOTE: Post-increment precedes post-decrement.

H8-6
2.2 Mapping Register (MPR)
The HuC6280 contains eight mapping registers (MPRO- MPR7). A mapping register is an 8bit
register which converts a 16bit logical address into a 2 1bit physical address.
As shown in Fig. 2-2-1, the mapping register (MPR) consists of eight registers (MPRO- MPR7),
an output selector flipflop, and an 1/0 control. In the figure,H7-H5refer to the highorder three
bits of H-BUS. These three bits are used to select a mapping register (MPRO- MPR7). They are
replaced with 8 bits of data from the selected mapping register and are then converted into
2 1 bits of physical address.

MPRO

MPR 1
c.
MPR Z .g
ec
0
()
MPR 3 -...
.9-
...0
(.) A13-AZO
(ll

0 MPR 4 a;
:::::, ...:::s
1/)

MPR 5 ...:::sc.
0
MPR6

Fig. 2-2-1 Organization of Mapping Register (MPR)

The relation between the high-order 3 bits of logical address and mapping registers selected
by them is listed in Table 2-2-1. The contents of a selected mapping register are output as a
physical address to A 13- A20.

Table 2-2-1 Selection of Mapping Registers

H7 H6 H5 H7 H6 H5

0 0 0 MPRO 1 0 0 MPR4
0 0 1 MPR1 1 0 1 MPR5
0 1 0 MPR2 1 1 0 MPR6
0 1 1 MPR3 1 1 1 MPR7

HB- 7
At a system reset, MPR7 is set to 0 ("OO,e"). Then the HuC6280 reads the low byte address at
logical address FFFE,s and the high byte address at logical address FFFF,s, and starts. Since
MPR7 = OO,s, the program reads the low byte address at physical address 001 FFE,s and the
high byte address at 001 FFF,s, and starts.
A system reset does not initialize the rest of the mapping registers (MPRO- MPR6). The initial
routine must be used to initialize these registers.
The TMAi (i = 0- 7) instruction is used to read data from a mapping register. The TAMi (i =
0- 7) instruction is used to write data to the mapping register. The TMAi or TAMi is a 2byte
instruction, the second byte being used to specify the mapping register to be selected. The bit
organization of the second byte is such that the bit corresponding to a mapping register number
to be selected is set to" 1" and the rest to "0". Table 2-2-2 shows assignment of the TMAi/T AMi
bits to the mapping registers.

Table 2-2-2 Mapping Register Selection by TMAi/TAMi

Second byte (binary)

Mapping register MSB LSB

MPR 1 0 0 0 0 0 0 0 1
MPR 1 00000010
MPR 2 00000100
MPR 3 0 0 0 0 1 0 0 0
MPR 4 0 0 0 1 0 0 0 0
MPR 5 0 0 1 0 0 0 0 0
MPR 6 01000000
MPR 7 10000000

Address line A20 of the output selector flipflop outputs (A 13- A20) provides "H" level in the
write cycle of an immediate data transfer instruction (STO, ST1, ST2) to the HuC6270. Special
code (shown in Table 2-2-3) is output to AO and A 1 in response to each immediate data transfer
instruction in its write cycle.

Table 2-2-3 Address Output to HuC6270

~R

ST 0
A1

0
AO

ST 1 1 0

ST 2 1 1

HS-8
 Physical Numbers of
Physical address space
address each block
Chip Enable (The parenthesized
CE is not outputto outside the chip.) IFFFFF
(reserved for extension)
IFF COO
IFF~FF
(reserved for extension)
IFF BOO
IFF7FF
(Interrupt request register
(CECG) interrupt disable register)
1FF400
IFF3FF
(CEIO) ( 1/0) FF
IFFOOO
IFEfFF
(CET) Timer
IFECOO
1FEBFF
(CEPl (PSG)
IFE800
IFE7FF
CEK (HuC6Z60)
1FE400
IFE.3FF
CE7 (HuC6Z70)
IFEOOO
IF~FFF
FE
IFCOOO
IFBFFF
FD
IFAOOO
IF9FFF
FC
IF8000
IF7FFF
FB
IF6000
1F5fFF
FA
1F4000
1F3FFF
F9
1F2000
CER 1F1FFF

1F0200
1F0.1FF
(Stack when MPR 1 = FS) F8
1F0100
1FOOFF
Zero page when MPR 1 = FS
IFOOOO
1EFFFF
F7
1EEOOO
I I
I I
I I
I I

003FFF
01
ooiooo
Vector of system -
reset ( OOIFFF
OOIFFE
(High byte address of reset)
(Low byte address of reset)
001FFD
00 8Kbytes
001FFC

000000
(hexadecimal) (hexadecimal)

Chip Enable Allocation

HS-9
2.3 Memory Space
The HuC6280 has 64K bytes of logical address space and 2M bytes of physical address space.
The relation between logical and physical addresses depends on the contents of the mapping
registers MPRO- MPR7. Fig. 2-8-1 gives an example of correspondence between the logical
address space and the physical address space.

2M bytes of
Numbers of physical Physical
each block address space address
IFFFFF
FF
IFEOOO
IFDfFF
FE
IFCOOO
I I
I I
I I
I I
IFIFFF
F8
~ IFOOOO
IEFFFF
F7
IEEOOO
I I
I
I 'I
I I

101FFF
80
100000
Logica I 64K bytes of OFFFFF
add res s logical address space MPR (example) 7F
OFEOOO
FFFF

EOOO
( 8Kbytes
- MPR7
=00
7E
OFDFFF
OFCOOO
DFFF

cooo - MPR6
=7F
70
OFBFFF

-
OFAOOO
BF~F I I
MPRS I
I
I
I
AOOO =01 I I

-
9FFF 009FFF
MPR4 04
=02

-
8000 008000
7F~F 007FFF
MPR3 03
6000 =70 006000
SF~F

- MPR2 I 02
005FFF

--
4000 =04 004000
3F~F 003.FFF

~
MPR1 01
2000 =F8 002000
1FFF 001FFF
MPRO 00
=FF ( 8Kbytes
0000 000000

(hexadecimal) (hexadecimal) (hexadecimal) (hexadecimal)

Fig. 2-3-1 Example of Correspondence between Logical

H8-10
As shown in Fig. 2-3-1, the address space is organized in 8K-byte units (8K bytes = one unit
of address space AO- A 12).
The physical address space consists of 256 units of 8K-byte blocks, which are numbered "OO,s"
to "FF,s" (low to high). Each block is selected by a mapping register (MPRO- MPR7), and
relocated in the logical address space.
Example: In Fig. 2-3-1, MPR 1 =FS,s. Therefore, the BK byte block at physical addresses from
1 FOOOO,s to 1 F 1FFF,s is relocated at logical addresses from 2000,s to 3FFF,s.

HB-11
2.4 Interrupt and Break
The HuC6280 allows three external interrupts and two internal interrupts. The external
interrupts are the nonmaskable interrupt (NMI input), interrupt request 1 (IRQ 1 input), and
interrupt request 2 (IRQ2 input). The internal interrupts are the timer interrupt and interrupt by
software (BRK instruction).
These interrupt inputs are sampled in the last bus cycle of one instruction when it is executed.
Fig. 2-9-1 shows the vector table and priority of the interrupts. System reset has higher priority
than any of the interrupts.
The CPU reads the status of an IRQ 1 input, IRQ2 input or timer interrupt from the interrupt
request resgister into the ACC. The interrupt disable register allows these interrupts to be
individually disabled. Moreover, Interrupt Disable (I) can disable all of the three interrupts at the
same time.
Figs. 2-4-2 and 2-4-3 represent the organization of the interrupt request register, interrupt
disable register and interrupt circuit, respectively.

2.4.1 Nonmaskable Interrupt (NMI Input)

Nonmaskable Interrupt (NMI) is an external interrupt driven by edge sense. It cannot be masked
by Interrupt Disable (I).
(1) Interrupt Caused by NMI Input
A transition of the NMI input from "H" to "L" level causes a nonmaskable interrupt. After
the instruction in progress is completed, the CPU reads the low byte at logical address FFFC1s,
and the high byte at logical address FFFD1s, and calls the interrupt handling subroutine.
(2) Operation of Interrupt Handling Subroutine In the subroutine call sequence, the contents
of the program counter (PCH, PCL) and the status register (P) are pushed into the stack in
that order (i.e., PCH, PCL and P). In the write cycle to the stack, the stack pointer (S) is
postdecremented. The break command (B) in the status register to be pushed into the stack
is set to "0".
The CPU sets Interrupt Disable (I) of the status register (P) and resets Decimal (D).
(3) Returning from Interrupt Handling Subroutine
When the RTI instruction is executed, the values of the PCH, PCL and P are returned from
the stack.
Then the CPU restarts at the next address at which the interrupt handling subroutine was
inserted.

HS-12
 • RESET and BRK instruction, and priority of interrupts

I RESET I > I NMI I > I BRK instructions I > I TIMER I > I IRQ 1 I > I1RQ2 I

• Vector table

Destination address of IRQ2 interrupt

FFFB - (BRK instruction) -Hl
FFF7
l
FFFB r- Destination address of IRQ 1 interrupt -H
Logical address FFF9
l
FFFA r- Destination address of timer interrupt -
H
FFFB
FFFC r- Destination address of NMI interrupt -HL
FFFD
L
Physical address
001FFE f- Destination address of RESET input -
H
001FFF
(hexadecimal)

Fig. 2·4-1. Vector Table and Priority

2.4.2 Interrupt Requests 1 and 2 (IRQ 1 and IRQ2}

Interrupt Request 1 (IRQ 1 input) and Interrupt Request 2 (IRQ2 input) are external interrupts
driven by level sense. These two are masked when Interrupt Disable (I) of the status register
(P) is set.
(1) Interrupt Caused by IRQ 1 Input
An IRQ 1 interrupt occurs when the IRQ 1 input goes "L" with Interrupt Disable (I) reset and
IRQ 1 Disable (IRQ 1 D) of the interrupt disable register at "0". When the instruction in progress
is terminated, the CPU reads the low byte at logical address FFF8,s and the high byte at logical
address FFF9,s, and executes the interrupt handling subroutine.

HB-13
(2) Interrupt Caused by IRQ2 Input
An IRQ2 interrupt occurs when the IRQ2 input goes "L" with Interrupt Disable (I) reset and
the IRQ2 Disable (IRQ2D) of the interrupt disable register at "0". When the instruction in
progress is terminated, the CPU reads the low byte at logical address FFF6,s and the high
byte at logical address FFF7,s, and executes the interrupt handling subroutine.
(3) Operation of Interrupt Handling Subroutine
In the subroutine call sequence, the values of the program counter (PCH, PCL) and the status
register (P) are pushed into the stack in that order (i.e., PCH, PCL and P). In the write cycle
to the stack, the stack pointer (S) is postdecremented. The break command (B) in the status
register to be pushed into the stack is set to "0".
The CPU sets Interrupt Disable (I) of the status register and resets Decimal (D).
(4) Returning from Interrupt Handling Subroutine
When the RTI instruction is executed, the values of the PCH, PCL and P are returned from
the stack. Then the CPU restarts at the next address at which the interrupt handling
subroutine was inserted.

2.4.3 Timer Interrupt

A timer interrupt is an internal interrupt which is caused by a borrow of the timer. It is masked
when Interrupt Disable (I) of the interrupt disable register is set.
( 1) Conditions and Processing for Timer Interrupt
If a timer borrow occurs with Interrupt Disable (I) reset and TIQ Disable (TIQD) of the interrupt
disable register at "0", Timer interrupt Request (TIQ) of the interrupt request register is set
and a timer interrupt occurs. Then the CPU reads the low byte at logical address FFFA,s and
the high byte at logical address FFFB,s, and calls the interrupt handling subroutine.
(2) Operation of Interrupt Handling Subroutine
In the subroutine call sequence, the values of the program counter (PCH, PCL) and the status
register (P) are pushed into the stack in that order (i.e., PCH, PCL and P). In the write cycle
to the stack, the stack pointer {S) is postdecremented. The break command (B) in the status
register to be pushed into the stack is set to "0".
The CPU sets Interrupt Disable (I) of the status register and resets Decimal (D).
(3) Returning from Interrupt Handling Subroutine
When the RTI instruction is executed, the values of the PCH, PCL and P are returned from
the stack. Then the CPU restarts at the next address at which the interrupt handling
subroutine was inserted.
(4) TIQ Reset
Timer Interrupt Request (TIQ) is reset by the execution of a write cycle to the interrupt request
register.

HB-14
2.4.4 Organization and Functions of Interrupt Request Register

MSB LSB

IRQ1 IRQ2
Organization of interrupt request register
(CECG=O, A1=1, A0=1)

Example of addressing:
logical address 1403,& with MPRO= FF,&

Interrupt Request 2 (IRQ2):

Read only.lnverted data of input level at pin IRQ2 is read.
1: Input at pin IRQ2 is "L".
0: Input at pin IRQ2 is "H".

,____ _ _ Interrupt Request 1 (IRQ 1)

Read only.lnverted data of input level at pin IRQ 1 is read.
1: Input at pin IRQ 1 is "L".
0: Input at pin IRQ 1 is "H".

______
.___ Timer Interrupt Request (TIQ):
Read only. This signal is reset by execution of a write cycle to
the interrupt request register. It is set by a timer borrow.
1: A timer interrupt request has occurred.
0: No timer interrupt request has occurred.
When system is reset, TIQ is set to "0".

Fig. 2-4-2 Interrupt Request Register

Data can be read from or written to the interrupt request register at physical addresses from
1FF400,& to 1 FF7 FF,& where (A 1, AO) = ( 1, 1).

HB-15
2.4.5 Organization and Functions of Interrupt Disable Register

Organization of interrupt request register

MSB LSB
(CECG=O, A 1 = 1, AO=O)

Example of addressing:
logical address 1402,6 with MPRO=FF,6

IRQ2 Disable (IRQ2D):

Read/write enabled.
1: Interrupt request at pin IRQ2 is disabled.
0: Interrupt request at pin IRQ2 is enabled.
After system is reset, IRQ2D is set to "0".
IRQ 1 Disable (IRQ 1D):
L------ Read/write enabled.
1: Interrupt request at pin IRQ 1 is disabled.
0: Interrupt request at pin IRQ 1 is enabled.
After system is reset, IRQ 1D is set to "0".
Timer Interrupt Disable (TIQD):

' - - - - - - - - - Read/write enabled.

1: Timer interrupt request is disabled.
0: Timer interrupt request is enabled.
After system is reset, TIQD is set to "0".

Fig. 2-4-3 Interrupt Disable Register

Data can be read from or written to the interrupt disable register at logical addresses from
1FF400,6 to 1FF7FF,6 where (A1, AO) = (1, 0).

HB-16
2.4.7 Break (BRK)
Break (BRK) is a pseudointerrupt which is caused by software. It occurs unconditionally
whenever a BRK instruction is executed.
( 1) Interrupt Caused by BRK Instruction
When a BRK instruction is executed, the CPU reads the low byte at address FFF6,s and the
high byte at address FFF7,s, and calls the interrupt handling subroutine.
(2) Operation of Interrupt Handling Subroutine
In the subroutine call sequence, the contents of the program counter (PCH, PCL) and the
status register (P) are pushed into the stack in that order (i.e., PCH, PCL and P). In the write
cycle to the the stack, the stack pointer (S) is postdecremented.
The break command (B) in the status register to be pushed into the stack is set to "1".
The CPU sets Interrupt Disable (I) and resets Decimal (D).
The vector address which is read from memory is the same as that of Interrupt Request 2
(IRQ2 input). Therefore, it is necessary to check, using the interrupt handling subroutine, the
value of the break command saved in the stack to see whether the interrupt of interest was
caused by a BRK instruction or Interrupt Request 2 (IRQ2).
(3) Returning from Interrupt Handling Subroutine
If an interrupt is caused by a BRK instruction, the value of the program counter (PCH, PCL)
+ 2). When the RTI instruction is executed, the program
to be pushed into the stack is (BRK
returns to address (BRK + 2) and the instruction inserted at address (BRK + 1) is ignored.
The program assumes the data at (BRK + 2) is an instruction code and restarts processing.

HB-17
2. 5 System Reset
( 1) System Resetting Procedure
System can be reset by setting the RESET input pin to "L" level. Returning the pin to "H"
level causes the system to start.
The "L" level applied to the pin must be a pulse which has a duration of at least 28 clock
cycles with the clock input at OSC 1 fully stabilized.
(2) Internal States after System Reset
When the system resumes after a reset, the program reads the low byte at physical address
001 FFE,s and the high byte at physical address 001 FFF,s, and starts.
A system reset causes the following internal states:
• Interrupt Disable (I) is set.
e The Decimal flag (D) is reset.
e "OO,s" is set in the MPR7 mapping register.
e The timer is stopped.
e The interrupt disable register is all reset.
• Timer Interrupt Request (TIQ) is reset.
e Low speed mode is set.
• "H" level is output to the output port (port 0).
• The interrupt circuit is initialized.
• The Memory Operation flag (T) is reset.
• The ready state is cleared.
• "H" level is output to the RD/WR pins.
• "L" level is output to the SYNC pin.
• Both the data bus and address bus provide invalid data.
e CE7, CEK, CER and A20 provide invalid data.
Only one of these four pins produces "L" level.
• System clock is output to the SX pin.
• "L" level is output to the HSM pin.

HB-18
2.6 1/0
The HuC6280 contains one 8bit input port (port K) and one 8bit output port (port 0).

2.6.1 Port K
Port K consists of 8 bits numbered KO- K7. Its input is of TTL level interface, with a pull up
resistor. Executing a read cycle at physical addresses from 1 FFOOO,s to 1FF3FF,s causes KO- K7
to be read into the device.

2.6.2 Port 0
Port 0 consists of 8 bits numbered 00-07, and has a latch. Its output is of a complementary
type. When the system is reset, the port provides an "H" level output.
Executing a write cycle at physical addresses from 1FFOOO,s to 1FF3FF,s causes data to be
output to 00-07.

Example of addressing to 1/0 port;

Physical address 1OOO,s with MPRO=FF,s

HB-19
2. 7 Timer
The HuC6280 has a 7bit timer.
( 1) Organization of Timer
Fig. 2- 7-1 shows the organization of the timer. It consists of a 7bit downcounter, a 7bit
reload register, a timer control register, and a prescaler.
e Downcounter
The downcounter (binary) receives the output of the prescaler and counts down.
• Reload Register
The contents of the reload register (7 bits) are loaded to the downcounter when the
Start/Stop flagof the control register changes from "0" to "1" or when a borrow occurs
in the downcounter.
e Timer Control Register
The timer control register ( 1 bit) is the Timer Start/Stop flag, as shown in Fig. 2- 7-1.
• Prescaler
The prescaler consists of ten frequency dividers each of which divides the input frequency
by 2. The signal from OSC 1 is divided by 3 to obtain a clock signal PPS3. PPS3 is further
divided by 1,024 (decimal) and supplied to the down counter.
(2) Writing Data to Reload Register
Executing a write cycle at physical addresses from
1FECOO,e to 1FEFFF,s causes bits 6 to 0 of write
data to be loaded into the reload register.
(3) Writing Data to Timer Control Register
Executing a write cycle at physical addresses from
1FECOO,s to 1 FEFFF,s causes bit 0 of write data
to be loaded into the timer control register.
(4) Reading Data from Timer
Executing a read cycle at physical addresses from
1 FECOO,s to 1FEFFF,s causes the contents of the
downcounter to be loaded to bits 60.
(5) Timer Operation
• System reset
Once the system has been reset, the data of both the reload register and the downcounter
are invalid. The Timer Start/Stop flag of the timer control register is reset.

H8-20
e Timer operation
When a timer interval is set in the reload register and the Timer Start/Stop flag is set,
the data in the reload register is loaded to the downcounter and the timer starts
countingdown. If a borrow occurs in the downcounter, Timer Interrupt Request (TIQ) of
the interrupt request register is set. The CPU is requested to handle a timer interrupt if
Timer Interrupt Disable (TIQD) is "0" and Interrupt Disable (I) is "0". At the same time, the
downcounter is loaded with the data of the reload register to have the timer continue
countingdown. Once an interrupt request has occurred and has been
handled, Timer Interrupt Request (TIQ) must be reset by executing a write cycle to the
interrupt request register.
e Interval control
The contents of the reload register can be updated while the timer is counting down. By
doing so it is possible to control the interval of interrupts.
When "0" is written in the Timer Start/Stop flag, the time stops and the prescaler is reset.
If a 2 1.48 MHz clock is used, the prescaler output frequency (f) is given as follows:
f = 21.48 MHz + 3 + 1024 = 6.992 KHz
Then the timer can be used for generating a time interval of interrupt request from 143
tJ-Sec to 18.3 msec.
e CAUTION:
When reading data from the downcounter, the count value can become invalid. It is
important to read data twice and compare two values with each other to assure data.

HB-21
 u-sus
I 7 (bit 6- bIt 0)
7
7-bit reload
(bIt 0) (bit 6-
b It 0)
Timer control
AO register

PPS3 Prescaler

Example of addressing to reload register and

down-counter:
Logical address OCOO,s with MPRO=FF,s

Fig. 2-7-1 Organization of Timer

MSB LSB Timer Control Register

~~--~--~--~--~--r-~~ST-A~RT (CET=O,A0=1)
/SiOP
Example of addressing:
Logical address OCO 1,s with MPRO= FF,s
(not used)

'--- 1: Timer continues to count down.

0: Timer stops.
The downcounter is loaded with the data of
the reload register when the Timer
Start/Stop flag changes from "0'" to '"1 ".

Fig. 2-7-2 Organization of Timer Control Register

HB-22
2. 8 Programmable Sound Generator (PSG)
The HuC6280 contains a programmable sound generator (PSG). For the operation of the PSG,
see its manual. The following signals flow from the CPU to the PSG for interfacing:
• DO- 07 (bidirectional data bus)
e RD, WR, CEP (PSG Chip Enable)
• AO -A3 (4 bits of address)
e CLKP (f =clock ~OSC1))

e RESET
• SX (output signal of system clock S3)

HB-23
2. 9 Device/Register Addresses
Physical Example of addressing
(hexadecimal) Device name Organization and function of bit
No. address
(Register name) (hexadecimal)
(hexadecimal) MPR Logical address

1 1FE000 MPRO= DODO HuC6270 Logical address Instruction for HuC6270

' FF 0002 (A 1 -AO) 0000 ST 0
1 FE3 F F 0003 0002 ST 1
0003 ST 2

2 1 FE4 0 0 MPRO= 0400 HuC6260

'' FF (A2-AO) --
1 FE7 F F 0407

3 1FE800 MPRO= 0800 PSG

''' FF ' (A3-AO) --
1 F E BF F 080F

4 1 F E C0 0 MPRO= 0 c0 1 Timer control register 7 6 5 4 3 2 1

1 1 1 1 1 1 1 1°1
'' FF (write only)
1 FEFFF Reserved
(AO= 1) 1: Timer start
0: Timer stop

1 F E C0 0 MPRO= ocoo Write cycle: 1]7]6]5]4]3]2]1 joj

' FF Timer reload register
''
1 FEFFF Timer interval setting
(AO=O) (7 bits)
Reserved

Read cycle: 1[7[6[5[4[3]2[1 joj

Timer downcounter
Timer downcounter
(7 bits)
Reserved

5 1FF000 MPRO= 10 00 Write cycle: port 0 07-00 Output to 07-00

'' FF
1FF3FF
Read cycle: port K Input from K7- KO

6 1 F F4 0 0 MPRO= 1 4 0 2 Interrupt disable regis- 171615141312111ol

'' FF ter (read/write enabled)
'
1 FF7 FF Reserved
IRQ2D 1: Disable
(A1=1)
AO=O (bit 0) 0: Enable
IRQ1D 1: Disable
(bit 1) 0: Enable
TIQD 1: Disable
(bit 2) 0: Enable

1 F F4 0 0 MPRO= 1403 Interrupt request regis- 171615141312111ol

FF ter (read; TIQ reset at
1 FF7 F F write) Reserved
(A1=1) IRQ2 1: Interrupt request
A0=1 (bitO) 0: No interrupt request
IRQ 1 1: Interrupt request
(bit1) 0: No interrupt request
TIQ 1: Interrupt request
(bit2) 0: No interrupt request

7 1FOOOO MPR1= 2000 DATA MEMORY

F8 (RAM)
1 FF7 FF ' 3 FFF
FB

H8-24
3. INSTRUCTION MAP
IR3 0 1

IR2 0 1 1 0

IR1 0 1 1 0 0 1 1 0

IR7 IR6 IRS IR4

IRO 0
I 1 1
I 0 0 I 1 1
I 0 0
I 1 1
I 0 0
I 1 1 I 0

BRK ORA STO SXY ASL RMBO ORA TSB TSB ORA BBRO ASL ASL ORA PHP
0 IMPLED (IND.X) IMM IMPLED ZP ZP ZP ZP ABS ABS ZP ABS ACC IMM IMPLED

18 2 7 2 4 13 2 6 2 7 2 4 26 3 7 3 5 3 6 3 7 1 2 2 2 1 3
0 1---
BPL ORA ST1 ORA ASL RMB1 ORA TRB TRB ORA BBR1 ASL INC ORA CLC
1 REL (IND).Y IMM (IN D) ZP.X ZP ZP.X ZP ABS ABS.X ZP ABS.X ACC ABS.Y IMPLED
2 2 2 7 2 4 2 7 2 6 2 7 2 4 26 3 7 35 36 37 1 2 3 5 1 2
0
BMI AND AND ROL ROL RMB3 AND BIT AND BBR3 ROL DEC AND SEC
1 REL (IND).Y (IN D) (IN D) ZP.X ZP ZP.X ABS.X ABS.X ZP ABS.X ACC ABS.Y IMPLED
2 2 2 7 2 7 2 7 26 2 7 24 3 5 3 5 36 3 7 1 2 3 5 1 2
1 1---
JSR AND ST2 SAX ROL RMB2 AND BIT BIT AND BBR2 ROL ROL AND PLP
0 ABS (IND.X) IMM IMPLED ZP ZP ZP ZP ABS ABS ZP ABS ACC IMM IMPLED

37 2 7 2 4 1 3 2 6 2 7 2 4 2 4 3 5 3 5 36 3 7 1 2 2 2 14
0
RTS ADC CLA ROR RMB6 ADC STZ JMP ADS BBR6 ROR ROR ADC PLA
0 IMPLED (IND.X) IMPLED ZP ZP ZP ZP (ABS) ABS ZP ABS ACC IMM IMPLED

1 7 2 7 1 2 2 6 2 7 2 4 2 4 3 7 3 5 36 37 1 2 2 2 14
1 1---
BVS ADC Til ADC ROR RMB7 ADC STZ JMP ADC BBR7 ROR PLY ADC SEI
1 REL (IND).Y IMPLED (IN D) ZP.X ZP ZP.X ZP.X ABS.X ABS.X) ZP ABS.X IMPLED ABS.Y IMPLED
2 2 2 7 7* 2 7 2 6 2 7 2 4 2 4 3 7 3 5 36 3 7 14 3 5 12
1
BVC EOR TAMi EOR LSR RMB5 EOR CSL EOR BBR5 LSR PHY EOR CLI
1 REL IND). Y IMPLED (IN D) ZP.X ZP ZP.X IMPLED ABS.X ZP ABS.X IMPLED ABS.Y IMPLED
2 2 2 7 2 5 27 2 6 2 7 2 4 13 3 5 36 3 7 1 3 3 5 1 2
0 1---
RT1 EOR TRAi SAY LSR RMB4 EOR BSR JMP EOR BBR4 LSR LSR EOR PHA
0 IMPLED (IND.X) IMPLED IMPLED ZP ZP ZP REL ABS ABS ZP ABS ACC IMM IMPLED

1 7 2 7 2 4 1 3 2 6 2 7 2 4 2 8 3 4 3 5 36 3 7 1 2 2 2 13

CPY CMP TDD CLY DEC SMB4 CMP CPY CPY CMP BBS4 DEC DEX CMP INY
0 IMM
2 2
(IND.X) IMPLED IMPLED
2 7 12
ZP
2 6
I 2ZP7 ZP
24
ZP
24
ABS
3 5
ABS
3 5
ZP
3 6
ABS
3 7
IMPLED

12
IMM
2 2
IMPLED

1 2
7*
0 1---
BNE CMP TIN CMP DEC SMB5 CMP CSH CMP BBS5 DEC PHX CMP CLD
I 1 REL IND). Y IMPLED (IN D) ZP.X ZP ZP.X IMPLED ABS.X ZP ABS.X IMPLED ABS.Y IMPLED
I 2 2 2 7 7* 2 7 2 6 2 7 2 4 1 3 3 5 3 6 3 7 13 3 5 1 2

I 1
I
I

~J
II BEO SBC TAl SBC INC SMB7 SBC SET SBC BBS7 INC PLX SBC SED
REL I(IND).Y IMPLED (IN D) ZP.X ZP ZP.X IMPLED ABS.X ZP ABS.X IMPLED ABS.Y IMPLED
2 2 2 7 7* 2 7 2 6 2 7 2 4 1 2 3 5 3 6 3 7 1 4 3 5 12
i 1

I i CPX INX
, I CPX
IMM
SBC
(IND.X) IMPLED
TIA
I INC
ZP
SMB61
ZP
SBC
ZP ZP
CPX
ABS
SBC •BBS6

I ABS ZP
INC
ABS
NCP
IMPLED
SBC
IMM IMPLED
I
2 2 2 7
17* 2 6 2 7 i 2 4 2 4 3 5 3 5 3 6 3 7 12 I 2 2 1 2

I'~:' I
LDY LDA tST IMM LDX LDX LDA LDY LDY LDA BBS2 LDX TAX LDA TAY
I
IMM (IND.X) ZP.X IMM ZP ZP ZP ABS ABS ZP ABS IMPLED I IMM IMPLED
I 2 2 2 7 3 7 2 2 2 4
I 2 4 2 4 35 3 5 3 6 3 5 2 2 1 2
1 2 1
I I 2 7

I LDA ~ST
1
I '
j I BCS I LDA TSX '
II 1 '
I REL fiND). Y~ABS.X
iMM LDA
(IN D)
LDX lsMB3
ZP.Y · ZP ZP 'ZP.X
LDA LDY
ABS.X ABS.X
LOA BBS3
ZP
LDX
IABS.Y IMPLED I IABS.Y
LDA
CLV

I I
I 2 2 I z1 I 4 8 2 7 2 4 I27 2 7 2 4 3 5 3 5 3 6 3 5 1 2 3 5
IMPLED

1 2
I
0 I I
II BCC STA STIMM STA STX SM81 STA STY STZ STA 8851 STZ TXS STA TVA
1 REL IND). Y ABS (IN D) ZP.Y ZP ZP.X ZP.X ABS ABS.X ZP ABS.X IMPLED ABS.Y IMPLED
I
I I 2 2 2 7 4 8 2 7
I
2 4 2 7 2 4 2 4 3 5 3 5 3 6 35 1 2 35 12
0 1---
BRA STA STIMM CLX STX SMBO STA STY STY STA BBSO STX TXA BIT DY
0 REL (IND.X) ZP IMPLED ZP ZP ZP ZP ABS ABS ZP ABS IMPLED IMM IMPLED

2 4 2 7 3 7 12 2 4 2 7 2 4 2 4 3 5 3 5 3 6 3 5 1 2 2 2 12

'17+ 16z

HB-25