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Application Note
Using the TPS6284x in an Inverting Buck-Boost Topology

Andreas Mueller
ABSTRACT
The TPS6284x family is a high-efficiency step-down converter with ultra-low operating quiescent current of
typically 60nA. The device contains special circuitry to achieve just 120nA IQ in 100% mode to further extend
battery life near the end of discharge. With an input voltage of 1.8V to 6.5V, the device supports multiple
power sources such as 2S to 4S Alkaline, 1S to 2S Li-MnO2, or 1S Li-Ion/Li-SOCl2. These devices are
well-designed for many battery powered applications, such as smart meters, medical sensor patches, industrial
IoT (smart sensors) and other test and measurement equipment. The analog signal chain in such applications
often requires symmetrical supply voltage or negative voltage biasing. The TPS6284x can be configured in an
inverting buck-boost topology, where the output voltage is inverted or negative with respect to ground. This
application report describes the inverting buck-boost topology in detail for the TPS6284x family.

Note
Precautions need to be taken when using these devices in an inverting buck-boost topology. Please
review section Section 2 to understand and robustly eliminate known risk.

Table of Contents
1 Inverting Buck-Boost Topology.............................................................................................................................................2
1.1 Concept..............................................................................................................................................................................2
1.2 Output Current Calculations...............................................................................................................................................3
1.3 VIN and VOUT Range.......................................................................................................................................................... 5
2 Design Considerations...........................................................................................................................................................5
2.1 Additional Input Capacitor.................................................................................................................................................. 5
2.2 Digital Input Pin Configurations..........................................................................................................................................6
2.3 Startup Behavior and Switching Node Consideration........................................................................................................ 7
3 External Component Selection..............................................................................................................................................8
3.1 Inductor Selection.............................................................................................................................................................. 8
3.2 Capacitor Selection............................................................................................................................................................ 8
4 Typical Performance...............................................................................................................................................................9
5 Summary................................................................................................................................................................................11
6 References.............................................................................................................................................................................11
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1 Inverting Buck-Boost Topology

1.1 Concept
The inverting buck-boost topology is very similar to the buck topology. In a standard buck configuration, shown in
Figure 1-1, the positive connection (VOUT) is connected to the inductor and the return connection is connected to
the device ground.

L1
VIN VIN SW VOUT

EN VOS
COUT
VSET
CIN
MODE

RSET STOP GND

GND GND

Figure 1-1. Buck Topology

However, in the inverting buck-boost configuration illustrated in Figure 1-2, the device ground is used as the
negative output voltage pin (labeled as VOUT). What was previously the positive output in the buck configuration
is now used as the ground (GND). This shift in topology allows the output voltage to be inverted and always
remain lower than the ground.
CIN

VIN

GND

L1
VIN SW

EN VOS GND

COUT
VSET
CBYP
MODE

RSET STOP GND VOUT

Figure 1-2. Inverting Buck-Boost Topology

The circuit operation in the inverting buck-boost topology differs from that in the buck topology. Though the
components are connected the same as with a buck converter, the output voltage terminals are reversed, as
Figure 1-3 shows. During the on time of the control MOSFET, shown in Figure 1-4, the inductor is charged with
current, while the output capacitor supplies the load current. The inductor does not provide current to the load
during that time. During the off time of the control MOSFET and the on time of the synchronous MOSFET, shown
in Figure 1-5, the inductor provides current to the load and the output capacitor. These changes affect many
parameters, as discussed in the Design Considerations section.

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Q1 +
+ VIN
VIN Control Q1
– –
Control
iL iL

VSW GND VSW

GND
GND GND GND
+ +
Q2 COUT Q2 COUT
Sync RLOAD Sync RLOAD

- -

VOUT VOUT
IOUT IOUT

Figure 1-3. Buck-Boost Configuration Figure 1-4. Buck-Boost On Time

+ Q1
VIN
– Control

iL

GND VSW

GND
+
COUT
Q2
Sync RLOAD
-

VOUT
IOUT

Figure 1-5. Buck-Boost Off Time

1.2 Output Current Calculations

The average inductor current is also affected in this topology. In the buck configuration, the average inductor
current is equal to the average output current because the inductor always supplies current to the load during
both the on and off times of the control MOSFET. However, in the inverting buck-boost configuration, the load
is supplied with current only from the output capacitor and is completely disconnected from the inductor during
the on time of the control MOSFET. During the off time, the inductor connects to both the output capacitor and
the load (see Figure 1-5). Knowing that the off time is (1 – D) of the switching period, Equation 1 can be used to
calculate the average inductor current:

I
IL Avg = OUT (1)
1−D

The operating duty cycle for an inverting buck-boost converter can be found with Equation 2:

VOUT
D= (2)
VOUT − VIN × η

Rather than VOUT/VIN for a buck converter. The efficiency term in Equation 2 adjusts the equations in this section
for power conversion losses and yields a more accurate maximum output current result. The peak-to-peak
inductor ripple current is given by Equation 3:

V ×D
ΔIL = fIN× L (3)
S

where:
• ΔIL (A): the peak-to-peak inductor ripple current
• D: duty cycle
• η: efficiency
• fS (MHz): switching frequency
• L (μH): inductor value

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• VIN (V): the input voltage with respect to ground, not with respect to the device ground or VOUT
Equation 4 calculates the maximum inductor current:

ΔI
IL = IL avg + 2L (4)

For example, for an output voltage of –1.8V, 2.2μH inductor, and input voltage of 3.3V, the following calculations
produce the maximum allowable output current that can be achieved based on the TPS62840 minimum current
limit value of 1A. The efficiency term is estimated at 80 %.

VOUT −1 . 8 V
D= = = 0 . 441 (5)
VOUT − VIN × η − 1.8 V − 3.3 V × 0.8

V ×D
ΔIL = fIN× L = 1 . 83 . 3MHz
V × 0 . 441
× 2 . 2 μH = 368 mA (6)
S

Rearranging Equation 4 and setting IL(max) equal to the minimum value of ILIMF, as specified in the data sheet,
gives:

ΔI
IL avg = IL max − 2L = 1000 mA − 3682 mA = 816 mA (7)

This result is then used in Equation 1 to calculate the maximum achievable output current:

IOUT = IL avg × 1 − D = 816 mA × 1 − 0 . 441 = 456 mA (8)

Table 1-1 provides several examples of the calculated maximum output currents for different output voltages
(–1.8V, –1.5V and –1.2V) based on an inductor value and switching frequency of 2.2μH and 1.8MHz,
respectively. Increasing the inductance and/or input voltage allows higher output currents in the inverting buck-
boost configuration. The maximum output currents for the TPS62840 in the inverting buck-boost topology are
frequently lower than 750mA due to the fact that the average inductor current is higher than that of a typical
buck. The output current for the same three output voltages and different input voltages is displayed in Figure
1-6.
Table 1-1. Maximum Output Current Calculation for Different Values of VOUT
Parameter VOUT = -1.8V VOUT = -1.5V VOUT = -1.2V
VIN (V) 3.3 3.3 3.3
η 0.8 0.8 0.8
fs (MHz) 1.8 1.8 1.8
L (μH) 2.2 2.2 2.2
IL(max) (mA) 1000 1000 1000
D 0.441 0.391 0.333
ΔIL (mA) 368 326 278
IL(avg) (mA) 816 837 861
IOUT (mA) 456 510 574

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700
VOUT = -1.8 V
660 VOUT = -1.5 V
620 VOUT = -1.2 V

580
IOUT (mA) 540
500
460
420
380
340
300
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VIN (V)
Figure 1-6. Maximum Output Current versus VIN

1.3 VIN and VOUT Range

The input voltage that can be applied to an inverting buck-boost converter IC is less than the input voltage
that can be applied to the same buck converter IC. This is because the ground pin of the IC is connected to
the (negative) output voltage. Therefore, the input voltage across the device is VIN to VOUT, not VIN to ground.
Thus, the input voltage range of the TPS6284x is 1.8V to 6.5V + VOUT, where VOUT is a negative value. The
output voltage range is the same as when configured as a buck converter, but negative. The output voltage for
the inverting buck-boost topology can be set the same way as in the buck configuration, with the RSET resistor
connected to the device GND pin.
2 Design Considerations
2.1 Additional Input Capacitor
An additional input capacitor, CBYP, is required for stability as a bypass capacitor for the device. This capacitor is
in addition to the input capacitor, CIN, from VIN to ground (refer to Figure 1-2). The recommended minimum value
for the bypass capacitor and the input capacitor is 4.7μF. As a side effect, the CBYP capacitor provides an AC
path from VIN to VOUT and together with COUT a capacitive voltage divider is build against GND. In the moment
when VIN is applied to the circuit, the capacitive voltage divider is pulling up VOUT above GND, which is causing
a positive prebias of the negative rail. This also means the IC GND pin (connected to VOUT) is also prebiased
positive, which is pulling SW pin and VOS pin more than 0.3V below IC ground, violating the absolute maximum
rating. Such a condition can damage the device and is not recommended. Therefore, a Schottky diode (D1) has
to be installed on the output, per Figure 2-1. Startup testing needs to be conducted to verify that the VOS pin is
not driven more than 0.3V below IC ground when VIN is applied.

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CIN

VIN

GND

L1
VIN SW GND

EN VOS GND

COUT
VSET
D1
CBYP
MODE

RSET STOP GND VOUT

Figure 2-1. Inverting Buck-Boost Topology With Schottky Diode

The AC path through CBYP can also worsen the line transient response. If strong line transients are expected,
the output capacitance can be increased to keep the output voltage within acceptable levels during the line
transient.
The TPS6284x can operate without the bypass capacitor and without Schottky diode, but care must be taken
to verify stability in the individual application and to check that the SW and VOS pin signals do not violate the
recommended operating conditions during startup.
2.2 Digital Input Pin Configurations
Because VOUT is the IC ground in this configuration, the EN pin must be referenced to VOUT instead of the
ground. In a buck configuration, the specified threshold voltage for the enable pin in the product data sheet
is 1.1V to be considered high and 0.4V to be considered low (see the TPS62840 product data sheet). In the
inverting buck-boost configuration, however, the VOUT voltage is the reference; therefore, the high threshold is
1.1V + VOUT and the low threshold is 0.4V + VOUT. For example, if VOUT = -1.8V, the VEN is considered a high
level for voltages above –0.7V and a low level for voltages below –1.4V. The same effect is true with the MODE
and STOP pins. This behavior can cause difficulties enabling or disabling the part, since in some applications,
the IC providing the EN signal cannot produce negative voltages. The level shifter shown in Figure 2-2 alleviates
any problems associated with the offset EN threshold voltages by eliminating the need for negative EN signals.
VIN

S G
Q2
1M PMOS
D

D
Q1 EN
G NMOS
SYS_EN
S
1M

GND

VOUT

Figure 2-2. EN Pin Level Shifter

The positive signal that originally drove EN is instead tied to the gate of Q1 (SYS_EN). When Q1 is off (SYS_EN
grounded), Q2 sees 0V across the VGS, and also remains off. In this state, the EN pin sees VOUT which is

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below the low level threshold and disables the device. When SYS_EN provides enough positive voltage to turn
Q1 on (minimum VGS as specified in the MOSFET’s data sheet), the gate of Q2 is pulled low through Q1. This
drives the VGS of Q2 negative and turns Q2 on. As a consequence, VIN ties to EN through Q2 and the pin
is above the high level threshold, causing the device to turn on. Make sure that the VGD of Q2 remains within
the MOSFET’s ratings during both enabled and disabled states. Failing to adhere to this constraint can result in
damaged MOSFETs. The enable and disable sequence is illustrated in Figure 2-3 and Figure 2-4. The SYS_EN
signal activates the enable circuit, and the G/D NODE signal represents the shared node between Q1 and Q2.
The EN signal is the output of the circuit and goes from VIN to –VOUT properly enabling and disabling the
device.

Figure 2-3. EN Pin Level Shifter on Startup Figure 2-4. EN Pin Level Shifter on Shutdown

2.3 Startup Behavior and Switching Node Consideration

In the inverting buck-boost topology, the voltage on the SW pin switches from VIN to VOUT, instead of from VIN
to GND. As the high-side MOSFET turns on, the SW node sees the input voltage; as the low-side MOSFET
turns on, the SW node sees the device ground, which is the output voltage. During startup, VIN rises to achieve
the desired input voltage. VOUT starts ramping down after the EN pin voltage exceeds the threshold level and
VIN exceeds the UVLO threshold. As VOUT continues to ramp down, the SW node low level follows VOUT
down. Figure 2-5 shows the resulting normal and smooth startup of the output voltage.

Figure 2-5. SW Node Voltage During Startup

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3 External Component Selection

The inductor and output capacitor must both be selected based on the requirements of the application and the
stability criteria of the device, which are different from the traditional buck converter approach. A load transient
test needs to be performed to evaluate stability. Figure 4-7 shows the results of such a test performed on the
example circuit. The lack of ringing indicates stability.
3.1 Inductor Selection
To select the inductor value for the inverting buck-boost topology, use Equation 1 through Equation 4 instead
of the equations provided in the TPS62840 data sheet. These formulas help to select the proper inductance by
designing for a maximum inductor current (IL(Max)) or finding the peak inductor current for a given inductance.
IL(Max) needs to be kept below the device minimum current limit value for a reliable design. The worst-case IL(Max)
occurs at the minimum VIN for a given design. Once IL(Max) is determined, the recommendation is to choose an
inductor with a saturation rating 20 % to 30 % higher than IL(Max) to allow for peak currents that can occur during
startup or load transients. For the inverting buckboost topology, the recommended inductance is 2.2μH.
3.2 Capacitor Selection
Tiny ceramic capacitors with low equivalent series resistance (ESR) are desired to have low output voltage
ripple. X5R- or X7R-type dielectrics are recommended for the stable capacitance versus temperature
characteristics. A minimum 10μF capacitor is recommended for both CBYP and CIN. These capacitance values
can be increased without limit. For the output capacitor, a minimum of 22μF is recommended. Making this
capacitor value too great can cause instability. This situation can be evaluated through a Bode plot or load
transient response. The voltage rating of CBYP must be greater than (VIN + VOUT).

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4 Typical Performance
The reference design with VOUT = -1.8V, as shown in Figure 4-1 was used to generate the typical characteristic
graphs presented in this section and shown in Figure 4-2 through Figure 4-9.
4.7 μF

2.2 μ
VIN
VIN SW GND
1.8 ... 4.7 V 47 μF 4.7 μF
GND EN VOS GND VOUT
- 1.8 V
GND 10 μF
VSET
SS2P3L

MODE

0
STOP GND

Figure 4-1. Schematic of the Tested Circuit

100 0.1
95 0.08
90 0.06
Line Regulation (%)

85 0.04
Efficiency (%)

80 0.02
75 0
70 -0.02
65 -0.04
60 -0.06
55 -0.08
50 -0.1
1E-5 0.0001 0.001 0.01 0.1 0.5 1.5 2 2.5 3 3.5 4 4.5 5
IOUT (A) Vin (V)

Figure 4-2. Efficiency vs Load Current with VIN = Figure 4-3. Line Regulation at 320mA Load
3.3V, VOUT = 1.8V

Figure 4-4. Load Regulation at VIN = 3.3V, VOUT = -1.8V

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Figure 4-5. Startup on VIN at 450mA Load, VIN = Figure 4-6. Shutdown on VIN at 450mA Load, VIN =
3.3V, VOUT = -1.8V 3.3V, VOUT = -1.8V

Figure 4-7. Load Transient Response, 0mA to Figure 4-8. Output Voltage Ripple, VIN = 3.3V, VOUT
400mA at 1A/μs With VIN = 3.3V, VOUT = -1.8V = -1.8V and IOUT = 450mA

70 210
60 180
50 150
40 120
30 90
Gain Magnitude (dB)

20 60
Gain Phase (°)

10 30
0 0
-10 -30
-20 -60
-30 -90
-40 -120
-50 Gain Magnitude (dB) -150
-60 Gain Phase (°) -180
-70 -210
1E+2 1E+3 1E+4 1E+5 1E+6
Frequency (Hz)

Figure 4-9. Bode Plot at VIN = 3.3V, VOUT = -1.8V and 450mA Load

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5 Summary
The TPS62840 buck dc-to-dc converter can be configured as an inverting buck-boost converter to generate a
negative output voltage. The inverting buck-boost topology changes some system characteristics, such as input
voltage range and maximum output current. This application report explains the inverting buck-boost topology
and how to select the proper values of external components with the changed system characteristics. TPS62840
also gives design guidelines and precautions to make sure the robust operation of the converter. Measured data
from the example design are provided. This application report also applies to any of the devices in the TPS6284x
family.
6 References
1. Texas Instruments, Using the TPS6215x in an Inverting Buck-Boost Topology, application note.
2. Texas Instruments, TPS62840 1.8-V to 6.5-V, 750-mA, 60-nA IQ Step-Down Converter, data sheet.

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