Booth Algorithm and fast

multiplication
 Booth Algorithm
• A powerful algorithm for signed-number multiplication
– treats positive and negative numbers uniformly
• So far, the number of additions equals the number of 1s
in the multiplier
• Consider a multiplication in which the multiplier is
positive and has a single block of 1s (e.g., 00111102 =
3010)
• To derive the product, we could add four appropriately
shifted versions of the multiplicand (i.e., for four 1s)
• We can reduce the number of operations by regarding
the multiplier as the difference between two numbers,
i.e., 3210-210 or 01000002-00000102
• This suggests
5
that the product can be generated by
adding
1
2 times the multiplicand to the 2's complement
of 2 times the multiplicand
• The sequence of required operations can be recoded as
0+1000-10
2
 Booth recoding of a multiplier
-1 times the shifted multiplicand is selected when changing multiplier from 0
to 1
+1 times the shifted multiplicand is selected when changing multiplier from 1
to 0
The multiplier is scanned form right to left
 Booth Multiplier Recoding Scheme

Multiplier
Version of multiplicand
selected by bit i
Bi i Bi i -1
t t
0 0 0×M
0 1 +1×M
1 0 −1×M
1 1 0×M

8
 Normal and Booth Multiplication Schemes
0 1 0 1 1 0 1
0 0 +1 +1 + 1+1 0
0 0 0 0 0 0 0
0 1 0 1 1 0 1
Normal 0 1 0 1 1 0 1
0 1 0 1 1 0 1
0 1 0 1 1 0 1
0 0 0 0 0 0 0
0 0 0 0 0 0 0
0 0 0 1 0 1 0 1 0 0 0 1 1 0

0 1 0 1 1 0 1
0 +1 0 0 0 -1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0
2's complement
1 1 1 1 1 1 1 0 1 0 0 1 1
of
the
0 0 0 0 0 0 0 0 0 0 0 0
multiplicand
Booth 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0
0 0 0 1 0 1 1 0 1
0 0 0 0 0 0 0 0
0 0 0 1 0 1 0 1 0 0 0 1 1 0

9
 Booth Recoding of a Multiplier

0 0 1 0 1 1 0 0 1 1 1 0 1 0 1 1 0 0

0 +1 -1 +1 0 - 1 0 +1 0 0 - 1 +1 - 1 + 1 0 - 1 0 0

• When the least significant bit is 1 , assume an implied 0

lies to its right

10
 Booth Multiplication with a Negative Multiplier

0 1 1 0 1 ( + 13) 0 1 1 0 1
× 1 1 0 1 0 (- 6) 0 - 1 +1 - 1 0
0 0 0 0 0 0 0 0 0 0
1 1 1 1 1 0 0 1 1
0 0 0 0 1 1 0 1
1 1 1 0 0 1 1
0 0 0 0 0 0
1 1 1 0 1 1 0 0 1 0 ( - 78)

■ Handles both positive and negative multipliers uniformly

11
 Fast Multiplication
• The techniques used for speeding up the
multiplication operation are
• Bit- Pair Recoding of multipliers
• Carry – Save addition of summands
 Bit-Pair Recoding of Multipliers
⚫ Bit-pair recoding halves the maximum number of
summands (versions of the multiplicand).
Sign extension Implied 0 to right of LSB
1 1 1 0
1 0 0

−
0 0 1 +1
−
1 0

0 − −
1 2

(a) Example of bitpair recoding derived from Booth recoding

Bit-Pair Recoding of Multipliers
Multiplier bitpair Multiplier bit on the right Multiplicand
selected at position i
i+1 i −
i 1
0 0 0 0 X M
0 0 1 +1 X M
0 1 0 +1 X M
0 1 1 +2 X M
1 0 0 − X M
2
1 0 1 − X M
1
1 1 0 − X M
1
1 1 1 0 X M

(b) Table of multiplicand selection decisions

 Bit-Pair Recoding of M u 0 1 1

l t ipliers
0 1
0 1 +1 1 0
0 0 0 0 0 0 0 0 0 0
1 1 1 1 1 0 0 1 1
0 0 0 0 1 1 0 1
0 1 1 0 1 1 1 0 0 1 1
1 ( + 13) 0 0 0 0 0 0
× 1 1 0
1 1 1 0 1 1 0 0 1 0 ( 78)
1 0 ( 6)

0 1 1 0
1
0 1 2
1 1 1 1 1 0 0 1 1
0
1 1 1 1 0 0 1 1
0 0 0 0 0 0
1 1 1 0 1 1 0 0 1
0
Figure 6.15. Multiplication requiring only n/2 summands.41
 Bit-Pair Recoding of M u 0 1 1

l t ipliers
0 1
0 0 0 0 0 0 0 0 0 0
0 1 +1 1 0
1 1 1 1 1 0 0 1 1
0 0 0 0 1 1 0 1
1 1 1 0 0 1 1
0 1 1 0 0 0 0 0 0 0
1 ( + 13) 1 1 1 0 1 1 0 0 1 0 ( 78)
× 1 1 0
1 0 ( 6)

0 1 1 0
1
0 1 2
1 1 1 1 1 0 0 1 1
0
1 1 1 1 0 0 1 1
0 0 0 0 0 0
1 1 1 0 1 1 0 0 1
0
Figure 6.15. Multiplication requiring only n/2 summands.41
Carry-Save Addition of Summands
⚫ CSA speeds up the addition process.

P7 P6 P5 P4 P3 P2 P1 4 P0
2
 Carry-Save Addition of Summands(Cont.,)

P7 P6 P5 P4 P3 P2 P1 P0
Carry-Save Addition of
Summands(Cont.,)
⚫ Consider the addition of many summands, we can:
Group the summands in threes and perform carry-save addition on
each of these groups in parallel to generate a set of S and C vectors in
one full-adder delay
Group all of the S and C vectors into threes, and perform carry-save
addition on them, generating a further set of S and C vectors in one
more full-adder delay
Continue with this process until there are only two vectors remaining
They can be added in a RCA or CLA to produce the desired product
Carry-Save Addition of Summands
M
1 0 1 1 0 1 (45)
Q
X 1 1 1 1 1 1 (63)

A
1 0 1 1 0 1
B
1 0 1 1 0 1
C
1 0 1 1 0 1
D
1 0 1 1 0 1
E
1 0 1 1 0 1
F
1 0 1 1 0 1

1 0 1 1 0 0 0 1 0 0 1 1 (2,835) Product

Figure 6.17. A multiplication example used to illustrate carrysave addition as shown in Figure 6.18.
 1 0 1 1 0 1 M
x 1 1 1 1 1 1 Q

A
1 0 1 1 0 1
B
1 0 1 1 0 1
C
1 0 1 1 0 1

1 1 0 0 0 S1
0 1 1
C1
0 0 1 1 1
1 0 0
1 0 1 1 0 D
E
1 0 1 0 1
1 F
1 1
1 0 1 S2
1 1 10 00 0
0 1 1 C2
0 0 1 1 1
1 0 0 S1
1 1 0 0 0
0 1 1
C1
0 0 1 1 1
1 0 0 S2
11 1 1 0 0 1 0 0 0 1 0 0
S3
0 1 0 1 1 1

0 0 0 0 1 0 1 C3
1 0 0 0
C2
00 1 0 0 1 1 1 1 1 1 1 0 0
1 0 0 0 1 1
S4
+ 0 1 0 1 0 1 0
1 Product
0 0 0 1 0 1 0 0 0 0
C4
1 0 0 1 1

Figure 6.18. The multiplication example from Figure 6.17 performed using
carrysave addition.