U.S.N.

BMS College of Engineering, Bangalore-560019

(Autonomous Institute, Affiliated to VTU, Belgaum)

July / August 2016 Supplementary Examination

Course: Introduction to VLSI Circuits and systems Duration: 3 hrs
Course Code: 10EC5DCVLS Max Marks: 100

Date: 31.07.2016
Instructions:

UNIT 1
1 a) Indicate the design hierarchy of CMOS VLSI chip fabrication. What is the 10
significance of Moore’s law as applicable to CMOS technology.
b) Consider the interconnect pattern shown in figure. The line has a width of 1 unit, an 04
the sheet resistance is Rs= 25 Ω. Find the resistance from A to B if each corner
square contributes a factor of 0.825 of a straight path square.

c) Illustrate the current flow in a NFET . Obtain the expression for the linear 06
resistance Rn of the device.
UNIT 2
2 a) “pFETs is used for pull up and nFETs for pull down in CMOS circuits“ Justify your 10
answer with diagrams and equations.
b) Construct the CMOS logic gate for the functions 10
(i) g= ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅ (ii) h= ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
( )( )( ) (iii) Three input
NOR gate
Start with the minimum-transistor nFET network, and then apply bubble pushing to
find the pFET wiring.
OR
3 a) With a neat diagram, Realize Non-inverting buffer using transmission gate. 05
b) Construct the basic layout for the function F= ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅ 05
c) With a neat diagram, Explain working of NMOS and PMOS pass transistor’s. 10

UNIT 3
4 a) Explain the importance of the following during the process of fabrication 10
i) Lithography ii) Etching iii) Photoresist
b) What is LDD MOSFET ? Why it is used and show the structure of LDD FET and 10
explain the same.
UNIT 4
5 a) Explain mathematically the DC characteristics of an CMOS inverter? 08
b) Consider an inverter circuit that has FET aspect ratios of (W/L)n=6 and (W/L)p=8 in 06
a process where
Kn’=150µA/V2 VTn=0.70V
2
Kp’=620µA/V VTp=0.85V
VDD=3V and total capacitor is 150pF. Compute rise time, fall time and fmax

c) Explain the DC characteristics of NOR gate and derive equations for the switching 06
times of the NOR gate.
OR
6 a) Explain with an example the resizing of an transistor for the high speed circuits? 10
b) Explain power dissipation in CMOS circuits. 10
UNIT 5
7 a) List the advantages of mirror circuit in CMOS logic. 03

b) Discuss the charge sharing concept of dynamic logic circuit. Explain in detail how 10
do you overcome the disadvantages of dynamic logic circuit

c) Draw the clocked CMOS logic circuit for given expression and discuss its working 07
principle.
𝐹 = 𝐴𝐵 𝐶

*******
 U.S.N.

BMS College of Engineering, Bangalore-560019

(Autonomous Institute, Affiliated to VTU, Belgaum)
December 2015 Semester End Main Examinations
Course: Introduction to VLSI Circuits and systems Duration: 3 hrs
Course Code: 10EC5DCVLS Max Marks: 100

Date: 15.12.2015
Instructions:

UNIT 1
1 a) Explain the steps required to design a microprocessor. 10
b) Consider a silicon that is p-type with boron added at a density of 1015 cm-3 , 05
µn=1350cm2/v-sec & µp= 450cm2/v-sec. Calculate the density of majority and
minority charge carriers and resistivity of silicon.
c) With a diagram show the physical structure of MOSFET, why silicon dioxide is 05
used as a insulator.
UNIT 2
2 a) Explain the FET threshold characteristic to show it as switch and also explain the 08
pass characteristics mathematically.
b) Draw the CMOS circuit diagram of the following Boolean equation 12
i. ̅̅̅̅̅̅̅̅̅̅̅̅
ii. ̅̅
iii. ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
( )( )
iv. f=a+b(c+d)
OR
3 a) Explain the working principle of an Transmission gate and also list advantages. 07
b) Implement the XOR gate using both CMOS logic and transmission gate, compare 07
both circuits and define which one is best with respect to area concerns.
c) Draw the layout patterns for the following equations 2+4
i. ̅ (CMOS logic)
ii. (̅ ) (Transmission gate)
UNIT 3
4 a) Explain the CMOS process flow with neat diagrams. 12
b) What do you understand about lithographic process? 08
 UNIT 4
5 a) Give in detail the DC analysis of NAND2 gate along with the layout representation. 12
b) A CMOS inverter is built in a process where k1n = 100µA/V2 k1p = 42µA/V2 08
VTn = +0.70V VTp = -0.80V , VDD = 3.3V Find the midpoint voltage VM if
(W/L)n =10 , (W/L)p=14.
OR
6 a) Illustrate the transient response analysis of given complex function 10
g = ̅̅̅̅̅̅̅̅̅̅̅̅̅̅
( )
b) An inverter uses FET’S with ßn = 2.1mA/V2 and ßp = 1.8mA/V2 . The threshold 10
voltages are given as Vtn = 0.60V, Vtp = -0.70V and the Power supply has a value
of VDD = 5v. The parasitic FET capacitance at the output node is estimated to be
Cfet = 74fF.
1. Find the midpoint voltage Vm
2. Find the values of Rn and Rp

Calculate the rise and fall time at the output when CL= 0 & WHEN CL= 115fF if its
connected to output
UNIT 5
7 a) With an example, explain the working of a Dynamic logic gate and the charge 10
sharing problem.
b) The output node of a C2MOS circuit is tri-stated with a clock signal of Φ = 0 . The 10
output capacitance at the node is Cout = 76fF . The leakage currents are estimated to
be in= 0.46µA and ip = 127nA. The output voltage must be maintained above
a value of 2.4 volts to be interpreted as a logic 1 stage by the next stage .
(i) Find the hold time at the output node if VDD = 5 V.
(ii) Find the hold time at the output node if VDD = 3.3V.
*******
 U.S.N.

BMS College of Engineering, Bangalore-560019

(Autonomous Institute, Affiliated to VTU, Belgaum)

July / August 2017 Supplementary Semester Examinations

Course: FUNDAMENTALS OF VLSI Duration: 3 hrs
Course Code: 16EC5DCFOV Max Marks: 100

Date: 31.07.2017
Instructions: Answer any FIVE choosing one from each Unit

UNIT 1
1 a Discuss circuit partitioning, floorplanning , placement and routing with neat 08
diagrams.
b Explain the following non-ideal I-V effects . 08
(i) Subthreshold conduction
(ii) Tunneling
c Find the subthreshold leakage current of an inverter at room temperature if the input 04
A = 0. Let βn = 2βp = 1 mA/V2, n = 1.0, and |Vt| = 0.4 V. Assume the body
effect and DIBL coefficients are γ = ɳ = 0.

UNIT 2
2 a Illustrate the process of photolithography & compare positive and negative 07
photoresist
b Design a CMOS logic circuit and layout for the function G = 07
c Explain Lambda -based design rules with neat figures. 06

OR
3 a Analyze the DC Characteristics of CMOS Gates by studying an Inverter. 08
b “nFETs pass strong logic 0 and pFETs pass weak logic 0 levels” Justify your 06
answer with diagrams and equations.
c Suppose VDD = 1.2 V and Vt = 0.4 V. Determine Vout in figure for the 06
following. Neglect the body effect.
i) Vin = 0 V ii) Vin = 0.6 V iii) Vin = 0.9 V iv) Vin = 1.2 V.

UNIT 3
4 a Sketch a CMOS logic gate for the following 10
(i) 3 input NAND (ii) 3 input NOR (iii) F =
 b Explain the working of a transmission gate? Implement a MUX using transmission 05
gate .
c Discuss the working of a CMOS tristate inverter with diagrams. 05

UNIT 4

5 a Analyze the bistable behaviour of a cross coupled inverter circuit . 10

b With a neat circuit , explain the operation of a CMOS implementation of a clocked 10
NOR- based SR latch using two simple AOI gates

OR

6 a Illustrate the three methods of static sequencing 10

b Explain the Max-Delay constraints with an example of a flip flop. 05
c Explain time borrowing with an example. 05

UNIT 5

7 a Draw the circuit for a 6 transistor SRAM cell and explain its working. 06
b With a neat diagram , explain the working of a NAND ROM. What are the 08
disadvantages of NAND ROM ?
c Explain the tradeoffs between open, foldeded and twisted bitlines in a dynamic 06
RAM arrays.

*******
 U.S.N.

BMS College of Engineering, Bangalore-560019

(Autonomous Institute, Affiliated to VTU, Belgaum)

December 2016 Semester End Main Examinations

Course: FUNDAMENTALS OF VLSI Duration: 3 hrs
Course Code: 16EC5DCFOV Max Marks: 100

Date: 17.12.2016
Instructions: Answer any FIVE choosing one from each Unit

UNIT 1
1 a Explain VLSI Design flow with flowchart in detail. 09
b Discuss I-V Characteristics of ideal nMOS transistor. 06
c Illustrate the concept of Channel Length modulation 05

UNIT 2
2 a Elaborate the p well fabrication with neat sketches 10
b Discuss layout design rules in detail 10

OR
3 a Obtain the transfer Characteristics of CMOS inverter highlighting the regions of 10
operations of MOS transistor, showing the status of PMOS and NMOS transistors.
b Suppose VDD = 1.2 V and Vt = 0.4 V. Determine Vout in Figure 1 for: 04
a)Vin = 0 V b) Vin = 0.6 V c) Vin = 0.9 V d)Vin = 1.2 V. Neglect the body
effect.

Figure 1

c Discuss Noise margin in detail. 06

UNIT 3
4 a 06
Design a CMOS logic gate circuit that implements . The objective is to
minimize transistor count.
b Design a 3 input CVSL OR/NOR gate. 06
c Sketch 2 input Multiplexer using a)Static CMOS b)Pseudo NMOS 08
 UNIT 4
5 a Demonstrate the working of CMOS implementation of D latch also draw the timing 09
diagram of D latch with Setup and Hold times.
b Illustrate the working operation of Clocked NOR based SR latch Circuit 06
c Demonstrate the Working of NOR based realization of JK master slave flip-flop. 05

OR
6 a Describe in detail the working of Max delay and Min delay Constraints with respect 12
to flipflop.
b Explain the working of Clock skew in detail. 08

UNIT 5
7 a Discuss the working of six transistor static SRAM and SRAM read operation with a 12
neat diagram
b Design a 4word by 6-bit pseudo-nMOS NOR ROM for following contents: 06

Word 0 : 0 1 0 1 0 1
Word 1 : 0 1 1 0 0 1
Word 2 : 1 0 0 1 0 1
Word 3 : 1 0 1 0 1 0
c List any two disadvantages of NAND ROM. 02

*******
 U.S.N.

BMS College of Engineering, Bangalore-560019

(Autonomous Institute, Affiliated to VTU, Belgaum)

January 2017 Semester End Make Up Examinations

Course: FUNDAMENTALS OF VLSI Duration: 3 hrs
Course Code: 16EC5DCFOV Max Marks: 100

Date: 13.01.2017
Instructions: Answer any FIVE choosing one from each Unit

UNIT 1

1 a Derive the I order ideal Shockley model relating the current and voltage for an 10
NMOS transistor in the 3 regions of operation
b With neat circuit diagram, discuss the following CMOS implementations. 10
(i) NAND (ii) NOR (iii) Y =

UNIT 2

2 a Discuss in detail, the λ based design rules with neat illustrations. 10

b Draw the Layout/Stick diagram for the following: 10
i) 3- input NAND ii) Y=

OR
3 a What is the effect of beta ratio on the DC characteristics of a CMOS inverter? 08
b Discuss in detail, the importance of Noise Margin. For the inverter transfer 12
characteristic shown, find the noise margin (Assume suitable values from within
range).

UNIT 3
4 a Discuss bubble pushing with an example. 06
b Design a 4:1 mux using 2:1 mux implemented by transmission gates. 06
c Discuss the following: i) Pseudo NMOS ii) Cascode Voltage switch logic 08
 UNIT 4
5 a Discuss in detail the methods of sequencing blocks of combinational logic. 08
b Explain the following: i) Max-Delay constraints ii) Min- Delay constraints. 12

OR
6 a What is clock skew? Explain with neat diagrams. 10
b Discuss time borrowing with the help of neat diagrams. 10

UNIT 5
7 a What is SRAM? Discuss the 6-Transistor SRAM cell with neat diagrams. 08
b How is read/write operation performed in a memory cell? Explain with neat 12
diagrams.
*******
 U.S.N.

BMS College of Engineering, Bengaluru-560019

Autonomous Institute Affiliated to VTU

December 2017 Semester End Main Examinations

Course: Fundamentals of VLSI Duration: 3 hrs

Course Code: 16EC5DCFOV Max Marks: 100
Date: 16.12.2017

Instructions: Answer five full questions choosing one from each unit. Assume any suitable data
if missing.

UNIT 1
1 a Explain VLSI design flow with relevant diagram. 10
b Explain any 2 non-ideal IV effects of MOS transistor. 6
c Consider the nMOS transistor in a 65nm process with a nominal threshold voltage of 4
0.3v and a doping level of 8x1017 cm-3 .The body is tied to ground with a substrate
contact. How much does the threshold change at room temperature if the source is at
0.6V instead of 0V?
UNIT 2
2 a Mention the main steps in a n-well process and draw the Cross-Sectional view of 10
n-well CMOS inverter.
b Explain Layout design rules based on Lambda. 10
UNIT 3
3 a From basics explain DC characteristics of CMOS Inverter. 6
b Implement the following using CMOS logic gates (With truth table): 6
(i) UNIVERSAL GATES

(ii)
c Discuss CMOS transmission gates and also discuss its merits and demerits. 8
OR
4 a Implement XOR and XNOR using transmission gates. 8
b Discuss multiplexers and tristate buffers implementation in CMOS 8

c What is noise margin. Explain with neat diagram. 4

 UNIT 4
5 a Explain briefly Max delay constraints concept in Flip Flops with relevant diagrams. 8
b Explain time borrowing concept in transparent latches. 8
c Transparent latch based systems are Skew tolerant. Justify. 4
OR
6 a What are regenerative circuits? Explain CMOS bistable element with time domain 6
behavior.
b Explain CMOS NOR2 based SR latch circuit with neat diagram and truth table 7

c Draw a CMOS D Flip-Flop implementation using 2 D Latches and explain its 7

operation
UNIT 5
7 a Explain DRAM sub array architecture with relevant diagram. 12
b Explain programmable ROM and Pseudo nMOS NAND ROM 8
*******
 U.S.N.

BMS College of Engineering, Bengaluru-560019

Autonomous Institute Affiliated to VTU

January 2018 Semester End Make Up Examinations

Course: Fundamentals of VLSI Duration: 3 hrs

Course Code: 16EC5DCFOV Max Marks: 100
Date: 10.01.2018

Instructions: Answer five full questions choosing one from each unit. Assume any suitable data
if missing.

UNIT 1
1 a With a flow chart explain the VLSI design flow starting from the design 10
specification to fabrication.
b Summarize any three non-ideal IV effects of a MOS transistor. 10

UNIT 2
2 a With neat illustrations, discuss the fabrication of CMOS inverter. 12
b Explain briefly -based CMOS layout design rules. 8

UNIT 3
3 a Design a CMOS circuit for the function Z= ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
+ + + and sketch the 8
stick diagram.
b The output of an nFET is used to drive the gate of another nFET as shown in Figure 8
3 below.
Given: VDD= 3.3V, Vt=0.4V

Find the output voltages Vout when the input voltages are at the following values.
i)Va=3.3V and Vb=3.3V.
ii)Va=0.5V and Vb=3.0V.
iii)Va=2.0V and Vb=2.5V.
iv)Va=3.3V and Vb=1.8V.
c Realize a transmission gate (TG)-based 2 to 1 multiplexer. 4
 OR
4 a Discuss the static CMOS inverter DC characteristics. Mention the effects of  ratio 10
on the characteristics.
b What is Noise Margin? Obtain an expression for NML and NMH from transfer 10
characteristics of inverter.
UNIT 4
5 a With neat diagram explain the operation of clocked SR latch. 10
b Explain the concept of time borrowing in latch-based system. 10
OR
6 a Describe the behavior of bistable element with neat illustration. 10
b With neat diagram explain the operation of NOR based SR latch. 10
UNIT 5
7 a Implement a 4 word by 6-bit NAND ROM using pseudo-nMOS pull ups with the 10
following
Contents:
Word 0: 010101
Word 1: 011001
Word 2: 100101
Word 3: 101010

b Mention the disadvantage and advantage of NAND ROM (any one). Explain the 10
Functioning of the column circuitry in a DRAM with a neat diagram.
*******
 U.S.N.

B.M.S. College of Engineering, Bengaluru-560019

Autonomous Institute Affiliated to VTU

July / August 2019 Supplementary Examinations

Programme: B.E. Semester : V
Branch : ELECTRONICS AND COMMUNICATION ENGG Duration: 3 hrs.
Course Code: 16EC5DCFOV Max Marks: 100
Course: Fundamentals of VLSI Date: 29.07.2019

Instructions: 1. Answer any FIVE full questions, choosing one full question from each unit.
2. Missing data, if any may suitably assumed.

UNIT - I
Revealing of identification, appeal to evaluator will be treated as
Important Note: Completing your answers, compulsorily draw diagonal cross lines on the remaining

1 a) Discuss the VLSI design flow starting from Design specification to 8

fabrication with a neat flow chart .
b) Explain the following nonideal I-V effects . 8
(i) Body Effect
(ii) Junction Leakage
c) Find the subthreshold leakage current of an inverter at room temperature if 4
the input A = 0. Let βn = 2βp = 1 mA/V2, n = 1.0, and |Vt| = 0.4 V.
Assume the body effect and DIBL coefficients are γ = ɳ = 0.

UNIT - II
2 a) Discuss in detail, the λ based design rules with neat illustrations. 6
b) Draw the Layout/Stick diagram for the following: 8
i) 3- input NAND ii) Y= ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
((𝐴 + 𝐵 + 𝐶). 𝐷)
c) Illustrate the process of photolithography with neat diagram 6

UNIT - III
3 a) What is the effect of beta ratio on the DC characteristics of a CMOS 8
inverter?
b) “nFETs pass strong logic 0 and pFETs pass weak logic 0 levels” Justify 6
your answer with diagrams and equations.
c) Suppose VDD = 1.2 V and Vt = 0.4 V. Determine Vout in figure for the 6
following. Neglect the body effect.

i) Vin = 0 V ii) Vin = 0.6 V iii) Vin = 0.9 V iv) Vin = 1.2 V.

OR
blank pages.
malpractice.

4 a) Design a CMOS logic gate for the following 8

i) F = ̅̅̅̅̅̅̅̅̅̅̅̅̅̅
(AB + C) D (ii) F = ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
AB + C(A + B)
b) Explain the working of a transmission gate? Implement a MUX using 6
 transmission gate .
c) Discuss the working of a CMOS tristate inverter with diagrams 6

UNIT - IV
5 a) Analyze the bistable behaviour of a cross coupled inverter circuit 10
b) With a neat circuit , explain the operation of a CMOS implementation of a 10
clocked NAND- based SR latch .

OR
6 a) Suppose one cycle of logic is particularly critical and the next cycle is 8
nearly empty. Determine the maximum amount of time the first cycle can
borrow into the second for each of the following sequencing styles.
Assume there is zero clock skew and that the cycle time is 500 ps.

i) Flip-flops
ii) Two-phase transparent latches with 50% duty cycle clocks
iii) Two-phase transparent latches with 60ps of nonoverlap between
phases
iv) Pulsed latches with 80 ps pulse width
b) Explain the Max-Delay constraints with a Pulsed Latch. 6
c) Explain time borrowing with an example. 6

UNIT - V
7 a) Explain a Memory array architecture with neat diagram. 8
b) Draw the circuit for a 6 transistor SRAM cell and explain its working. 8
c) Explain the tradeoffs between open, folded and twisted bitlines in a 4
dynamic RAM arrays.