LTM4638

20VIN, 15A Step-Down DC/DC

µModule Regulator
FEATURES DESCRIPTION
n Complete Solution in <1cm2 (Single-Sided PCB) or The LTM®4638 is a complete 15A step-down switch-
0.5cm2 (Dual-Sided PCB) ing mode µModule (power module) regulator in a tiny
n 6.25mm × 6.25mm × 5.02mm BGA Package 6.25mm × 6.25mm × 5.02mm BGA package. Included
n Wide Input Voltage Range: 3.1V to 20V in the package are the switching controller, power FETs,
n 0.6V to 5.5V Output Voltage inductor and support components. Operating over an
n 15A DC Output Current input voltage range of 3.1V to 20V, the LTM4638 sup-
n ±1.5% Maximum Total DC Output Voltage Error ports an output voltage range of 0.6V to 5.5V, set by a
Over Line, Load and Temperature single external resistor. Its high efficiency design delivers
n Differential Remote Sensing Amp up to 15A continuous output current. Only bulk input and
n Current Mode Control, Fast Transient Response output capacitors are needed. The LTM4638 product video
n External Frequency Synchronization is available on the website.
n Multiphase Parallel Current Sharing with
The LTM4638 supports selectable discontinuous mode
Multiple LTM4638s
operation and output voltage tracking for supply rail se-
n Output Voltage Tracking quencing. Its high switching frequency and current mode
n Selectable Discontinuous Mode
control enable a very fast transient response to line and
n Power Good Indicator
load changes without sacrificing stability.
n Overvoltage, Overcurrent and Overtemperature
Protection Fault protection features include overvoltage, overcurrent
and overtemperature protection.
APPLICATIONS The LTM4638 is available with SnPb or RoHS compliant
n Telecom, Datacom, Networking and terminal finish.
Industrial Equipment All registered trademarks and trademarks are the property of their respective owners.

n Medical Diagnostic Equipment Click to view associated Video Design Idea.

n Data Storage Rack Units and Cards
n Test and Debug Systems

TYPICAL APPLICATION 1.0V Output Efficiency vs Load Current

15A, 1.0V Output DC/DC µModule Step-Down Regulator
® 95

90
PHMODE CLKOUT
VOUT
VIN
EFFICIENCY (%)

VIN VOUT 1.0V

3.1V TO 20V 22µF 85
100µF 15A
25V RUN VOSNS+
LTM4638 6.3V
INTVCC PGOOD x2
80
MODE/CLKIN COMPa
TRACK/SS COMPb
0.1µF FREQ FB 75
VIN = 5V, 600kHz
GND VOSNS– 90.9k
VIN = 12V, 600kHz
4638 TA01a
70
0 3 6 9 12 15
LOAD CURRENT (A)
4638 TA01b

Rev. C

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LTM4638
ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION
(Note 1) (See Pin Functions, Pin Configuration Table)
VIN.............................................................. –0.3V to 22V
TOP VIEW
VOUT.............................................................. –0.3V to 6V SW
TSENSE–
INTVCC....................................................... –0.3V to 3.6V 7
RUN............................................................. –0.3V to VIN TSENSE+
6
GND

PGOOD, FREQ, COMPa, COMPb, PGOOD

VOUT
PHMODE, CLKOUT, FB............................... –0.3V to 3.6V RUN
5 PHMODE

MODE/CLKIN, TRACK/SS...................... –0.3V to INTVCC 4 VIN

VOSNS+.......................................................... –0.3V to 6V
INTVCC
3 VOUT

VOSNS –....................................................... –0.3V to 0.3V VOSNS–

2
MODE/CLKIN
TRACK/SS

Internal Operating Temperature Range VOSNS+ CLKOUT

1
(Notes 2, 5)............................................. –40°C to 125°C FB COMPb
Storage Temperature Range................... –55°C to 125°C COMPa
A B C D E F G
FREQ

Peak Solder Reflow Body Temperature.................. 250°C BGA PACKAGE

49-LEAD (6.25mm × 6.25mm × 5.02mm)

TJMAX = 125°C, θJCtop = 10°C/W, θJCbottom = 4.2°C/W, θJA = 16°C/W

NOTE:
1) θ VALUES ARE DETERMINED BY SIMULATION PER JESD51 CONDITIONS, WEIGHT 660mg
2) θJA VALUE IS OBTAINED WITH DEMO BOARD
3) REFER TO PAGES 21, 22 FOR LAB MEASUREMENT AND DE-RATING INFORMATION

ORDER INFORMATION
PART MARKING* PACKAGE MSL TEMPERATURE RANGE
PART NUMBER PAD OR BALL FINISH DEVICE FINISH CODE TYPE RATING (NOTE 2)
LTM4638EY#PBF SAC305 (RoHS) 4638 e1 BGA 3 –40°C to 125°C
LTM4638IY#PBF SAC305 (RoHS) 4638 e1 BGA 3 –40°C to 125°C
LTM4638IY SnPb 4638 e0 BGA 3 –40°C to 125°C
• Contact the factory for parts specified with wider operating temperature • Recommended LGA and BGA PCB Assembly and
ranges. *Pad or ball finish code is per IPC/JEDEC J-STD-609. Manufacturing Procedures
• LGA and BGA Package and Tray Drawings

Rev. C

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 LTM4638
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified internal
operating temperature range (Note 2), otherwise specifications are at TA = 25°C. VIN = 12V per the typical application shown on the
front page.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Switching Regulator Section: per Channel
VIN Input DC Voltage l 3.1 20 V
VOUT Output Voltage Range l 0.6 5.5 V
VOUT(DC) Output Voltage, Total CIN = 22µF, COUT = 100µF Ceramic, RFB = 40.2k,
Variation with Line and Load MODE = INTVCC, IOUT = 0A to 15A (Note 3)
(Note 6) –40°C to 125°C l 1.477 1.50 1.523 V
VRUN RUN Pin On Threshold VRUN Rising 1.1 1.25 1.35 V
IQ(VIN) Input Supply Bias Current VIN = 12V, VOUT = 1.5V, MODE = INTVCC 100 mA
VIN = 12V, VOUT = 1.5V, MODE = GND 18 mA
Shutdown, RUN = 0, VIN = 12V 20 µA
IS(VIN) Input Supply Current VIN = 12V, VOUT = 1.5V, IOUT = 15A 2.3 A
IOUT(DC) Output Continuous Current VIN = 12V, VOUT = 1.5V 0 15 A
Range
ΔVOUT (Line)/VOUT Line Regulation Accuracy VOUT = 1.5V, VIN = 3.1V to 20V, IOUT = 0A l 0.04 0.15 %/V
ΔVOUT (Load)/VOUT Load Regulation Accuracy VOUT = 1.5V, IOUT = 0A to 15A l 0.5 1.2 %
VOUT(AC) Output Ripple Voltage IOUT = 0A, COUT = 100µF Ceramic, VIN = 12V, 5 mV
VOUT = 1.5V
ΔVOUT(START) Turn-On Overshoot IOUT = 0A, COUT = 100µF Ceramic, VIN = 12V, 30 mV
VOUT = 1.5V
tSTART Turn-On Time COUT = 100µF Ceramic, No Load, TRACK/SS = 0.01µF, 2.5 ms
VIN = 12V, VOUT = 1.5V
ΔVOUTLS Peak Deviation for Dynamic Load: 0% to 50% to 0% of Full Load, COUT = 47µF 160 mV
Load Ceramic, VIN = 12V, VOUT = 1.5V
tSETTLE Settling Time for Dynamic Load: 0% to 50% to 0% of Full Load, COUT = 47µF 40 µs
Load Step Ceramic, VIN = 12V, VOUT = 1.5V
IOUTPK Output Current Limit VIN = 12V, VOUT = 1.5V 18 A
VFB Voltage at FB Pin IOUT = 0A, VOUT = 1.5V l 0.594 0.60 0.606 V
IFB Current at FB Pin (Note 4) ±30 nA
RFBHI Resistor Between VOUT and 60.05 60.40 60.75 kΩ
FB Pins
ITRACK/SS Track Pin Soft-Start Pull-Up TRACK/SS = 0V 6 10 µA
Current
VIN(UVLO) VIN Undervoltage Lockout VIN Falling 2.5 2.6 2.7 V
VIN Hysteresis 250 mV
tON(MIN) Minimum On-Time (Note 4) 25 ns
tOFF(MIN) Minimum Off-Time (Note 4) 50 ns
VPGOOD PGOOD Trip Level VFB With Respect to Set Output
VFB Ramping Negative –12 –8 –5 %
VFB Ramping Positive 5 8 12 %
IPGOOD PGOOD Leakage 2 µA
VPGL PGOOD Voltage Low IPGOOD = 1mA 0.02 0.1 V

Rev. C

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LTM4638
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified internal
operating temperature range (Note 2), otherwise specifications are at TA = 25°C. VIN = 12V per the typical application shown on the
front page.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VINTVCC Internal VCC Voltage VIN = 4V to 20V 3.2 3.3 3.4 V
fOSC Oscillator Frequency 600 kHz
Note 1: Stresses beyond those listed under Absolute Maximum Ratings maximum ambient temperature consistent with these specifications is
may cause permanent damage to the device. Exposure to any Absolute determined by specific operating conditions in conjunction with board
Maximum Rating condition for extended periods may affect device layout, the rated package thermal resistance and other environmental
reliability and lifetime. factors.
Note 2: The LTM4638 is tested under pulsed load conditions such that Note 3: See output current derating curves for different VIN, VOUT and TA.
TJ ≈ TA. The LTM4638E is guaranteed to meet performance specifications Note 4: 100% tested at wafer level.
over the 0°C to 125°C internal operating temperature range. Specifications Note 5: This IC includes overtemperature protection that is intended
over the –40°C to 125°C internal operating temperature range are assured to protect the device during momentary overload conditions. Junction
by design, characterization and correlation with statistical process temperature will exceed 125°C when overtemperature protection is active.
controls. The LTM4638I is guaranteed to meet specifications over the Continuous operation above the specified maximum operating junction
full –40°C to 125°C internal operating temperature range. Note that the temperature may impair device reliability.

Rev. C

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 LTM4638
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency vs Load Current Efficiency vs Load Current Efficiency vs Load Current
from 3.3VIN from 5VIN from 12VIN
100 100 100

95 95 95

90 90 90
EFFICIENCY (%)

EFFICIENCY (%)

EFFICIENCY (%)
85 85 85
1.0VOUT, 600kHz
1.0VOUT, 600kHz 1.2VOUT, 600kHz
80 1.0VOUT, 500kHz 80 80 1.5VOUT, 800kHz
1.2VOUT, 600kHz
1.2VOUT, 500kHz 1.5VOUT, 600kHz 1.8VOUT, 800kHz
75 1.5VOUT, 500kHz 75 1.8VOUT, 800kHz 75 2.5VOUT, 1000kHz
1.8VOUT, 500kHz 2.5VOUT, 800kHz 3.3VOUT, 1000kHz
2.5VOUT, 500kHz 3.3VOUT, 800kHz 5.0VOUT, 1500kHz
70 70 70
0 5 10 15 0 5 10 15 0 5 10 15
LOAD CURRENT (A) LOAD CURRENT (A) LOAD CURRENT (A)
4638 G01 4638 G02 4638 G03

1V Output Transient Response 1.5V Output Transient Response 2.5V Output Transient Response

OUTPUT OUTPUT OUTPUT

VOLTAGE VOLTAGE VOLTAGE
50mV/DIV 50mV/DIV 100mV/DIV
AC COUPLED AC COUPLED AC COUPLED

LOAD STEP LOAD STEP LOAD STEP

CURRENT CURRENT CURRENT
2A/DIV 2A/DIV 2A/DIV

4638 G04 4638 G05 4638 G06

100µs/DIV 100µs/DIV 100µs/DIV
VIN=12V, VOUT=1.0V, fS=600kHz VIN=12V, VOUT=1.5V, fS=800kHz VIN=12V, VOUT=2.5V, fS=1000kHz
COUT = 3x 100µF + 1x 22µF CERAMIC CAPACITOR COUT = 3x 100µF + 1x 22µF CERAMIC CAPACITOR COUT = 3x 100µF + 1x 22µF CERAMIC CAPACITOR
INTERNAL COMPENSATION, COMPa CONNECT TO INTERNAL COMPENSATION, COMPb CONNECT TO INTERNAL COMPENSATION, COMPa CONNECT TO
COMPb, CFF=33pF COMPb, CFF=33pF COMPb, CFF=33pF

Start-up Waveform Without

3.3V Output Transient Response 5V Output Transient Response Load Current

RUN
OUTPUT OUTPUT 5V/DIV
VOLTAGE VOLTAGE PGOOD
100mV/DIV 200mV/DIV 5V/DIV
AC COUPLED AC COUPLED
VOUT
1V/DIV
LOAD STEP LOAD STEP
CURRENT CURRENT
2A/DIV 2A/DIV IIN
0.5A/DIV

4638 G07 4638 G08 4638 G09

100µs/DIV 100µs/DIV 5ms/DIV
VIN=12V, VOUT=3.3V, fS=1000kHz VIN=12V, VOUT=5V, fS=1500kHz VIN=12V, VOUT=1V, fS=600kHz
COUT = 3x 100µF + 1x 22µF CERAMIC CAPACITOR COUT = 3x 100µF + 1x 22µF CERAMIC CAPACITOR COUT = 3x 100µF + 1x 22µF CERAMIC CAPACITOR
INTERNAL COMPENSATION, COMPa CONNECT TO INTERNAL COMPENSATION, COMPa CONNECT TO INTERNAL COMPENSATION, COMPa CONNECT TO
COMPb, CFF=33pF COMPb, CFF=33pF COMPb, CFF=33pF, CSS=0.1µF

Rev. C

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LTM4638
TYPICAL PERFORMANCE CHARACTERISTICS
Start-up Waveform with 15A Load Output Short Circuit Waveform Output Short Circuit Waveform
Current without Load Applied with 15A Load Current Applied

RUN
5V/DIV
IIN IIN
PGOOD
1A/DIV 1A/DIV
5V/DIV

VOUT
1V/DIV

VOUT VOUT
IIN 1V/DIV
2A/DIV 1V/DIV

4638 G10 4638 G11 4638 G12

5ms/DIV 50µs/DIV 50µs/DIV
VIN=12V, VOUT=1V, fS=600kHz VIN=12V, VOUT=1.5V, fS=800kHz VIN=12V, VOUT=1.5V, fS=800kHz
COUT = 3x 100µF + 1x 22µF CERAMIC CAPACITOR COUT = 3x 100µF + 1x 22µF CERAMIC CAPACITOR COUT = 3x 100µF + 1x 22µF CERAMIC CAPACITOR
INTERNAL COMPENSATION, COMPa CONNECT TO INTERNAL COMPENSATION, COMPa CONNECT TO INTERNAL COMPENSATION, COMPa CONNECT TO
COMPb, CFF=33pF, CSS=0.1µF COMPb, CFF=33pF COMPb, CFF=33pF

Steady-State Output Voltage

Start-up into Pre-Biased Output Ripple

RUN
5V/DIV
PGOOD
OUTPUT
5V/DIV
VOLTAGE
VOUT 10mV/DIV
2V/DIV AC COUPLED

IIN
0.5A/DIV

4638 G13 4638 G14

5ms/DIV 500ns/DIV
VIN=12V, VOUT=3.3V, fS=800kHz VIN=12V, VOUT=1.5V, fS=800kHz
COUT = 3x 100µF + 1x 22µF CERAMIC CAPACITOR COUT = 3x 100µF + 1x 22µF CERAMIC CAPACITOR
INTERNAL COMPENSATION, COMPa CONNECT TO INTERNAL COMPENSATION, COMPa CONNECT TO
COMPb, CFF=33pF, PREBIASED OUTPUT TO 1.2V, COMPb, CFF=33pF
CSS=0.1µF

Rev. C

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 LTM4638
PIN FUNCTIONS
PACKAGE ROW AND COLUMN LABELING MAY VARY TRACK/SS (E2): Output Tracking and Soft-Start Pin of the
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE Switching Mode Regulator. Allows the user to control the
LAYOUT CAREFULLY.
rise time of the output voltage. Putting a voltage below
VOUT (A1-A5, F3, G1-G3): Power Output Pins of the 0.6V on this pin bypasses the internal reference input to the
Switching Mode Regulator. Apply output load between error amplifier, instead it servos the FB pin to the TRACK
these pins and GND pins. Recommend placing output voltage. Above 0.6V, the tracking function stops and the
decoupling capacitance directly between these pins and internal reference resumes control of the error amplifier.
GND pins. See the Applications Information section for There’s an internal 6µA pull-up current from INTVCC on this
paralleling outputs. pin, so putting a capacitor here provides soft-start func-
tion. See the Applications Information section for details.
COMPb (F1): Internal Loop Compensation Network.
Connect to COMPa to use the internal compensation in MODE/CLKIN (D2): Discontinuous Mode Select Pin and
majority of applications. External Synchronization Input to Phase Detector. Tie
MODE/CLKIN to GND for discontinuous mode of operation.
FREQ (E1): Switching Frequency Program Pin. Frequency is
Floating MODE/CLKIN or tying it to a voltage above 1V will
set internally to 600kHz. An external resistor can be placed
select forced continuous mode. Furthermore, connecting
from this pin to GND to increase frequency, or from this
MODE/CLKIN to an external clock will synchronize the
pin to INTVCC to reduce frequency. See the Applications
Information section for frequency adjustment. system clock to the external clock and puts the part in
forced continuous mode. See Applications Information
COMPa (D1): Current control threshold and error ampli- section for details.
fier compensation point of the switching mode regulator
channel. The internal current comparator threshold is VOSNS– (C2): Negative Input to the Differential Remote
Sense Amplifier. Connect an external resistor between FB
linearly proportional to this voltage. Tie the COMPa pins
and VOSNS– pin to set the output voltage of the specific
from different channels together for parallel operation.
channel. See the Applications Information section for
The device is internal compensated. Connect to COMPb
details.
to use the internal compensation. Or connect to a Type-II
C-R-C network to use customized compensation. CLKOUT (F2): Output Clock Signal for PolyPhase Op-
eration. The phase of CLKOUT with respect to CLKIN is
FB (C1): The Negative Input of the Error Amplifier for the
determined by the state of the respective PHMODE pin.
switching mode regulator. This pin is internally connected
CLKOUT’s peak-to-peak amplitude is INTVCC to GND. See
to VOSNS+ with a 60.4kΩ precision resistor. Output voltages
Application Information section for details.
can be programmed with an additional resistor between
FB and VOSNS– pins. In PolyPhase® operation, tying the VIN (D3-D4, E3-E4, F4, G4): Power input pins connect to
FB pins together allows for parallel operation. See the the drain of the internal top MOSFET and signal VIN to the
Applications Information section for details. internal 3.3V regulator for the control circuitry for each
switching mode regulator channel. Apply input voltages
VOSNS+ (B1): Positive Input to the Differential Remote
Sense Amplifier. Internally, this pin is connected to FB between these pins and GND pins. Recommend placing
with a 60.4k 0.5% precision resistor. See the Applications input decoupling capacitance directly between each of VIN
pins and GND pins.
Information section for details.
INTVCC (B3): Internal 3.3V Regulator Output of the Switch-
PHMODE (G5): Control Input to the Phase Selector of the
ing Mode Regulator Channel. The internal power drivers
Switching Mode Regulator. Determines the phase rela-
tionship between internal oscillator and CLKOUT. Tie it to and control circuits are powered from this voltage. The
INTVCC for 2-phase operation, tie it to SGND for 3-phase LTM4638 has an internal 2.2µF decoupling capacitor. No
operation, and tie it to INTVCC /2 for 4-phase operation. external decoupling capacitor is required.
See Application Information section for details.
Rev. C

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LTM4638
PIN FUNCTIONS
RUN (B4): Run Control Input Pin. Enable regulator opera- PGOOD (B5): Output Power Good Pin with Open-Drain
tion by tying the specific RUN pin above 1.25V. Tying it Logic. PGOOD is pulled to ground when the voltage on
below 1.1V shuts down the specific regulator channel. the FB pin is not within ±8% of the internal 0.6V reference.
TSENSE+ (A6): Temperature Monitor Pin. An internal diode TSENSE– (A7): Low Side of the Internal Temperature Monitor.
connected NPN transistor is placed between TSENSE+ and SW (B7): Switching node of each channel that is used
TSENSE– pins. See the Applications Information section.
for testing purposes. Also an R-C snubber network can
GND (B2, B6, C3-C7, D5-D7, E5-E7, F5-F7, G6-G7): be applied to reduce or eliminate switch node ringing, or
Power Ground Pins for Both Input and Output Returns. otherwise leave floating. See the Applications Information
Use large PCB copper areas to connect all GND together. section.

Rev. C

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 LTM4638
BLOCK DIAGRAM

PGOOD 10k
INTVCC

INTVCC
VIN VIN
2.2µF
CIN 3.1V TO 20V
0.1µF
MODE/CLKIN 22µF
25V

0.24µH VOUT VOUT

1.5V
CLKOUT COUT 15A
1µF 100µF
PHMODE POWER CONTROL ×3
GND 6.3V

TRACK/SS
VOSNS–
0.1µF –
DIFF RFB
RUN AMP 40.2k
VIN + FB

COMPa 60.4k
VOSNS+
COMPb

INTERNAL TSENSE+
INTERNAL FILTER
COMP

274k TSENSE–

FREQ GND
4638 BD

Figure 1. Simplified LTM4638 Block Diagram

DECOUPLING REQUIREMENTS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
CIN External Input Capacitor Requirement IOUT = 15A 22 44 µF
(VIN = 3.1V to 20V, VOUT = 1.5V)
COUT External Output Capacitor Requirement IOUT = 15A 220* 470* µF
(VIN = 3.1V to 20V, VOUT = 1.5V)
*Additional capacitance may be required under extreme temperature and/or capacitor bias voltage conditions due to variation of actual capacitance over bias voltage and temperature.

Rev. C

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LTM4638
OPERATION
The LTM4638 is a standalone nonisolated switch mode Furthermore, in order to protect the internal power MOSFET
DC/DC power supply. It can deliver up to 15A DC output devices against transient voltage spikes, the LTM4638
current with few external input and output capacitors. constantly monitors the VIN pin for an overvoltage condi-
This module provides precisely regulated output voltage tion. When VIN rises above 24.5V, the regulator suspends
adjustable between 0.6V to 5.5V via one external resistor operation by shutting off both power MOSFETs. Once VIN
over a 3.1V to 20V input voltage range. The typical ap- drops below 21.5V, the regulator immediately resumes
plication schematic is shown in Figure 23. normal operation. The regulator does not execute its
The LTM4638 contains an integrated constant on-time soft-start function when exiting an overvoltage condition.
valley current mode regulator, power MOSFETs, inductor, Multiphase operation can be easily employed with the
and other supporting discrete components. The default synchronization and phase mode controls. Up to 6 phases
switching frequency is 600kHz. For switching noise- can be cascaded to run simultaneously with respect to
sensitive applications, the switching frequency can be each other by programming the PHMODE pin to different
adjusted by external resistors and the μModule regulator levels. The LTM4638 has MODE/CLKIN and CLKOUT pins
can be externally synchronized to a clock within ±30% of for PolyPhase operation of multiple devices or frequency
the set frequency. See the Applications Information section. synchronization.
With current mode control and internal feedback loop Pulling the RUN pin to GND forces the controller into its
compensation, the LTM4638 module has sufficient stabil- shutdown state, turning off both power MOSFETs and
ity margins and good transient performance with a wide most of the internal control circuitry. At light load currents,
range of output capacitors, even with all ceramic output discontinuous mode (DCM) operation can be enabled to
capacitors. achieve higher efficiency compared to continuous mode
Current mode control provides cycle-by-cycle fast current (CCM) by pulling the MODE/CLKIN pin to GND. The
TRACK/SS pin is used for power supply tracking and
limiting. Internal output overvoltage and undervoltage
soft-start programming. See the Applications Informa-
comparators pull the open-drain PGOOD output low if the
tion section.
output feedback voltage exits a ±8% window around the
regulation point. Continuous operation is forced during OV
and UV condition except during start-up when the TRACK
pin is ramping up to 0.6V.

Rev. C

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 LTM4638
APPLICATIONS INFORMATION
The typical LTM4638 application circuit is shown in in Figure 2, thus tying one of the internal 60.4k resistors
Figure 23. External component selection is primarily to the output. All of the VFB pins tie together with one
determined by the input voltage, the output voltage and programming resistor as shown in Figure 2.
the maximum load current. Refer to Table 7 for specific See Figure 25 for an example of parallel operation.
external capacitor requirements for a particular application.
COMPa VOUT 1.2V/30A
VIN to VOUT Step-Down Ratios
COMPb LTM4638
There are restrictions in the maximum VIN and VOUT step- VOSNS+
down ratios that can be achieved for a given input voltage VFB
due to the minimum off-time and minimum on-time limits
TRACK/SS
of the regulator. The minimum off-time limit imposes a VOSNS–
maximum duty cycle which can be calculated as:
DMAX = 1 – (tOFF(MIN) • fSW) COMPa VOUT
LTM4638
COMPb VOSNS+
where tOFF(MIN) is the minimum off-time, typically 50ns
for LTM4638, and fSW (Hz) is the switching frequency. VFB
Conversely the minimum on-time limit imposes a minimum RFB
duty cycle of the converter which can be calculated as: TRACK/SS
VOSNS–
60.4k
0.1µF
DMIN = tON(MIN) • fSW 4638 F02

where tON(MIN) is the minimum on-time, typically 25ns Figure 2. 2-Phase Parallel Configurations
for LTM4638. In the rare cases where the minimum duty
cycle is surpassed, the output voltage will still remain Input Decoupling Capacitors
in regulation, but the switching frequency will decrease The LTM4638 module should be connected to a low AC
from its programmed value. Note that additional thermal impedance DC source. For the regulator, a 22µF input
derating may be applied. See the Thermal Considerations ceramic capacitor is required for RMS ripple current de-
and Output Current Derating section in this data sheet. coupling. Bulk input capacitance is only needed when the
input source impedance is compromised by long inductive
Output Voltage Programming leads, traces or not enough source capacitance. The bulk
The PWM controller has an internal 0.6V reference voltage. capacitor can be an aluminum electrolytic capacitor or
As shown in the Block Diagram, a 60.4k internal feedback polymer capacitor.
resistor connects the VOUT and FB pins together. Adding a Without considering the inductor ripple current, the RMS
resistor, RFB, from FB pin to VOSNS– programs the output current of the input capacitor can be estimated as:
voltage:
IOUT(MAX)
0.6V ICIN(RMS) = • D• (1–D)
R FB = • 60.4k η%
VOUT – 0.6V
where η% is the estimated efficiency of the power module.
Table 1. RFB Resistor Table vs Various Output Voltages
VOUT (V) 0.6 1.0 1.2 1.5 1.8 2.5 3.3 5.0 Output Decoupling Capacitors
RFB (kΩ) OPEN 90.9 60.4 40.2 30.1 19.1 13.3 8.25
With an optimized high frequency, high bandwidth de-
For parallel operation of multiple channels the same feed- sign, only a single low ESR output ceramic capacitor is
back setting resistor can be used for the parallel design. required for the LTM4638 to achieve low output ripple
This is done by connecting the VOSNS+ to the output shown voltage and very good transient response. In extreme
Rev. C

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LTM4638
APPLICATIONS INFORMATION
cold or hot temperature or high output voltage case, ad- by adding a resistor, RFSET, between the FREQ pin and
ditional ceramic capacitor or tantalum-polymer capacitor SGND, as shown in Figure 24. The operating frequency
is required due to variation of actual capacitance over bias can be calculated as:
voltage and temperature. Table 7 shows a matrix of dif-
1.67e11
ferent output voltages and output capacitors to minimize f (Hz ) =
the voltage droop and overshoot during a 4A load-step 274k ||R FSET ( Ω )
transient. Additional output filtering may be required by
The programmable operating frequency range is from
the system designer if further reduction of output ripple or
400kHz to 3MHz.
dynamic transient spikes is required. The Linear Technology
LTpowerCAD™ design tool is available to download online Frequency Synchronization and Clock In
for output ripple, stability and transient response analysis
for further optimization. The power module has a phase-locked loop comprised
of an internal voltage controlled oscillator and a phase
Discontinuous Current Mode (DCM) detector. This allows the internal top MOSFET turn-on to be
locked to the rising edge of the external clock. The external
In applications where low output ripple and high efficiency
clock frequency range must be within ±30% around the
at intermediate current are desired, discontinuous current
resistor set operating frequency. A pulse detection circuit
mode (DCM) should be used by connecting the MODE/
is used to detect a clock on the CLKIN pin to turn on the
CLKIN pin to GND. At light loads the internal current com-
phase-locked loop. The pulse width of the clock has to
parator may remain tripped for several cycles and force the
be at least 100ns. The clock high level must be above 1V
top MOSFET to stay off for several cycles, thus skipping
and clock low level below 0.3V. During the start-up of
cycles. The inductor current does not reverse in this mode.
the regulator, the phase-locked loop function is disabled.
Forced Continuous Current Mode (CCM)
Multiphase Operation
In applications where fixed frequency operation is more
For output loads that demand more than 15A of current,
critical than low current efficiency, and where the lowest
multiple LTM4638s can be paralleled to run out of phase
output ripple is desired, forced continuous operation should
to provide more output current without increasing input
be used. Forced continuous operation can be enabled by
and output voltage ripples.
tying the MODE/CLKIN pin to INTVCC. In this mode, induc-
tor current is allowed to reverse during low output loads, The CLKOUT signal can be connected to the MODE/CLKIN
the COMP voltage is in control of the current comparator pin of the following LTM4638 stage to line up both the
threshold throughout, and the top MOSFET always turns on frequency and the phase of the entire system. Tying the
with each oscillator pulse. During start-up, forced continuous PHMODE pin to INTVCC, GND or FLOAT generates a phase
mode is disabled and inductor current is prevented from difference (between CLKIN and CLKOUT) of 180°, 120°, or
reversing until the LTM4638’s output voltage is in regulation. 90° respectively, which corresponds to 2-phase, 3-phase
or 4-phase operation. A total of 6 phases can be cascaded
Operating Frequency to run simultaneously out of phase with respect to each
The operating frequency of the LTM4638 is optimized other by programming the PHMODE pin of each LTM4638
to achieve the compact package size and the minimum to different levels. Figure 3 shows a 4-phase design and
out-put ripple voltage while still keeping high efficiency. a 6-phase design example for clock phasing.
The default operating frequency is 600kHz. In most ap- Table 2. PHMODE Pin Status and Corresponding Phase
plications, no additional frequency adjustment is required. Relationship (Relative to CLKIN)
PHMODE INTVCC GND FLOAT
If an operating frequency other than 600kHz is required by
CLKOUT 180° 120° 90°
the application, the operating frequency can be increased
Rev. C

12 For more information www.analog.com

 LTM4638
APPLICATIONS INFORMATION
0 90 180 270
+90 +90 +90
CLKIN CLKOUT CLKIN CLKOUT CLKIN CLKOUT CLKIN CLKOUT

PHMODE PHMODE PHMODE PHMODE

PHASE 1 PHASE 2 PHASE 3 PHASE 4

(420)
0 120 240 60 180 300
+120 +120 +180 +120 +120
CLKIN CLKOUT CLKIN CLKOUT CLKIN CLKOUT CLKIN CLKOUT CLKIN CLKOUT CLKIN CLKOUT

PHMODE PHMODE INTVCC PHMODE PHMODE PHMODE INTVCC PHMODE

PHASE 1 PHASE 3 PHASE 5 PHASE 2 PHASE 4 PHASE 6 4638 F03

Figure 3. 4-Phase, 6-Phase Operation

0.60
1 PHASE
2 PHASE
0.55 3 PHASE
4 PHASE
0.50 6 PHASE

0.45

0.40
RMS INPUT RIPPLE CURRENT
DC LOAD CURRENT

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0
0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9
DUTY CYCLE (VOUT/VIN)
4638 F04

Figure 4. RMS Input Ripple Current to DC Load Current Ratio as a Function of Duty Cycle

A multiphase power supply significantly reduces the The LTM4638 device is an inherently current mode con-
amount of ripple current in both the input and output ca- trolled device, so parallel modules will have very good
pacitors. The RMS input ripple current is reduced by, and current sharing. This will balance the thermals on the
the effective ripple frequency is multiplied by, the number design. Please tie the RUN, TRACK/SS, FB and COMPa
of phases used (assuming that the input voltage is greater pins of each paralleling channel together. Figure 25 shows
than the number of phases used times the output voltage). an example of parallel operation and pin connection.
The output ripple amplitude is also reduced by the number
of phases used when all of the outputs are tied together
to achieve a single high output current design.
Rev. C

For more information www.analog.com 13

LTM4638
APPLICATIONS INFORMATION
Input RMS Ripple Current Cancellation 0.6V, it will take over the internal 0.6V reference voltage
to control the output voltage. The total soft-start time can
Application Note 77 provides a detailed explanation of
be calculated as:
multiphase operation. The input RMS ripple current can-
cellation mathematical derivations are presented, and a C
t SS = 0.6 • SS
graph is displayed representing the RMS ripple current 6µA
reduction as a function of the number of interleaved phases.
Figure 4 shows this graph. where CSS is the capacitance on the TRACK/SS pin. Cur-
rent foldback and forced continuous mode are disabled
Soft-Start And Output Voltage Tracking during the soft-start process.
The TRACK/SS pin provides a means to either soft start Output voltage tracking can also be programmed externally
the regulator or track it to a different power supply. A using the TRACK/SS pin. The output can be tracked up
capacitor on the TRACK/SS pin will program the ramp and down with another regulator. Figure 5 and Figure 6
rate of the output voltage. An internal 6µA current source show an example waveform and schematic of ratiometric
will charge up the external soft-start capacitor towards tracking where the slave regulator’s output slew rate is
INTVCC voltage. When the TRACK/SS voltage is below proportional to the master’s.

MASTER OUTPUT
OUTPUT VOLTAGE

SLAVE OUTPUT

TIME
4638 F05

Figure 5. Output Ratiometric Tracking Waveform

VIN
3.1V TO 20V

FREQ VOUT(MA) FREQ VOUT(SL)

VIN VOUT 1.5V VIN VOUT 1.2V
22µF 100µF 15A 22µF 100µF 15A
LTM4638 6.3V LTM4638 6.3V
25V 25V
RUN VOSNS+ ×2 RUN VOSNS+ ×2
INTVCC RTR(TOP) INTVCC
MODE FB 60.4k MODE FB
TRACK/SS COMPa TRACK/SS COMPa
RFB(MA) RFB(SL)
PGOOD COMPb RTR(BOT) PGOOD COMPb
40.2k 60.4k
40.2k
GND VOSNS– GND VOSNS–

4638 F06

Figure 6. Example Schematic of Ratiometric Output Voltage Tracking

Rev. C

14 For more information www.analog.com

 LTM4638
APPLICATIONS INFORMATION
Since the slave regulator’s TRACK/SS is connected to
the master’s output through a RTR(TOP)/RTR(BOT) resistor
divider and its voltage used to regulate the slave output MASTER OUTPUT

voltage when TRACK/SS voltage is below 0.6V, the slave

OUTPUT VOLTAGE
output voltage and the master output voltage should satisfy SLAVE OUTPUT
the following equation during start-up:
R FB(SL)
VOUT(SL) • =
R FB(SL) + 60.4k

R TR(BOT) TIME
VOUT(MA) • 4638 F07

R TR(TOP) +R TR(BOT)
Figure 7. Output Coincident Tracking Waveform
The RFB(SL) is the feedback resistor and the RTR(TOP)/
RTR(BOT) is the resistor divider on the TRACK/SS pin of From the equation, we could easily find that, in coincident
the slave regulator, as shown in Figure 6. tracking, the slave regulator’s TRACK/SS pin resistor divider
is always the same as its feedback divider:
Following the previous equation, the ratio of the master’s
output slew rate (MR) to the slave’s output slew rate (SR) R FB(SL) R TR(BOT)
=
is determined by: R FB(SL) + 60.4k R TR(TOP) +R TR(BOT)
R FB(SL)
For example, RTR(TOP) = 60.4k and RTR(BOT) = 60.4k is a
MR 60.4k +R FB(SL) good combination for coincident tracking for a VOUT(MA)
=
SR R TR(BOT) = 1.5V and VOUT(SL) = 1.2V application.
R TR(TOP) +R TR(BOT)
Power Good
For example, VOUT(MA)=1.5V, MR = 1.5V/1ms and VOUT(SL) The PGOOD pin is an open-drain pin that can be used to
= 1.2V, SR = 1.2V/1ms. From the equation, we could solve monitor valid output voltage regulation. This pin is pulled
that RTR(TOP) = 60.4k and RTR(BOT) = 40.2k are a good low when the output voltage exceeds a ±8% window
combination for the ratiometric tracking. around the regulation point. To prevent unwanted PGOOD
The TRACK/SS pin will have the 2µA current source on glitches during transients or dynamic VOUT changes, the
when a resistive divider is used to implement tracking LTM4638’s PGOOD falling edge includes a blanking delay
on the slave regulator. This will impose an offset on the of approximately 25 switching cycles.
TRACK/SS pin input. Smaller value resistors with the same
ratios as the resistor values calculated from the above RUN Enable
equation can be used. For example, where the 60.4k is Pulling the RUN pin to ground forces the LTM4638 into
used then a 6.04k can be used to reduce the TRACK/SS its shutdown state, turning off both power MOSFETs and
pin offset to a negligible value. most of its internal control circuitry. Bringing the RUN pin
above 0.6V turns on the internal reference only, while still
Coincident output tracking can be recognized as a special
keeping the power MOSFETs off. Increasing the RUN pin
ratiometric output tracking in which the master’s output
voltage above 1.25V will turn on the entire chip.
slew rate (MR) is the same as the slave’s output slew rate
(SR), waveform as shown in Figure 7.

Rev. C

For more information www.analog.com 15

LTM4638
APPLICATIONS INFORMATION
Pre-Biased Output Start-Up Stability Compensation
There may be situations that require the power supply to The LTM4638 has already been internally optimized and
start up with some charge on the output capacitors. The compensated for all output voltages and capacitor combi-
LTM4638 can safely power up into a pre-biased output nations including all ceramic capacitor applications when
without discharging it. COMPb is tied to COMPa. Please note that a 22pF to
The LTM4638 accomplishes this by forcing discontinuous 47pF feedforward capacitor (CFF) is required connecting
mode (DCM) operation until the TRACK/SS pin voltage from VOUT to VFB pin for all ceramic capacitor application
reaches 0.6V reference voltage. This will prevent the BG to achieve high bandwidth control loop compensation
from turning on during the pre-biased output start-up with enough phase margin. Table 7 is provided for most
which would discharge the output. application requirements using the optimized internal
compensation. For specific optimized requirement, dis-
SW Pins and Snubbering Circuit connect COMPb from COMPa and apply a Type II C-R-C
compensation network from COMPa to GND to achieve
The SW pin is generally for testing purposes by monitor- external compensation. The LTpowerCAD design tool is
ing the pin. The SW pin can also be used to dampen out available to download online to perform specific control
switch node ringing caused by LC parasitic in the switched loop optimization and analyze the control stability and load
current path. Usually a series R-C combination is used transient performance.
called a snubber circuit. The resistor will dampen the
resonance and the capacitor is chosen to only affect the Differential Remote Sense Amplifier
high frequency ringing across the resistor.
An accurate differential remote sense amplifier is build into
If the stray inductance or capacitance can be measured or the LTM4638 to sense output voltages accurately at the
approximated then a somewhat analytical technique can remote load points. This is especially true for high current
be used to select the snubber values. The inductance is loads. It is very important that the VOSNS+ and VOSNS– are
usually easier to predict. It combines the power path board connected properly at the remote output sense point, and
inductance in combination with the MOSFET interconnect the feedback resistor RFB is connected to between VFB
bond wire inductance. pin to VOSNS– pin. Review the schematics in Figure 23
First the SW pin can be monitored with a wide bandwidth for reference.
scope with a high frequency scope probe. The ring fre- In multiphase single output application. Only one set of
quency can be measured for its value. The impedance Z differential sensing amplifier and one set of feedback
can be calculated: resistor are required while connecting RUN, TRACK/SS,
ZL = 2π • f • L VOUT, VFB and COMPa of different channels together. See
Figure 25 for paralleling application.
where f is the resonant frequency of the ring, and L is the
total parasitic inductance in the switch path. If a resistor Input Overvoltage Protection
is selected that is equal to Z, then the ringing should be
dampened. The snubber capacitor value is chosen so that In order to protect the internal power MOSFET devices
its impedance is equal to the resistor at the ring frequency. against transient voltage spikes, the LTM4638 constantly
Calculated by: monitors each VIN pin for an overvoltage condition. When
VIN rises above 24.5V, the regulator suspends operation
1 by shutting off both power MOSFETs on the correspond-
ZC =
2π • f •C ing channel. Once VIN drops below 21.5V, the regulator
immediately resumes normal operation. The regulator
These values are a good place to start. Modification to
executes its soft-start function when exiting an overvolt-
these components should be made to attenuate the ring-
age condition.
ing with the least amount the power loss.
Rev. C

16 For more information www.analog.com

 LTM4638
APPLICATIONS INFORMATION
Temperature Monitoring where VD appears to increase with temperature. It is com-
mon knowledge that a silicon diode biased with a current
Measuring the absolute temperature of a diode is possible
source has an approximate –2mV/°C temperature rela-
due to the relationship between current, voltage and tem-
tionship (Figure 8), which is at odds with the equation. In
perature described by the classic diode equation:
fact, the IS term increases with temperature, reducing the
⎛ V ⎞ ln(ID/IS) absolute value yielding an approximate –2mV/°C
ID =IS • e ⎜ D ⎟ composite diode voltage slope.
⎝ η• VT ⎠
0.8
or
0.7
I
VD = η• VT •In D

DIODE VOLTAGE (V)

IS 0.6

where ID is the diode current, VD is the diode voltage, η 0.5

is the ideality factor (typically close to 1.0) and IS (satura-
tion current) is a process dependent parameter. VT can be 0.4

broken out to:

0.3
k•T –50 –25 0 25 50 75 100 125
VT = TEMPERATURE (°C) 4638 F08
q
Figure 8. Diode Voltage VD vs Temperature T(°C)
where T is the diode junction temperature in Kelvin, q is
the electron charge and k is Boltzmann’s constant. VT is To obtain a linear voltage proportional to temperature
approximately 26mV at room temperature (298K) and we cancel the IS variable in the natural logarithm term to
scales linearly with Kelvin temperature. It is this linear remove the IS dependency from the equation 1. This is
temperature relationship that makes diodes suitable tem- accomplished by measuring the diode voltage at two cur-
perature sensors. The IS term in the previous equation is rents I1, and I2, where I1 = 10 • I2) and subtracting we get:
the extrapolated current through a diode junction when
I I
the diode has zero volts across the terminals. The IS term ΔVD = T(KELVIN)•KD •IN 1 − T(KELVIN)•KD •IN 2
varies from process to process, varies with temperature, IS IS
and by definition must always be less than ID. Combining
Combining like terms, then simplifying the natural log
all of the constants into one term:
terms yields:
η•k
KD = ∆VD = T(KELVIN) • KD • lN(10)
q
and redefining constant
where KD = 8.62−5, and knowing ln(ID/IS) is always posi- 198µV
tive because ID is always greater than IS, leaves us with K'D = K D •IN(10) =
the equation that: K

I yields
VD = T (KELVIN ) • K D •In D
IS ∆VD = K’D • T(KELVIN)

Rev. C

For more information www.analog.com 17

LTM4638

Solving for temperature:

ΔVD
T(KELVIN) = (�CELSIUS) = T(KELVIN) – 273.15
K'D

where
300°K = 27°C
means that is we take the difference in voltage across the
diode measured at two currents with a ratio of 10, the
resulting voltage is 198μV per Kelvin of the junction with
a zero intercept at 0 Kelvin.
The diode connected NPN transistor at the TEMP pin can be
used to monitor the internal temperature of the LTM4638. Figure 9. Thermal Image at 12V Input, 1.0V Output Without Air
Flow and Heat Sinking

Rev. C

18 For more information www.analog.com

 LTM4638
APPLICATIONS INFORMATION
Thermal Considerations and Output Current Derating 1. θJA, the thermal resistance from junction to ambient, is
the natural convection junction-to-ambient air thermal
The thermal resistances reported in the Pin Configuration
resistance measured in a one cubic foot sealed enclo-
section of the data sheet are consistent with those param-
sure. This environment is sometimes referred to as
eters defined by JESD 51-12 and are intended for use with
“still air” although natural convection causes the air to
finite element analysis (FEA) software modeling tools that
move. This value is determined with the part mounted
leverage the outcome of thermal modeling, simulation,
to a 95mm × 76mm PCB with four layers.
and correlation to hardware evaluation performed on a
µModule package mounted to a hardware test board. 2. θJCbottom, the thermal resistance from junction to the
The motivation for providing these thermal coefficients is bottom of the product case, is determined with all of
found in JESD 51-12 (Guidelines for Reporting and Using the component power dissipation flowing through the
Electronic Package Thermal Information). bottom of the package. In the typical µModule regulator,
the bulk of the heat flows out the bottom of the pack-
Many designers may opt to use laboratory equipment
age, but there is always heat flow out into the ambient
and a test vehicle such as the demo board to anticipate
environment. As a result, this thermal resistance value
the µModule regulator’s thermal performance in their ap-
may be useful for comparing packages, but the test
plication at various electrical and environmental operating
conditions don’t generally match the user’s application.
conditions to compliment any FEA activities. Without FEA
software, the thermal resistances reported in the Pin Con- 3. θJCtop, the thermal resistance from junction to top of
figuration section are, in and of themselves, not relevant to the product case, is determined with nearly all of the
providing guidance of thermal performance; instead, the component power dissipation flowing through the top of
derating curves provided in this data sheet can be used the package. As the electrical connections of the typical
in a manner that yields insight and guidance pertaining to µModule regulator are on the bottom of the package, it
one’s application usage, and can be adapted to correlate is rare for an application to operate such that most of
thermal performance to one’s own application. the heat flows from the junction to the top of the part.
As in the case of θJCbottom, this value may be useful
The Pin Configuration section gives four thermal coeffi-
for comparing packages but the test conditions don’t
cients explicitly defined in JESD 51-12; these coefficients
generally match the user’s application.
are quoted or paraphrased below:

µMODULE DEVICE θJA JUNCTION-TO-AMBIENT RESISTANCE

θJCtop JUNCTION-TO-CASE CASE (TOP)-TO-AMBIENT
(TOP) RESISTANCE RESISTANCE

θJB JUNCTION-TO-BOARD RESISTANCE

JUNCTION AMBIENT

θJCbot JUNCTION-TO-CASE CASE (BOTTOM)-TO-BOARD BOARD-TO-AMBIENT

(BOTTOM) RESISTANCE RESISTANCE RESISTANCE

4638 F10

Figure 10. Graphical Representation of JESD 51-12 Thermal Coefficients

Rev. C

For more information www.analog.com 19

LTM4638
APPLICATIONS INFORMATION
4. θJB, the thermal resistance from junction to the printed thermal resistance values; (3) the model and FEA software
circuit board, is the junction-to-board thermal resistance is used to evaluate the LTM4638 with heat sink and airflow;
where almost all of the heat flows through the bottom (4) having solved for and analyzed these thermal resistance
of the µModule package and into the board, and is really values and simulated various operating conditions in the
the sum of the θJCbottom and the thermal resistance of software model, a thorough laboratory evaluation replicates
the bottom of the part through the solder joints and the simulated conditions with thermocouples within a
through a portion of the board. The board temperature controlled environment chamber while operating the device
is measured a specified distance from the package. at the same power loss as that which was simulated. An
A graphical representation of the aforementioned thermal outcome of this process and due diligence yields the set
resistances is given in Figure 10; blue resistances are of derating curves shown in this data sheet. After these
contained within the μModule regulator, whereas green laboratory tests have been performed and correlated to
resistances are external to the µModule package. the LTM4638 model, then the θJB and θBA are summed
together to provide a value that should closely equal the
As a practical matter, it should be clear to the reader that θJA value because approximately 100% of power loss
no individual or sub-group of the four thermal resistance flows from the junction through the board into ambient
parameters defined by JESD 51-12 or provided in the with no airflow or top mounted heat sink.
Pin Configuration section replicates or conveys normal
The 1.0V, 1.5V, 3.3V and 5V power loss curves in Figure
operating conditions of a μModule regulator. For example,
11 to Figure 14 can be used in coordination with the
in normal board-mounted applications, never does 100%
load current derating curves in Figure 15 to Figure 21
of the device’s total power loss (heat) thermally conduct
for calculating an approximate θJA thermal resistance
exclusively through the top or exclusively through bot-
tom of the µModule package—as the standard defines for the LTM4638 with various airflow conditions. The
for θJCtop and θJCbottom, respectively. In practice, power power loss curves are taken at room temperature, and
loss is thermally dissipated in both directions away from are increased with a multiplicative factor according to the
the package—granted, in the absence of a heat sink and ambient temperature. This approximate factor is: 1.2 for
airflow, a majority of the heat flow is into the board. 120°C at junction temperature. Maximum load current is
achievable while increasing ambient temperature as long
Within the LTM4638 be aware there are multiple power as the junction temperature is less than 120°C, which is
devices and components dissipating power, with a con- a 5°C guard band from maximum junction temperature
sequence that the thermal resistances relative to different of 125°C. When the ambient temperature reaches a point
junctions of components or die are not exactly linear with where the junction temperature is 120°C, then the load
respect to total package power loss. To reconcile this current is lowered to maintain the junction at 120°C while
complication without sacrificing modeling simplicity—but increasing ambient temperature up to 120°C. The derat-
also, not ignoring practical realities—an approach has been ing curves are plotted with the output current starting at
taken using FEA software modeling along with laboratory 15A and the ambient temperature at 30°C. The output
testing in a controlled environment chamber to reason- voltages are 1.0V, 1.5V, 3.3V and 5V. These are chosen
ably define and correlate the thermal resistance values to include the lower and higher output voltage ranges
supplied in this data sheet: (1) Initially, FEA software is for correlating the thermal resistance. Thermal models
used to accurately build the mechanical geometry of the are derived from several temperature measurements in
LTM4638 and the specified PCB with all of the correct a controlled temperature chamber along with thermal
material coefficients along with accurate power loss source modeling analysis. The junction temperatures are moni-
definitions; (2) this model simulates a software-defined tored while ambient temperature is increased with and
JEDEC environment consistent with JSED 51-12 to predict without airflow. The power loss increase with ambient
power loss heat flow and temperature readings at different temperature change is factored into the derating curves.
interfaces that enable the calculation of the JEDEC-defined The junctions are maintained at 120°C maximum while
Rev. C

20 For more information www.analog.com

 LTM4638
APPLICATIONS INFORMATION
3.0 3.0 4.0
600kHz 600kHz
3.5
2.5 2.5
3.0
2.0 2.0 800kHz
POWER LOSS (W)

POWER LOSS (W)

POWER LOSS (W)

2.5

1.5 1.5 2.0

1000kHz
1.5
1.0 1.0
1.0
0.5 0.5
VIN = 5V VIN = 5V 0.5 VIN = 5V
VIN = 12V VIN = 12V VIN = 12V
0 0 0
0 3 6 9 12 15 0 3 6 9 12 15 0 3 6 9 12 15
LOAD CURRENT (A) LOAD CURRENT (A) LOAD CURRENT (A)
4638 F11 4638 F12 4638 F13

Figure 11. Power Loss at 1V Output Figure 12. Power Loss at 1.5V Output Figure 13. Power Loss at 3.3V
Output
5.0 16 16

4.5 14 14
4.0
12 12
3.5
LOAD CURRENT (A)

LOAD CURRENT (A)

POWER LOSS (W)

10 10
3.0
2.5 8 8

2.0 6 6
1.5
4 4
1.0 OLFM OLFM
2 200LFM 2 200LFM
0.5 400LFM 400LFM
VIN = 12V, 2000kHz
0 0 0
0 3 6 9 12 30 40 50 60 70 80 90 100 110 120 30 40 50 60 70 80 90 100 110 120
LOAD CURRENT (A) AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C)
4638 F14
4638 F15 4638 F16

Figure 14. Power Loss at 5V Output Figure 15. 5V to 1V Derating Curve, Figure 16. 12V to 1V Derating
No Heat Sink Curve, No Heat Sink

16 16 16

14 14 14

12 12 12
LOAD CURRENT (A)

LOAD CURRENT (A)

LOAD CURRENT (A)

10 10 10

8 8 8

6 6 6

4 4 4
OLFM OLFM OLFM
2 200LFM 2 200LFM 2 200LFM
400LFM 400LFM 400LFM
0 0 0
30 40 50 60 70 80 90 100 110 120 30 40 50 60 70 80 90 100 110 120 30 40 50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C)
4638 F17 4638 F18 4638 F19

Figure 17. 5V to 1.5V Derating Figure 18. 12V to 1.5V Derating Figure 19. 5V to 3.3V Derating
Curve, No Heat Sink Curve, No Heat Sink Curve, No Heat Sink
Rev. C

For more information www.analog.com 21

LTM4638
APPLICATIONS INFORMATION
16 16

14 14

12 12
LOAD CURRENT (A)

LOAD CURRENT (A)

10 10

8 8

6 6

4 4
OLFM OLFM
2 200LFM 2 200LFM
400LFM 400LFM
0 0
30 40 50 60 70 80 90 100 110 120 30 40 50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C)
4638 F20 4638 F21

Figure 20. 12V to 3.3V Derating Figure 21. 12V to 5V Derating

Curve, No Heat Sink Curve, No Heat Sink

Table 3. 1.0V Output

DERATING CURVE VIN (V) POWER LOSS CURVE AIR FLOW (LFM) HEAT SINK θJA (°C/W)
Figures 15, 16 5, 12 Figure 11 0 None 15
Figures 15, 16 5, 12 Figure 11 200 None 12
Figures 15, 16 5, 12 Figure 11 400 None 11

Table 4. 1.5V Output

DERATING CURVE VIN (V) POWER LOSS CURVE AIR FLOW (LFM) HEAT SINK θJA (°C/W)
Figures 17, 18 5, 12 Figure 12 0 None 15
Figures 17, 18 5, 12 Figure 12 200 None 12
Figures 17, 18 5, 12 Figure 12 400 None 11

Table 5. 3.3V Output

DERATING CURVE VIN (V) POWER LOSS CURVE AIR FLOW (LFM) HEAT SINK θJA (°C/W)
Figures 19, 20 5, 12 Figure 13 0 None 15
Figures 19, 20 5, 12 Figure 13 200 None 12
Figures 19, 20 5, 12 Figure 13 400 None 11

Table 6. 5V Output
DERATING CURVE VIN (V) POWER LOSS CURVE AIR FLOW (LFM) HEAT SINK θJA (°C/W)
Figure 21 12 Figure 14 0 None 15
Figure 21 12 Figure 14 200 None 12
Figure 21 12 Figure 14 400 None 11

Rev. C

22 For more information www.analog.com

 LTM4638
APPLICATIONS INFORMATION
Table 7. Output Voltage Response vs Component Matrix (Refer to Figure 23)
COUT2
COUT1 VENDORS PART NUMBER DESCRIPTION VENDORS PART NUMBER DESCRIPTION
Murata GRM186R60J226ME 22µF, 6.3V, X5R, PANASONIC EEF-GX0E471L 470µF, 2.5V, 3mΩ
0603
TDK C1608X5R0J226M080AC 22µF, 6.3V, X5R,
0603
Murata GRM31CR60J107ME 100µF, 6.3V,
X5R, 1206
Taiyo Yuden JMK316BJ107ML 100µF, 6.3V,
X5R, 1206
TDK C3216X5R0J107M160AB 100µF, 6.3V,
X5R, 1206

All Ceramic Output Capacitors

RTH CTH
on on LOAD PK-PK RECOVERY
VOUTn VINn RFB fSW COUT1 COUT2 COMPa COMPa COMPa STEP DEVIATION TIME
(V) (V) (kΩ) (kHz) (CERAMIC CAP) (BULK CAP) (pF) (kΩ) (pF) (A) (mV) (µs)
1 5 90.9 600 22µF + 3x100µF None Short to None None 3.75 85 40
COMPb
1 12 90.9 600 22µF + 3x100µF None Short to None None 3.75 94.4 40
COMPb
1.5 5 40.2 600 22µF + 3x100µF None Short to None None 3.75 106.4 40
COMPb
1.5 12 40.2 800 22µF + 3x100µF None Short to None None 3.75 109.1 40
COMPb
2.5 5 19.1 800 22µF + 3x100µF None Short to None None 3.75 165.4 40
COMPb
2.5 12 19.1 1000 22µF + 3x100µF None Short to None None 3.75 171 40
COMPb
3.3 5 13.3 800 22µF + 3x100µF None Short to None None 3.75 218 40
COMPb
3.3 12 13.3 1000 22µF + 3x100µF None Short to None None 3.75 218 40
COMPb
5 12 8.25 1500 22µF + 3x100µF None Short to None None 3.75 328 40
COMPb

lowering output current or power with increasing ambient 92°C ambient temperature is subtracted from the 120°C
temperature. The decreased output current will decrease junction temperature, then the difference of 28°C divided
the internal module loss as ambient temperature is in- by 18W equals a 15.5°C/W θJA thermal resistance. Table 3
creased. The monitored junction temperature of 120°C specifies a 15°C/W value which is very close. Table 4, Table 5
minus the ambient operating temperature specifies how and Table 6 provide equivalent thermal resistances for
much module temperature rise can be allowed. As an 1.5V 3.3V and 5V outputs with and without airflow and
example, in Figure 16 the load current is derated to ~8A heat sinking. The derived thermal resistances in Table 3,
at ~92°C with no air flow or heat sink and the power loss Table 4, Table 5 and Table 6 for the various conditions can
for the 12V to 1.5V at 8A output is about 1.8W. The 8W be multiplied by the calculated power loss as a function
loss is calculated with the ~1.5W room temperature loss of ambient temperature to derive temperature rise above
from the 12V to 1.5V power loss curve at 8A, and the 1.2 ambient, thus maximum junction temperature. Room
multiplying factor at 120°C junction temperature. If the temperature power loss can be derived from the efficiency
Rev. C

For more information www.analog.com 23

LTM4638
APPLICATIONS INFORMATION
curves in the Typical Performance Characteristics section • To minimize the via conduction loss and reduce module
and adjusted with the above ambient temperature multipli- thermal stress, use multiple vias for interconnection
cative factors. The printed circuit board is a 1.6mm thick between top layer and other power layers.
4-layer board with two ounce copper for the two outer
• Do not put via directly on the pad, unless they are
layers and one ounce copper for the two inner layers. The
capped or plated over.
PCB dimensions are 95mm × 76mm.
• Use a separated SGND ground copper area for com-
Safety Considerations ponents connected to signal pins. Connect the SGND
The LTM4638 modules do not provide galvanic isolation to GND underneath the unit.
from VIN to VOUT. There is no internal fuse. If required, • Bring out test points on the signal pins for monitoring.
a slow blow fuse with a rating twice the maximum input
current needs to be provided to protect each unit from • Keep separation between CLKIN, CLKOUT and FREQ pin
catastrophic failure. The device does support thermal traces to minimize possibility of noise due to crosstalk
shutdown and over current protection. between these signals.
Figure 22 gives a good example of the recommended layout.
Layout Checklist/Example
The high integration of LTM4638 makes the PCB board
layout very simple and easy. However, to optimize its electri- VOUT

cal and thermal performance, some layout considerations

are still necessary.
• Use large PCB copper areas for high current paths,
including VIN, GND and VOUT. It helps to minimize the
PCB conduction loss and thermal stress.
VIN
• Place high frequency ceramic input and output capaci-
tors next to the VIN, PGND and VOUT pins to minimize
high frequency noise.
GND
• Place a dedicated power ground layer underneath the
unit. 4638 F22

Figure 22. Recommended PCB Layout

Rev. C

24 For more information www.analog.com

 LTM4638
APPLICATIONS INFORMATION

FREQ CLKOUT VOUT FREQ MODE/ VOUT

VIN VIN CLKIN V
VIN VOUT 1.0V VIN OUT 1.5V
3.1V TO 20V 22µF 3.1V TO 20V 22µF
15A 30A
RUN VOSNS+ 100µF 25V RUN VOSNS+
25V LTM4638 6.3V ×2 100µF
INTVCC LTM4638
×3 6.3V
33pF
MODE/CLKIN 33pF INTVCC ×6
PHMODE PHMODE FB
TRACK/SS FB TRACK/SS COMPa
0.1µF PGOOD COMPa 0.1µF PGOOD COMPb
COMPb 90.9k

GND VOSNS– GND CLKOUT VOSNS–

4638 F23

Figure 23. 3.1VIN to 20VIN, 1V Output at 15A Design FREQ MODE/ CLKOUT
VIN CLKIN VOUT
RUN VOSNS+
113k
LTM4638
INTVCC
FREQ CLKOUT PHMODE
VOUT FB
VIN 3.3V
VIN VOUT TRACK/SS COMPa
5V TO 20V 22µF 15A
RUN VOSNS+ PGOOD COMPb
25V LTM4638 47µF + 220µF 40.2k
INTVCC 6.3V
×2 6.3V
2MHz CLOCK MODE/CLKIN GND VOSNS–
PHMODE
4638 F25
TRACK/SS FB
0.1µF PGOOD COMPa Figure 25. 3.1VIN to 20VIN, Two Phases, 1.5V at 30A Design
COMPb 13.3k
GND VOSNS–

4638 F24

Figure 24. 5VIN to 20VIN, 3.3V Output with 2MHz External Clock

Rev. C

For more information www.analog.com 25

LTM4638
APPLICATIONS INFORMATION

FREQ CLKOUT
VOUT
VIN
VIN VOUT 1.5V
3.1V TO 20V 22µF 100µF 15A
25V RUN VOSNS+ 6.3V
×2 LTM4638 ×3
INTVCC
MODE/CLKIN
PHMODE 33pF
TRACK/SS FB
0.1µF PGOOD COMPa
COMPb 40.2k
GND VOSNS–

FREQ CLKOUT
VOUT2
VIN VOUT 1.2V
100µF 15A
RUN VOSNS+ 6.3V
LTM4638
INTVCC ×3
MODE/CLKIN
60.4k PHMODE 33pF
TRACK/SS FB

60.4k PGOOD COMPa

COMPb 60.4k
GND VOSNS–

4638 F26

Figure 26. 3.1VIN to 20VIN, 1.2V and 1.5V with Coincident Tracking

Rev. C

26 For more information www.analog.com

 LTM4638
PACKAGE DESCRIPTION
PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY.

LTM4638 Component BGA Pinout

PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION
A1 VOUT A2 VOUT A3 VOUT A4 VOUT A5 VOUT A6 TSENSE+ A7 TSENSE–
B1 VOSNS + B2 GND B3 INTVCC B4 RUN B5 PGOOD B6 GND B7 SW
C1 FB C2 VOSNS– C3 GND C4 GND C5 GND C6 GND C7 GND
D1 COMPa D2 MODE/CLKIN D3 VIN D4 VIN D5 GND D6 GND D7 GND
E1 FREQ E2 TRACK/SS E3 VIN E4 VIN E5 GND E6 GND E7 GND
F1 COMPb F2 CLKOUT F3 VOUT F4 VIN F5 GND F6 GND F7 GND
G1 VOUT G2 VOUT G3 VOUT G4 VIN G5 PHMODE G6 GND G7 GND

Rev. C

For more information www.analog.com 27

28
BGA Package
49-Lead (6.25mm × 6.25mm × 5.02mm)
(Reference LTC DWG# 05-08-1574 Rev A)
LTM4638

Z
DETAIL A SEE NOTES
PIN 1 A
5.48 ±0.20 A1 6
CORNER A2 7 6 5 4 3 2 1
SEE NOTES
2× aaa Z
4 ccc Z PIN 1
3
A

b B
b1
MOLD C
CAP
5.28 ±0.20 D SUBSTRATE F D
H3 H1
H2 E
e
PACKAGE DESCRIPTION

F
DETAIL B

// bbb Z
G

Øb (49 PLACES)

subject to change without notice. No license For

X b e
ddd M Z X Y
E Y G
eee M Z

is granted
DETAIL B
PACKAGE SIDE VIEW

more by
PACKAGE TOP VIEW

aaa Z
PACKAGE BOTTOM VIEW

2×
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994

information
2. ALL DIMENSIONS ARE IN MILLIMETERS

implication or
DETAIL A 3 BALL DESIGNATION PER JEP95
4 DETAILS OF PIN 1 IDENTIFIER ARE OPTIONAL,
DIMENSIONS BUT MUST BE LOCATED WITHIN THE ZONE INDICATED.

2.400
1.600
0.800
0.000
0.800
1.600
2.400
SYMBOL MIN NOM MAX NOTES THE PIN 1 IDENTIFIER MAY BE EITHER A MOLD OR
MARKED FEATURE

www.analog.com
A 4.68 5.02 5.36
0.40 REF Ø 49x 2.400
A1 0.30 0.40 0.50 BALL HT 5. PRIMARY DATUM -Z- IS SEATING PLANE
1.600 A2 1.41 1.52 1.69 6 PACKAGE ROW AND COLUMN LABELING MAY VARY
b 0.45 0.50 0.55 BALL DIMENSION ! AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
0.800
b1 0.37 0.40 0.43 PAD DIMENSION LAYOUT CAREFULLY
0.000 D 6.25
E 6.25
0.800
e 0.80
1.600 F 4.80
2.400
G 4.80
H1 0.32 REF SUBSTRATE THK
H2 1.20 REF MOLD CAP HT
SUGGESTED PCB LAYOUT
H3 3.10 REF INDUCTOR HT

Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
otherwise under any patent or patent rights of Analog Devices.
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
TOP VIEW COMPONENT
aaa 0.15 PIN 1
bbb 0.10
ccc 0.20
TRAY PIN 1
ddd 0.20 BEVEL
eee 0.08 PACKAGE IN TRAY LOADING ORIENTATION
BGA 49 1218 REV A
TOTAL NUMBER OF BALLS: 49

Rev. C
 LTM4638
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 08/19 Added LTM4638IY to Order Information 2
Added Temperature Monitoring 17, 18
B 11/19 Updated Peak Solder Reflow Body Temperature to 250°C 2
Updated Package Thermal Resistance 2
Changed RUN Threshold to 1.25V 8, 15
Updated Coefficient in Frequency Equation to 1.67e11 from 1.6e11 12
C 01/21 Change text from PNP to NPN on TSENSE+. 8
Added TSENSE+ and TSENSE– on Block Diagram. 9
Removed unnecessary symbol from Block Diagram. 9

Rev. C

For more information www.analog.com 29

LTM4638
PACKAGE PHOTO

DESIGN RESOURCES
SUBJECT DESCRIPTION
µModule Design and Manufacturing Resources Design: Manufacturing:
• Selector Guides • Quick Start Guide
• Demo Boards and Gerber Files • PCB Design, Assembly and Manufacturing Guidelines
• Free Simulation Tools • Package and Board Level Reliability
µModule Regulator Products Search 1. Sort table of products by parameters and download the result as a spread sheet.
2. Search using the Quick Power Search parametric table.

Digital Power System Management Analog Devices’ family of digital power supply management ICs are highly integrated solutions that
offer essential functions, including power supply monitoring, supervision, margining and sequencing,
and feature EEPROM for storing user configurations and fault logging.

RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
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LTM4638.
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LTM4644 Quad 4A µModule Regulator 4V ≤ VIN ≤ 14V. 0.6V ≤ VOUT ≤ 5.5V. 9mm × 15mm × 5.01mm BGA

Rev. C

30
01/21
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