Computer Organization and

Architecture
Instruction Set Architecture
 Hamacher: Ch 2
 Stallings: Ch 12

 A complete instruction set, including operand addressing methods, is often

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Memory Locations and Addresses
 Memory consists of many millions of storage cells, each cell holds a bit of
information, 0 or 1
 A single bit represents a very small amount of information, bits are seldom
handled individually. Information is usually handled in larger units
 The memory is organized so that a group of n bits can be stored or retrieved in a
single, basic operation.
 Each group of n bits is referred to as a word of information, and n is called the
word length.
 Word length can be 16 to 64 bits
 Memory is a collection of consecutive word of the size specified by the word
length
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Memory Locations and Addresses

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Memory Locations and Addresses
 A common word length is 32 bits
 Such a word can store a 32-bit signed integer or four 8-bit bytes (e.g., ASCII
characters)
 For 32-bit integer encoding, bit b31 is sign bit
 Words in memory may store data or machine instructions for a program
 Each machine instruction may require one or more consecutive words for
encoding

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Memory Locations and Addresses
 To store or retrieve items of information, each memory location has a distinct
address
 Numbers 0 to 2k  1 are used as addresses for successive locations in the memory
 The 2k locations constitute the address space
 Memory size set by k (number of address bits)
 Examples:
 k  20  220 or 1M locations,
 k  32  232 or 4G locations

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Byte Addressability
 Byte size is always 8 bits
 But word length may range from 16 to 64 bits
 Impractical to assign an address to each bit
 Instead, provide a byte-addressable memory that assigns an address to each byte
 Byte locations have addresses 0, 1, 2, …
 Assuming that the word length is 32 bits, word locations have addresses 0, 4, 8, …

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Big-Endian and Little-Endian Assignments
 Two ways to assign byte address across words
 Big-endian
 Little-endian
 Big-endian addressing assigns lower addresses to more significant (leftmost)
bytes of word
 The lower byte addresses are used for the less significant bytes (the rightmost
bytes) of the word. Little-endian
 Commercial computers use either approach, and some can support both
approaches
 Addresses for 32-bit words are still 0, 4, 8, …
 Bits in each byte labeled b7 … b0, left to right

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Big-Endian and Little-Endian Assignments
 The property of endianness does not extend beyond an individual data unit.
 In any machine, aggregates such as files, data structures, and arrays are
composed of multiple data units, each with endianness
 Machines, such as the Intel 80x86, x86, VAX, and Alpha, are little-endian
machines, whereas others, such as the IBM System 370/390, the Motorola 680x0,
Sun SPARC, and most RISC machines, are big endian

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Big-Endian and Little-Endian Assignments

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Big-Endian and Little-Endian Assignments

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Word Alignment
 Number of bytes per word is normally a power of 2
 Word locations have aligned addresses if they begin at byte addresses that are
multiples of the number of bytes in a word
 Examples of aligned addresses:
2 bytes per word  0, 2, 4, …
8 bytes per word  0, 8, 16, …
 Some computers permit unaligned addresses

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Accessing Numbers and Characters
 A number usually occupies one word, and can be accessed in the memory by
specifying its word address.
 Individual characters can be accessed by their byte address.
 The beginning of a character string is indicated by giving the address of the byte
containing its first character.

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Example C Data Structure and Its Endian Maps

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Example C Data Structure and Its Endian Maps
struct{
int a; //0x1112_1314 word
int pad; //
double b; //0x2122_2324_2526_2728 doubleword
char* c; //0x3132_3334 word
char d[7]; //'A','B','C','D','E','F','G' byte array
short e; //0x5152 halfword
int f; //0x6162_6364 word
} s;

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Big-Endian and Little-Endian Assignments
 Some observations about the above data structure:
 Each data item has the same address in both schemes.
 For example, the address of the doubleword with hexadecimal value 2122232425262728 is 08.
 Within any given multibyte scalar value, the ordering of bytes in the little-endian structure is
the reverse of that for the big-endian structure.
 Endianness does not affect the ordering of data items within a structure.
 Thus, the four-character word c exhibits byte reversal, but the seven-character byte array d does not. Hence,
the address of each individual element of d is the same in both structures.

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Big-Endian and Little-Endian Assignments
 The following points favor the big-endian style:
 Character-string sorting: A big-endian processor is faster in comparing integer- aligned
character strings; the integer ALU can compare multiple bytes in parallel.

 Decimal dumps: All values can be printed left to right without causing confusion.

 Consistent order: Big-endian processors store their integers and character strings in the same
order (most significant byte comes first).

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Big-Endian and Little-Endian Assignments
 The following points favor the little-endian style:
 A big-endian processor has to perform addition when it converts a 32-bit integer address to a
16-bit integer address, to use the least significant bytes.

 It is easier to perform higher-precision arithmetic with the little-endian style; you don’t have
to find the least-significantbyte and move backward.

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Memory Operations
 Memory contains data & program instructions
 Control circuits initiate transfer of data and instructions between memory and
processor
 Two basic operations involving the memory are needed
 Read (Load, Fetch) and
 Write (Store).
 Read operation: transfers a copy of the contents of a specific memory location to
the processor
 Write operation: transfers an item of information from the processor to a specific
memory location, overwriting the former contents of that location

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Instructions and Instruction Sequencing
 A computer must have instructions capable of performing four types of
operations:
 Data transfers between the memory and the processor registers
 Arithmetic and logic operations on data
 Program sequencing and control
 I/O transfers

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Register Transfer Notation
 Register transfer notation is used to describe hardware-level data transfers and
operations
 Predefined names for processor register (R0, R5 ) and I/O registers (DATAIN,
OUTSTATUS)
 Arbitrary names (LOC, PLACE, A ) for locations in memory
 Use […] to denote contents of a location
 Use  to denote transfer to a destination
 Example: R2  [LOC] // (transfer from LOC in memory to register R2)

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Register Transfer Notation
 Consider the operation that adds the contents of registers R2 and R3, and places
their sum into register R4. This action is indicated as
 R4 ← [R2] + [R3]
 This type of notation is known as Register Transfer Notation (RTN).
 The right-hand side of an RTN expression always denotes a value, and the left-
hand side is the name of a location where the value is to be placed, overwriting
the old contents of that location.

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Assembly-Language Notation
 RTN shows data transfers and arithmetic
 Another notation is needed to represent machine instructions & programs using
them
 Assembly language is used for this purpose
 For the two preceding examples using RTN, the assembly-language instructions
are:
Load R2, LOC

Add R4, R2, R3

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Assembly-Language Notation
 An instruction specifies the desired operation and the operands that
are involved
 We will use English words for the operations (e.g., Load, Store, and
Add)
 Commercial processors use mnemonics, usually abbreviations (e.g.,
LD, ST, and ADD)
 Mnemonics differ from processor to processor

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RISC and CISC Instruction Sets
 One of the most important characteristics that distinguish different computers is
the nature of their instructions.
 There are two fundamentally different approaches in the design of instruction
sets for modern computers
 Reduced Instruction Set Computers (RISC)
 Complex Instruction Set Computers (CISC)
 Reduced Instruction Set Computers (RISC)
 Each instruction occupies exactly one word in memory,
 All operands needed to execute a given arithmetic or logic operation specified by an
instruction are already in processor registers,
 Easier to pipeline,
 Reduces the complexity and
 The number of different types of instructions that may be included in the instruction set of a
computer

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RISC and CISC Instruction Sets
 Complex Instruction Set Computers (CISC)
 Have multi-word instructions,
 Allow operands directly from memory
 May specify more complicated operations.

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Introduction to RISC Instruction Sets
 Two key characteristics of RISC instruction sets are:
 Each instruction fits in a single word.
 A load/store architecture is used, in which
 Memory operands are accessed only using Load and Store instructions.
 All operands involved in an arithmetic or logic operation must either be in processor
registers, or one of the operands may be given explicitly within the instruction word.

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Introduction to RISC Instruction Sets
 Instructions/data are stored in the memory
 Processor register contents are initially invalid
 Because RISC requires register operands, data transfers are required before
arithmetic
 The Load instruction is used for this purpose:
Load destination, source
Load procr_register, mem_location
 Addressing mode specifies memory location; different modes are discussed later

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Introduction to RISC Instruction Sets
 Consider high-level language statement:
CAB
 A, B, and C correspond to memory locations
 RTN (Register Transfer Notation) specification with these symbolic names:
C  [A]  [B]
 Steps:
1. Fetch contents of locations A and B into the processor,
2. Compute sum, and
3. Transfer result to location C

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Introduction to RISC Instruction Sets
 Sequence of simple RISC instructions for task:
Load R2, A
Load R3, B
Add R4, R2, R3
Store R4, C

 Load instruction transfers data from memory to processor register

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Introduction to RISC Instruction Sets
 Add is a three-operand, or a three-address, instruction of the form
Add destination, source1, source2

 The Store instruction is of the form

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Instruction Execution and Straight-Line
Sequencing
 Consider the task C = A + B, implemented as C←[A] + [B]
 How is it stored in the memory? (32-bit word length, byte-addressable)
 Place first RISC instruction word at address i
 Remaining instructions are at i  4, i  8, i  12
 For now, assume that Load/Store instructions specify desired operand address
directly; this issue is discussed in detail later

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Instruction
Execution
and
Straight-
Line
Sequencing

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Branching
 We can illustrate the concept of branching with a program that adds a list of
numbers
 Same operations performed repeatedly,
so the program contains a loop
 Loop body is straight-line instruction sequence
 It must determine address of next number,
load value from the memory, and add to sum
 Branch instruction causes repetition of body

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Branching

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Branching
 Assume that size of list, n, stored at location N
 Use register R2 as a counter, initialized from N
 Body of loop includes the instruction Subtract R2, R2, #1 to decrement
counter in each loop pass
 Branch_if_[R2]0 goes to branch target LOOP as long as contents of R2 are
greater than zero
 Therefore, this is a conditional branch

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Branching
 Branches that test a condition are used in loops and various other programming
tasks
 One way to implement conditional branches is to compare contents of two
registers, e.g.,
Branch_if_[R4][R5] LOOP
 In generic assembly language with mnemonics the same instruction might
actually appear as
BGT R4, R5, LOOP

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Instruction Execution and Straight-Line
Sequencing
 How is the program executed?
 Processor has program counter (PC) register
 Address i for first instruction placed in PC
 The processor control circuits uses the information in the PC to fetch and execute
instructions, one at a time, in the order of increasing addresses.
 This is called straight-line sequencing.
 During execution of each instruction, PC register is incremented by 4
 PC contents are i  16 after Store is executed

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Instruction Execution and Straight-Line
Sequencing
 Executing a given instruction is a two-phase procedure:
 Instruction Fetch and
 Instruction Execute
 Instruction Fetch: involves fetching instruction from the memory location whose
address is in the PC.
 This instruction is placed in the instruction register (IR) in the processor
 Instruction execute: the instruction in IR is examined to determine which
operation is to be performed.
 The specified operation is then performed by the processor.
 This involves a small number of steps such as fetching operands from the memory or from
processor registers, performing an arithmetic or logic operation, and storing the result in the
destination location.

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Instruction Execution and Straight-Line
Sequencing
 During this two-phase procedure, the contents of the PC are advanced to point to
the next instruction.
 When the execute phase of an instruction is completed, the PC contains the
address of the next instruction, and a mew instruction phase can begin

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Addressing Modes
• Refer Stalling slides for the details

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Addressing Modes
 An address field in an instruction contains decimal value 14. Where is
the corresponding operand located for
 immediate addressing?
 direct addressing?
 indirect addressing?
 register addressing?
 register indirect addressing?

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Addressing Modes
 A PC-relative mode branch instruction is 3 bytes long. The address of
the instruction, in decimal, is 256028. Determine the branch target
address if the signed displacement in the instruction is -31.

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Addressing Modes
 A PC-relative mode branch instruction is stored in memory at address
62010. The branch is made to location 53010. The address field in the
instruction is 10 bits long. What is the binary value in the instruction?

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Addressing Modes
 Assume an instruction set that uses a fixed 16-bit instruction length.
Operand specifiers are 6 bits in length. There are K two-operand
instructions and L zero-operand instructions. What is the maximum
number of one-operand instructions that can be supported?

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Subroutines
 In a given program, a particular task may be executed many times using different
data
 Examples: mathematical function, list sorting
 Implement task in one block of instructions
 This is called a subroutine
 Rather than reproduce entire subroutine block in each part of program, use a
subroutine call
 A Call instruction is a special type of branch
 Store the contents of the PC in the link register
 Branch to the target address specified by the Call instruction

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Subroutines
 Branching to same block of instructions saves space in memory, but must branch
back
 The subroutine must return to calling program after executing last instruction in
subroutine
 This branch is done with a Return instruction
 Branch to the address contained in the link register
 Subroutine can be called from different places
 How can return be done to the correct place?
 This is the issue of subroutine linkage

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Subroutine Linkage
 During execution of Call instruction, PC upated to point to instruction after Call
 Save this address for Return instruction to use
 Simplest method: place address in link register
 Call instruction performs two operations: store updated PC contents in link
register, then branch to target (subroutine) address
 Return just branches to address in link register

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Subroutine Linkage

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Subroutine Nesting and the Stack
 We can permit one subroutine to call another, which results in subroutine nesting
 Link register contents after first subroutine call are overwritten after second
subroutine call
 First subroutine should save link register on the processor stack before second
call
 After return from second subroutine, first subroutine restores link register
Parameter Passing
 A program may call a subroutine many times with different data to obtain
different results
 Information exchange to/from a subroutine is called parameter passing
 Parameters may be passed in registers
 Simple, but limited to available registers
 Alternative: use stack for parameter passing, and also for local variables and
saving registers
The Stack Frame
 Locations at the top of the processor stack are used as a private work space by
subroutines
 A stack frame is allocated on subroutine entry and deallocated on subroutine exit
 A frame pointer (FP) register enables access to private work space for current
subroutine
 With subroutine nesting, the stack frame also saves return address and FP of
each caller
The Stack Frame

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