Lab Sheet : Combinational Circuit

EEN 682 - Advanced Digital System Design

Spring Semester, 2021-22

1 What is FPGA?
FPGA stands for Field Programmable Gate Array. Here ’Array’ means ar-
rangement, so ’Gate Array’ means arrangement of Gates. Now the question
arise what is a Gate? To put it simply, gate is the fundamental element of a
digital logic, which means it can take some digital inputs (possible values 0 or
1) and give a digital output (again 0 or 1). The digital output of these gates is
governed by the digital algebra, also known as Boolean Algebra after the name
of its inventor George Boole. In digital design these Gates are interconnected
to form more sophisticated digital systems. FPGAs are the integrated circuits
(ICs) in which these gates are interconnected as shown in fig. 1.

Figure 1: FPGA chip design.

In FPGA terms, the dots are called the Configurable Logic Blocks (CLB)
which means that their behaviour can be programmed to show different func-
tionalities. So we can configure them to function as AND gate or XOR gate or
as some other logic unit. The connecting lines, on the other hand, are called
Programmable Interconnect which ensures connection between the two blocks,
these interconnects can also be programmed as required. So we can connect
any CLB to any CLB on the chip through programmable interconnects. This

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programmability of CLB and Programmable Interconnects on FPGA allows us
to program the FPGA chip to work as any required digital circuit. This ex-
plains the ’Programmable’ part of ’Field Programmable Gate Array’. Finally,
the FPGAs are field programmable, means that the FPGA chips’ behaviour can
be reprogrammed even after their deployment in the field of operation.

2 FPGA Development Environment

The FPGA board of choice for this lab is a Xilinx Spartan 3 FPGA chip based
development board as shown in fig. 2, in conjunction with a FPGA programming
software known as Xilinx ISE 14.7 (Embedded version). Which is the free
version of the software.

Figure 2: Xininx Spartan 3e FPGA board

Now FPGA programming is different from the software programming of

microprocessors, as the former is focused on hardware description that would
get physically synthesised on the FPGA chip, while the later one is sequen-
tial execution of software instructions on a microprocessor. Thus the FPGA
programming languages are called Hardware Description Language (HDL). The
common examples of HDL are, Verilog, VHDL, SystemVerilog etc. The HDL
which is going to be used here is VHDL. VHDL stands for, V (Very High Speed
Integrated Circuit) H (Hardware) D (Description) L (Language). So the abbre-

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viation VHDL consists an abbreviation in it. More about VHDL fundamentals
could be read in the companion reading material.

2.1 Xilinx ISE 14.7

The FPGA process flow includes the following steps,
1. Create a new project.
2. Add a new VHDL source file to the project to describe the design module.
3. Add a testbench module to the project to simulate the functioning of the
design module. Testbench is a file that becomes a top module to the
design and applies inputs to the circuit, and checks that the outputs are
correct. This will be another VHDL file written slightly differently than
the one written earlier.
4. Simulate the design to test the design functionality.

5. Add a user constraints file (UCF) to the project to implement the design
module on the FPGA board. UCF allow us to assign FPGA physical pins
to the ports of design to be implemented on the FPGA.
6. Synthesize the design. This process will create a structural representation
of the design (similar to compiling C code into assembly code.
7. Implement the design. This process will translate the synthesized design to
something that can physically be mapped to the particular FPGA devise
(in our case xc3s500e).
8. Generate the file to program FPGA. In this step all information resulting
from the last two steps are gathered and put into a .bit file that the USB
programmer on the FPGA board (in our case Spartan 3E) understands.
9. Program the FPGA.
These steps are now described in detail,

1. First we need to create a New Project in ISE, following the given steps,
(a) Open the Xilinx ISE Design Suit 14.7. You can click on the ISE icon
on the desktop, or search Start / Xilinx Design Suite / 32-bit Project
Navigator
(b) Now either press the New Project tab or select File / New Project
from the toolbar at top. Change the Name and Location of the
project as suitable. Please note that Xilinx does not allow spaces
in path or file names. For example “FPGA Project” will not work,
same for the file name. Use the under score for spaces if required.
(c) Verify that HDL is selected from the ’Top-Level Source Type’ list.

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 (d) Click NEXT and in the next dialog box you should fill in the project
properties. Select an “Evaluation Development Board” from the drop
down list, and in our case you should select “Spartan 3E”. This will
automatically fill out the board information in the next five sections.
Make sure that the Synthesis Tool is XST, the Simulator is the ISim,
and the Preferred Language is VHDL. This is very important for
proper operation.
(e) Click NEXT and review the project summary page and then click
FINISH.
2. Now we need to add a new source to the created New Project, to do so
follow following steps,
(a) Choose Project / New Source or right click on the Hierarchy section
of the design windows to get the dialog box that adds a new source
file to your project, or use the New Source widget on the left vertical
tool bar. In the next window choose “VHDL Module” and give it a
file name.
(b) Click NEXT and you should see the module definition box. Here you
can setup I/O names with correct polarity and a choice for buses and
their width. Note that you do not have to add anything here right
away and you can always add the I/O definitions to the module’s
header when it is created. After you’re done click NEXT and then
observe the summary page for a quick review of the I/O list.
(c) Now you should have a tab for the VHDL file opened in the ISE main
pane. Here the VHDL code for circuit implementation will be added.
3. After writing the VHDL design code we need to add a testbench module
to the created New Project, to do so follow following steps,

(a) Ensure that the ISE mode is changed to “Simulation” from ”Imple-
mentation”, by changing the “View” field in the top left pane to
”Simulation”.
(b) Add a new source fle to the project as described in step 2.a. The
only change in that step would be to select “VHDL Test Bench” to
create a VHDL file that will contain the Testbech.
(c) Click NEXT and choose which design you want to associate the test
bench with.
(d) Click NEXT and after observing the summary click FINISH. Now
you’ll get a new piece of VHDL code generated for you, that would
be the testbench for the design.
(e) Complete the testbench code.
4. After writing the tesbench we need to simulate the design. To do so follow
the following steps,

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 (a) Select the test bench file and check for the syntactic errors by click-
ing the “Behavioral Check Syntax” in the ’Processes’ windows right
below. If your code is correct syntactically then you’ll get a green
check mark.
(b) Double-click the “Simulate Behavioral Model” to see the waveform
generated by the ISim.
(c) The simulation is now done. You can always go back to the test
bench and make a more complicated set of tests and re-simulate the
circuit.
5. After successful simulation, we need to add a user constraints file to im-
plement the design on the FPGA board. These steps are not required to
be followed as of now, and are only given here for the sake of complete
picture. To do so follow following step,
(a) Add a new source fle to the project as described in step 2.a. The
only change in that step would be that now we have to select “Im-
plementation Constraints File” to create a user constraints file.
(b) Click NEXT and after observing the summary click FINISH. Now
you’ll get a new file generated for you, that would be the user con-
straint file for the design.
6. After adding the constraints to UCF, synthesize the design by following
the given steps.
(a) Ensure that the ISE mode is changed to “Implementation” from
”Simulation”, by changing the “View” field in the top left pane to
”Implementation”.
(b) Set the design file created in step 1 as the top module, by right
clicking on it in the ’Hierarchy’ window and selecting ”Set as top
module”.
(c) Double click ”Synthesize – XST” in the lower left pane. After the
process is done, you will either get a green check mark (everything
is fine), a yellow attention mark (there are warnings!), or a red cross
mark (there are errors!), and orange question mark just means “out of
date”. In the case of errors you need to investigate them by looking at
the Errors tab on the bottom pane and fix, and then rerun synthesis.
7. After the Synthesize step, next in line is Implement.For implementation
of the design follow the given steps.
(a) With your top module source file selected, double click the ”Imple-
ment Design” process in the Processes tab.
(b) You should see a green check mark if this step finishes without issues.
8. After implementation part is done we need to convert the design into a
bitstream (.bit) file. To do so follow the given steps.

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 (a) Double-click the ”Generate Programming File” to generate a .bit file
which will be used in the final step to program the board. Now the
design is ready to be put on the board so we can physically see its
functionality.
Attention: Before proceeding to the next step connect the board via
the USB cable to the PC you’re using, and turn on the power, the next
step ensure proper connection to the board. Also note that you do not
have to do steps 6, 7, and 8 individually. These processes are dependent
on each other, if one needs a preceding process to be updated then it
will automatically run that process before it runs itself. So you can just
proceed to step 9 skipping 6,7, and 8 and watch ISE do everything for
you.
9. Once the bitstream file is generated, it could be used to program the
FPGA board, using a programming cable. Here are the steps to carry
that out.

(a) Double click ”Configure Target Device” and ISE will launch yet an-
other Xilinx tool called iMpact.
(b) A warning box appears complaining about “No iMpact project file
exists. . . ”, so just click OK to launch iMpact as it will automatically
read your existing project.
(c) In the ISE iMpact window, double click Boundary Scan in the top
left pane.
(d) In the boundary scan windows in the main pane, where it says “Right
click to Add Device or Initialize chain” right-click in the middle of
the page and select ”Initialize Chain”. This will ensure there is a
good connection to your board and ISE can communicate with it.
(e) After iMpact verifies that the cable is connected it will prompt to
load the .bit file, generated in step 8. Double click or select the bit
file and click open, again make sure it is the right file.
(f) After the bit file is read, iMpact prompts you to attach a PROM
controller, just click NO to skip this step since we’re not putting
anything in the Flash memory.
(g) In the next dialog box you would be verifying which device on the
board you’re targeting but in our case we only have the FPGA chip
to program, so click Ok and the preparation for programming the
board is complete.
(h) All that is left noe is to right click on the green chip icon with the
Xilinx logo in the main pane and click Program. After the commu-
nication bar finishes, your design is programmed to the Spartan 3E
FPGA board.
This completes the FPGA design flow.

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3 Experiments
3.1 Exp 1: Half Adder
3.1.1 VHDL design code for half adder

l i b r a r y IEEE ;
use IEEE . STD LOGIC 1164 .ALL;

entity ha i s
Port ( i n 1 : in STD LOGIC ;
in2 : in STD LOGIC ;
sum : out STD LOGIC ;
cout : out STD LOGIC ) ;
end ha ;

architecture B e h a v i o r a l of ha i s

begin
sum<=(i n 1 xor i n 2 ) ;
cout <=(i n 1 and i n 2 ) ;
end B e h a v i o r a l ;

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 Figure 3: Half adder simulation waveform

3.1.2 VHDL Testbench for half adder

LIBRARY i e e e ;
USE i e e e . s t d l o g i c 1 1 6 4 .ALL;
ENTITY h a t b IS
END h a t b ;

ARCHITECTURE b e h a v i o r OF h a t b IS
COMPONENT ha
PORT( i n 1 : IN s t d l o g i c ; i n 2 : IN s t d l o g i c ;
sum : OUT s t d l o g i c ; c o u t : OUT s t d l o g i c ) ;
END COMPONENT;

signal in1 tb : s t d l o g i c := ’ 0 ’ ;
signal in2 tb : s t d l o g i c := ’ 0 ’ ;
signal sum tb : std logic ;
signal cout tb : std logic ;

BEGIN
uut : ha PORT MAP ( i n 1 => i n 1 t b , i n 2 => i n 2 t b ,
sum => sum tb , c o u t => c o u t t b ) ;

s t i m p r o c : process
begin
i n 1 t b <= ’0 ’; i n 2 t b <= ’0 ’; wait f o r 5 ns ;
i n 1 t b <= ’0 ’; i n 2 t b <= ’1 ’; wait f o r 5 ns ;
i n 1 t b <= ’1 ’; i n 2 t b <= ’0 ’; wait f o r 5 ns ;
i n 1 t b <= ’1 ’; i n 2 t b <= ’1 ’; wait f o r 5 ns ;
end process ;

END;
The simulation waveform thus obtained is shown is fig. 3.

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3.2 Exp 2: Full Adder
3.2.1 VHDL design code for full adder

l i b r a r y IEEE ;
use IEEE . STD LOGIC 1164 .ALL;

entity f a i s
Port ( i n 1 : in STD LOGIC ;
in2 : in STD LOGIC ;
cin : in STD LOGIC ;
sum : out STD LOGIC ;
cout : out STD LOGIC ) ;
end f a ;

architecture B e h a v i o r a l of f a i s

begin
sum<=(i n 1 xor ( i n 2 xor c i n ) ) ;
cout <=(i n 1 and i n 2 ) or ( i n 2 and c i n ) or ( c i n and i n 1 ) ;

end B e h a v i o r a l ;

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3.2.2 VHDL Testbench for full adder

LIBRARY i e e e ;
USE i e e e . s t d l o g i c 1 1 6 4 .ALL;
ENTITY f a t b IS
END f a t b ;

ARCHITECTURE b e h a v i o r OF f a t b IS

COMPONENT f a
PORT( i n 1 : IN s t d l o g i c ;
i n 2 : IN s t d l o g i c ;
c i n : IN s t d l o g i c ;
sum : OUT s t d l o g i c ;
c o u t : OUT s t d l o g i c ) ;
END COMPONENT;

signal in1 : s t d l o g i c := ’ 0 ’ ;
signal in2 : s t d l o g i c := ’ 0 ’ ;
signal cin : s t d l o g i c := ’ 0 ’ ;
signal sum : std logic ;
signal cout : std logic ;

BEGIN

uut : f a PORT MAP ( i n 1 => in1 , i n 2 => in2 , c i n => c i n ,

sum => sum , c o u t => c o u t ) ;

s t i m p r o c : process
begin
in1 <= ’0 ’; in2 <= ’0 ’; c i n <= ’0 ’; wait f o r 5 ns ;
in1 <= ’0 ’; in2 <= ’0 ’; c i n <= ’1 ’; wait f o r 5 ns ;
in1 <= ’0 ’; in2 <= ’1 ’; c i n <= ’0 ’; wait f o r 5 ns ;
in1 <= ’0 ’; in2 <= ’1 ’; c i n <= ’1 ’; wait f o r 5 ns ;
in1 <= ’1 ’; in2 <= ’0 ’; c i n <= ’0 ’; wait f o r 5 ns ;
in1 <= ’1 ’; in2 <= ’0 ’; c i n <= ’1 ’; wait f o r 5 ns ;
in1 <= ’1 ’; in2 <= ’1 ’; c i n <= ’0 ’; wait f o r 5 ns ;
in1 <= ’1 ’; in2 <= ’1 ’; c i n <= ’1 ’; wait f o r 5 ns ;
end process ;

END;
The simulation waveform thus obtained is shown is fig. 4.

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 Figure 4: Full adder simulation waveform

3.2.3 VHDL design code for full adder using half adders

l i b r a r y IEEE ;
use IEEE . STD LOGIC 1164 .ALL;

entity f a u s i n g h a i s
Port ( i n 1 f a : in STD LOGIC ;
i n 2 f a : in STD LOGIC ;
c i n : in STD LOGIC ;
sum fa : out STD LOGIC ;
c o u t f a : out STD LOGIC ) ;
end f a u s i n g h a ;

architecture B e h a v i o r a l of f a u s i n g h a i s
component ha
Port ( i n 1 : in STD LOGIC ;
i n 2 : in STD LOGIC ;
sum : out STD LOGIC ;
c o u t : out STD LOGIC ) ;
end component ;
s i g n a l c1 : STD LOGIC ;
s i g n a l c2 : STD LOGIC ;
s i g n a l s 1 : STD LOGIC ;
begin
−− f u l l adder i n t a n t i a t i o n s
−− H a l f adder module ( ha ) has a l r e a d y
−− been d e s i g n e d i n Exp 1 , e a r l i e r .
HA1 : ha port map( i n 1=>i n 1 f a ,
i n 2=>i n 2 f a ,
sum=>s1 ,
c o u t=>c1 ) ;
HA2 : ha port map( i n 1=>c i n ,
i n 2=>s1 ,
sum=>sum fa ,
c o u t=>c2 ) ;

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 c o u t f a <=(c1 or c2 ) ;
end B e h a v i o r a l ;

3.2.4 VHDL Testbench for full adder using half adder

LIBRARY i e e e ;
USE i e e e . s t d l o g i c 1 1 6 4 .ALL;
ENTITY f a u s i n g h a t b IS
END f a u s i n g h a t b ;

ARCHITECTURE b e h a v i o r OF f a u s i n g h a t b IS

COMPONENT f a u s i n g h a
PORT( i n 1 f a : IN s t d l o g i c ;
i n 2 f a : IN s t d l o g i c ;
c i n : IN s t d l o g i c ;
sum fa : OUT s t d l o g i c ;
c o u t f a : OUT s t d l o g i c ) ;
END COMPONENT;

signal i n 1 f a t b : s t d l o g i c := ’ 0 ’ ;
signal i n 2 f a t b : s t d l o g i c := ’ 0 ’ ;
signal c i n t b : s t d l o g i c := ’ 0 ’ ;
signal sum fa tb : s t d l o g i c ;
signal cout fa tb : std logic ;

BEGIN

uut : f a u s i n g h a PORT MAP ( i n 1 f a => i n 1 f a t b ,

i n 2 f a =>i n 2 f a t b ,
c i n => c i n t b ,
sum fa => s u m f a t b ,
c o u t f a => c o u t f a t b ) ;
s t i m p r o c : process
begin
i n 1 f a t b <= ’0 ’; i n 2 f a t b <= ’0 ’; c i n t b <= ’0 ’; wait f o r 5 ns ;
i n 1 f a t b <= ’0 ’; i n 2 f a t b <= ’0 ’; c i n t b <= ’1 ’; wait f o r 5 ns ;
i n 1 f a t b <= ’0 ’; i n 2 f a t b <= ’1 ’; c i n t b <= ’0 ’; wait f o r 5 ns ;
i n 1 f a t b <= ’0 ’; i n 2 f a t b <= ’1 ’; c i n t b <= ’1 ’; wait f o r 5 ns ;
i n 1 f a t b <= ’1 ’; i n 2 f a t b <= ’0 ’; c i n t b <= ’0 ’; wait f o r 5 ns ;
i n 1 f a t b <= ’1 ’; i n 2 f a t b <= ’0 ’; c i n t b <= ’1 ’; wait f o r 5 ns ;
i n 1 f a t b <= ’1 ’; i n 2 f a t b <= ’1 ’; c i n t b <= ’0 ’; wait f o r 5 ns ;
i n 1 f a t b <= ’1 ’; i n 2 f a t b <= ’1 ’; c i n t b <= ’1 ’; wait f o r 5 ns ;
end process ;
END;

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 Figure 5: Full adder using Half Adder simulation waveform

The simulation waveform thus obtained is shown is fig. 5.

3.3 Exp 3: Four Bit Ripple Carry Adder

3.3.1 VHDL design code for 4-bit ripple carry adder using 1-bit full
adders which further uses half-adders

l i b r a r y IEEE ;
use IEEE . STD LOGIC 1164 .ALL;

entity f o u r b i t r i p p l e c a r r y i s
Port ( i n 1 r c : in STD LOGIC VECTOR ( 3 downto 0 ) ;
i n 2 r c : in STD LOGIC VECTOR ( 3 downto 0 ) ;
c i n r c : in STD LOGIC ;
sum rc : out STD LOGIC VECTOR ( 3 downto 0 ) ;
c o u t r c : out STD LOGIC ) ;
end f o u r b i t r i p p l e c a r r y ;

architecture B e h a v i o r a l of f o u r b i t r i p p l e c a r r y i s
component f a u s i n g h a
Port ( i n 1 f a : in STD LOGIC ;
i n 2 f a : in STD LOGIC ;
c i n : in STD LOGIC ;
sum fa : out STD LOGIC ;
c o u t f a : out STD LOGIC ) ;
end component ;

s i g n a l c o u t 1 : STD LOGIC ;
s i g n a l c o u t 2 : STD LOGIC ;
s i g n a l c o u t 3 : STD LOGIC ;

begin

−− f u l l adder i n t a n t i a t i o n s

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−− F u l l adder module u s i n g h a l f adder ( f a u s i n g h a )
−− has a l r e a d y been d e s i g n e d i n Exp 2 , e a r l i e r .

FA1 : f a u s i n g h a port map( i n 1 f a=>i n 1 r c ( 0 ) ,

i n 2 f a=>i n 2 r c ( 0 ) ,
c i n=>c i n r c ,
sum fa=>sum rc ( 0 ) ,
c o u t f a=>c o u t 1 ) ;

FA2 : f a u s i n g h a port map( i n 1 f a=>i n 1 r c ( 1 ) ,

i n 2 f a=>i n 2 r c ( 1 ) ,
c i n=>cout1 ,
sum fa=>sum rc ( 1 ) ,
c o u t f a=>c o u t 2 ) ;

FA3 : f a u s i n g h a port map( i n 1 f a=>i n 1 r c ( 2 ) ,

i n 2 f a=>i n 2 r c ( 2 ) ,
c i n=>cout2 ,
sum fa=>sum rc ( 2 ) ,
c o u t f a=>c o u t 3 ) ;

FA4 : f a u s i n g h a port map( i n 1 f a=>i n 1 r c ( 3 ) ,

i n 2 f a=>i n 2 r c ( 3 ) ,
c i n=>cout3 ,
sum fa=>sum rc ( 3 ) ,
c o u t f a=>c o u t r c ) ;
end B e h a v i o r a l ;

3.3.2 VHDL testbench for 4-bit ripple-carry adder

l i b r a r y IEEE ;
use IEEE . STD LOGIC 1164 .ALL;

entity f o u r b i t r i p p l e c a r r y t b i s
end f o u r b i t r i p p l e c a r r y t b ;

architecture B e h a v i o r a l of f o u r b i t r i p p l e c a r r y t b i s
component f o u r b i t r i p p l e c a r r y
Port ( i n 1 r c : in STD LOGIC VECTOR ( 3 downto 0 ) := ( others => ’ 0 ’ ) ;
i n 2 r c : in STD LOGIC VECTOR ( 3 downto 0 ) := ( others => ’ 0 ’ ) ;
c i n r c : in STD LOGIC := ’ 0 ’ ;
sum rc : out STD LOGIC VECTOR ( 3 downto 0 ) ;
c o u t r c : out STD LOGIC ) ;
end component ;

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 Figure 6: Two Bit ripple carry adder

signal in1 rc tb : s t d l o g i c v e c t o r ( 3 downto 0):= ( others => ’ 0 ’ ) ;

signal in2 rc tb : s t d l o g i c v e c t o r ( 3 downto 0):= ( others => ’ 0 ’ ) ;
signal cin rc tb : s t d l o g i c := ’ 0 ’ ;
signal sum rc tb : s t d l o g i c v e c t o r ( 3 downto 0 ) ;
signal cout rc tb : std logic ;

begin
uut : f o u r b i t r i p p l e c a r r y
PORT MAP ( i n 1 r c => i n 1 r c t b ,
i n 2 r c => i n 2 r c t b ,
c i n r c => c i n r c t b ,
sum rc => s u m r c t b ,
c o u t r c => c o u t r c t b
);

s t i m p r o c : process
begin
i n 1 r c t b <= ” 1101 ” ; in2 rc tb <= ” 1111 ” ; cin rc tb <= ’1 ’; wait f o r 5 ns ;
i n 1 r c t b <= ” 0011 ” ; in2 rc tb <= ” 0111 ” ; cin rc tb <= ’ 0 ’ ; wait f o r 5 ns ;
i n 1 r c t b <= ” 1010 ” ; in2 rc tb <= ” 1011 ” ; cin rc tb <= ’1 ’; wait f o r 5 ns ;
i n 1 r c t b <= ” 0110 ” ; in2 rc tb <= ” 1001 ” ; cin rc tb <= ’1 ’; wait f o r 5 ns ;
end process ;
end B e h a v i o r a l ;
The output waveform thus obtained is shown in fig. 6.

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