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EC-CC-01 END

This document is an examination paper for the Bachelor of Technology in Electronics and Communication Engineering, specifically for the Digital Electronics Circuits subject. It outlines the exam structure, including the number of questions to attempt, marks distribution, and specific topics covered in each question. The exam is designed to assess knowledge in digital electronics concepts, circuit design, and logic minimization.

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fiscal012
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6 views

EC-CC-01 END

This document is an examination paper for the Bachelor of Technology in Electronics and Communication Engineering, specifically for the Digital Electronics Circuits subject. It outlines the exam structure, including the number of questions to attempt, marks distribution, and specific topics covered in each question. The exam is designed to assess knowledge in digital electronics concepts, circuit design, and logic minimization.

Uploaded by

fiscal012
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
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CODE: _____________________________

(To be filled by office)

CONFIDENTIAL
2018
Examination: Bachelor of Technology
Subject: Electronics and Communication Engineering
Part/Semester: 3rd Semester
Paper No.: EC-CC-01
Paper: Digital Electronics Circuits
Time: 2 hrs
FULL MARKS: 50
PASS MARKS: 15

Note: 1. Attempt any five questions.


2. Begin each answer in a new page.
3. Answer parts of a question at a place.
4. Assume reasonable data wherever required.
5. The figures in the right margin indicate full marks for the question.

Marks of
Question
each
Number
question
1 a) 1x5=5
i) Convert 3A9E.B0D16 to binary.
ii) Find 10’s complement of 1056.074.
iii) Given 29210=1204b, find the value of b.
iv)What do you mean by alphanumeric codes?
v) Convert 101010110101 to gray code
b) Convert the following AOI logic circuit to 5
i) NAND logic
ii)NOR logic

2 a) Minimize in SOP and POS forms on the map the 5 variable functions 5
F=∑m(0,1,4,5,6,13,14,15,22,24,25,28,29,30,31)
b) Minimize and implement the following multiple output functions 5
f1=∑m(1,2,3,6,8,12,14,15)
f2=∑M(0,4,9,10,11,14,15)
3 a) Design a full adder using half adder. 5
b) Design a full subtractor using 1:8 MUX. 3

Moderated by:
1.
2.
3. Signature of the Setter
Signature of Chairman of the Board
of Moderation
Date:
c) How parity generator circuit can be deferred from parity checker circuit? 2
4 a) Draw the circuit of CMOS inverter and explain the operation. 5
b) What are the characteristics of ECL gates? 5
5 a)Design Mod-5 synchronous counter using J-K flip flops. 6
b)Convert D flip-flop to a J-K flip-flop. 3
c)What is race around condition? How can we overcome this condition? 1
6 a)With a neat diagram explain the working of SISO mode shift register. 5
b) Design a 32:1 MUX using 8:1 MUX. 5
7 a) Show how the PLA circuit shown in the figure would be programmed to 5
implement the sum and carry output of a full adder

b) Give the comparison between PROM, PLA and PAL. 5


8 Write short notes on any two of the following: 5x2=10
i)Totem pole configuration of TTL logic
ii)Types of ROM’s
iii)Master Slave JK flip-flop
iv)4bit binary to gray converter

Moderated by:
1.
2.
3. Signature of the Setter
Signature of Chairman of the Board
of Moderation
Date:

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