VISVESVARAYA TECHNOLOGICAL UNIVERSITY

BELAGAVI -590018, KARNATAKA

A
MINIPROJECT REPORT
ON
INSTRUCTION SET& SYSTEM DESIGN
BACHELOR OF ENGINEERING IN
ELECTRONICS AND COMMUNICATION ENGINEERING

Submitted by:

NAME: USN:
SUDARSHAN.G 1SJ20EC147

Under the guidance of

Prof. MANJULA K
Assistant Professor
Department of ECE
2021
VISVESVARAYA TECHNOLOGICAL UNIVERSITY
BELAGAVI -590018, KARNATAKA

PROJECT SYNOPSIS
on
“AUTOMATIC WASHING MACHINE”
Submitted in partial fulfilment of the requirement for the award of

BACHELOR OF ENGINEERING
IN
ELECTRONICS AND COMMUNICATION
ENGINEERING

Submitted by

SUDARSHAN.G 1SJ20EC147

Under the guidance of

Prof. MANJULA
Assistant Professor

DEPARTMENT OF ELECTRONICS AND COMMUNICATION

ENGINEERING
S J C INSTITUTE OF TECHNOLOGY
CHICKABALLAPUR – 562101
2021-22
Table of Content

SL NO TITLE PAGE NO
1) Abstract 1
2) Introduction 2
3) Summary 2
4) Specification 3
5) Block Diagram 4
6) Algorithm 4
7) Source code Justification 5
8) Verilog code 6-12
9) Test Bench 13-14
10) Waveforms 15
11) Advantage and Disadvantages 16
12) Conclusion and future scope 16
13) References
17
 ABSTRACT

This mini project proposes to demonstrate the capabilities and

scope of Verilog HDL by implementing the control system of an
automatic washing machine. This mini project accomplishes the
above mentioned objective by implementing the Control System of
an automatic washing using the Finite State Machine model. The
Control System generates the control signals to control the overall
operation of the washing machine.

DEPT. OF ECE, SJCIT 2022-23 Page 1

 INTRODUCTION
 Various real life scenarios can be represented by Finite State Machine like
control system of an automatic washing machine
 Assigning then main stage of the process like Close door,Fill water,Add
detergent, Cycle,Drain and Spin various stages that can be implemented as a
state machine.
 Writing a test bentch to observe the working of the machine
 Using Xilinx ISE 14.7 to implement the control system

SUMMARY
An Automatic Washing Machine controller has the following functionalities:
•The washing machine has the following states:
Check_Door,Fill_Water,Add_Detergent,Drain_Water,Spin
• The controller is composed of two blocks:

A Finite-State Machine (FSM) block and a Timer block. The FSM block receives some
signals from the user, from the timer, and from other hardware parts such as the door
sensor. FSM block output control the timer block and other hardware components of
the washing machine. Table1 identifies the FSM input and output signals and their
functionality. The timer block generates the correct time periods required for each
cycle after it has been reset. The timer block is composed of an up- counter and
combinational logic to give the correct time signals once certain count values have
been achieved. The timer values will be determined by the clock frequency being
used in the system.

DEPT. OF ECE, SJCIT 2022-23 Page 2

 SPECIFICATION
Table 1: Alphabetical listing of input and output signals for the FSM

Signal Name Direction Purpose

Clock input Clock, positive edge triggered.

Reset input Reset, synchronous and active high.

Start Input
Should generate a pulse; 1 = start washing process; 0 = don't start.
This start should be used to generate a pulse to trigger an internal
flag register.
Door_close Input
Used to see if the door is closed;
Door_close = 0; Machine stops (in any state). Door_close = 1;
Machine resumes/starts.

Filled Input From some sensor; Filled = 1 means water filled OK.

Drained Input From some sensor; Drained = 1 means drained OK.

Added Input From user; Added = 1 means detergent added OK.

Cycle_Timeout Input
From timer; Cycle_Timeout = 1 means time finished go to next state
Spin_Timeout Input
From timer; Spin_Timeout = 1 means time finished go to next state
Motor_on output Motor_on = 1; drive the motor. Motor_on = 0; motor off, not
driven.

Fill_Valve_on output Fill_valve_on = 1; valve open& filling will proceed. Fill_valve_on = 0;

valve closed & filling stops.
Drain_valve_on output
Drain_valve_on = 1; drain valve open & draining in progress.
Drain_valve_on = 0; drain valve closed and draining stopped.
Door_lock output
To lock the door (some mechanism)
Door_lock = 1 when the machine has started Door_lock = 0 when
the machine has done washing The essential condition for the
Door_lock is that there must be no Water inside the machine. That
is, Door_lock can only be 0 when Draining has been finished.

Done output Done = 1 when draining has been finished and washing has been
finished. This should also deassert Door_lock.

DEPT. OF ECE, SJCIT 2022-23 Page 3

 STATE DIAGRAM:

ALGORITHM

DEPT. OF ECE, SJCIT 2022-23 Page 4

 Source Code Justification
In the design of the source code, it was chosen that a case statement be the
preference for the design. A FSM-structure was chosen for the design. It
was chosen that based on the amount of states, a 3 bit signal would be
enough to represent the state. There were a total of 6 states in our design.
There is 1 “off” state for when the power is off, 1 “Check_Door” state for
when the machine is not running, or incrementing, and 6 states for the
washing machine. We originally wanted to add two scenarios that we
could handle, which are if the machine asynchronously loses power, or if
the door asynchronously opens. We were successful in implementing both
signals in simulation. Then After the Check_Door State there is Fill_Water
state which checks that the water is filled in the drum .After that there is
Add_Detergent state which checks if the detergent has been added .After it
the Cycle stage is there which accomplishes the washing cycle ,After that
Drain _Water stage has been encountered which checks if the water has
been draind out or not and finally there is Spin stage and when the process
has been completed the process is Finally Done and each stage has been
changed after the encounter of the positive pulse of the clock only .

DEPT. OF ECE, SJCIT 2022-23 Page 5

 VERILOG CODE
Module Automatic_Washing_Machine(Clock,Reset,Door_Close,start,
Filld,Detergent_Added,Cycle_Timeout,drained,Spin_Timeout,
door_lock,motor_on,Fill_valve_on,Drain_valve_on,done,soap_wash,water_wash);
Input Clock,Reset,Door_Close,start,Filld,Detergent_Added,
Cycle_Timeout,drained,Spin_Timeout;
output reg door_lock,motor_on,Fill_valve_on,Drain_valve_on,Done,
Soap_wash,Water_wash;
parameter Check_Door=3'b000;
parameter Fill_Water=3'b001;
parameter Add_Detergent=3'b010;
parameter Cycle=3'b011;
parameter Drain_Water=3'b100;
parameter Spin=3'b101;
reg[2:0] Current_State,Next_State;
always@(Current_State or Start or Door_Close or Filled or Drained or Detergent_Added
or Cycle_Timeout or Spin_Timeout)
begin
case(Current_State)
Check_Door:
if(Start==1 && Door_Close==1)
begin
Next_State=Fill_Water;
Motor_on=0;
Fill_valve_on=0;
Drain_valve_on=0;
Door_Lock=1;

DEPT. OF ECE, SJCIT 2022-23 Page 6

 Soap_wash=0;
Water_wash=0;
Done=0;
end
else
begin
Next_State=Current_State;
Motor_on=0;
Fill_valve_on=0;
Drain_valve_on=0;
Door_Lock=0;
Soap_wash=0;
Water_wash=0;
Done=0;
End
Fill_Water:
if(Filled==1)
begin
if(soap_wash==0)
begin
Next_State=Add_Detergent; Motor_on=0;
Fill_valve_on=0;
Drain_valve_on=0;
Door_Lock=1;
Soap_wash=1;
Water_wash=0;
Done=0;
end

DEPT. OF ECE, SJCIT 2022-23 Page 7

 else
begin
Next_State=Cycle;
Motor_on=0;
Fill_valve_on=0;
Drain_valve_on=0;
Door_Lock=1;
Soap_wash=1;
Water_wash=1;
Done=0;
end
else
begin
Next_State=Current_state;
Motor_on=0;
Fill_valve_on=1;
Drain_valve_on=0;
Door_Lock=1;
Done=0;
end
Add_Detergent:
If(Detergent_Added==1)
begin
Next_State=Cycle;
Motor_on=0;
Fill_valve_on=0;
Drained_valve_on=0;
Door_Lock=1;

DEPT. OF ECE, SJCIT 2022-23 Page 8

 Soap_wash=1;
Done=0;
end
else
begin
Next_State=current_state;
Motor_on=0;
Fill_valve_on=0;
Drain_valve_on=0;
Door_Lock=1;
Soap_wash=1;
Water_wash=0;
Done=0;
end
Cycle:
If(Cycle_timeout==1)
begin
Next_State=Drain_Water;
Motor_on=0;
Fill_valve_on=0;
Drain_valve_on=0;
Door_Lock=1;
//Soap_wash=1;
Done=0;
end
Else
begin
Next_State=Current_state;
Motor_on=1;

DEPT. OF ECE, SJCIT 2022-23 Page 9

 Fill_valve_on=0;
Drain_valve_on=0;
Door_Lock=1;
//Soap_wash=1;
Done=0;
end
Drain_Water:
if(Drained==1)
begin
If(Water_wash==0)
begin
Next_State=Fill_water;
Motor_on=0;
Fill_valve_on=0;
Drain_valve_on=0;
Door_Lock=1;
Soap_wash=1;
//Water_wash=1;
Done=0;
End
else
begin
Next_State=Spin;
Motor_on=0;
Fill_valve_on=0;
Drain_valve_on=0;
Door_Lock=1;
Soap_wash=1;
Water_wash=1;

DEPT. OF ECE, SJCIT 2022-23 Page 10

 Done=0;
end
else
begin
Next_State=Current_State;
Motor_on=0;
Fill_valve_on=0;
Drain_valve_on=1;
Door_Lock=1;
Soap_wash=1;
//Water_wash=1;
Done=0;
End
Spin:
if(Spin_Timeout==1)
begin
Next_State=Door_close;
Motor_on=0;
Fill_valve_on=0;
Drain_valve_on=0;
Door_Lock=1;
Soap_wash=1;
Water_wash=1;
Done=1;
end
else
begin
Next_State=Current_State; Motor_on=0;

DEPT. OF ECE, SJCIT 2022-23 Page 11

 Fill_valve_on=0;
Drain_valve_on=1;
Door_Lock=1;
Soap-wash=1;
Water_wash=1;
Done=0;
end
default:
Next_State=Check_Door;
endcase
end
always@(posedge Clock or negedge Reset)
begin
if (Reset)
Current_State<=3’b000;
end
else
begin
Current_State<=Next_State;
end
end
endmodul

DEPT. OF ECE, SJCIT 2022-23 Page 12

 TEST BENCH
module Automatic_Washing_Machine_Test_Bench;
Reg Clock,Reset,Door_Close,Start,Filled,Detergent_Added,Drained
Cycle_Timeout,Spin_Timeout;
Wire Door_lock,Motor_on,Fill_valve_on,Drain_valve_on,Done,
Soap_wash,Water_wash;
Automatic_Washing_Machine Customer1(Clock,Reset,Door_Close,
Start,Filled,Detergent_Added,Cycle_Timeout,Drained,Spin_Timeout,
Door_lock,Motor_on,Fill_valve_on,Drain_valve_on,Done,Soap_wash,
Water_wash);
Initial
begin
Clock=0;
Reset=1;
Start=0;
Door_Close=0;
Filled=0;
Drained=0;
Detergent_Added=0;
Cycle_Timeout=0;
Spine_timeout=0;
#5 Reset=0;
#5 Start=1;
Door_Close=1;
#10 Filled=1;
#10 Detergent_added=1;
//filled=0;
#10 Cycle_Timeout=1;

DEPT. OF ECE, SJCIT 2022-23 Page 13

 //Detergent_Added=0;
#10 Drained=1;
//Cycle_Timeout=0;
#10 Spin_Timeout=1;
//Drained=0;
/*
#0 reset = 0;
#2 start = 1;
#4 door_close = 1;
#3 filled = 1;
#3 detergent_added = 1;
#2 cycle_timeout = 1;
#2 drained = 1;
#3 spin_timeout = 1;
*/
End
always
begin
#5 Clock = ~Clock;
end
initial
begin
$monitor("Time=%d, Clock=%b, Reset=%b, start=%b, door_close=
%b, filled=%b, detergent_added=%b, cycle_timeout=%b, drained=
%b, spin_timeout=%b, door_lock=%b, motor_on=%b, fill_valve_on=
%b, drain_valve_on=%b, soap_wash=%b, water_wash=%b, done=
%b",$time, clk, reset, start, door_close, filled, detergent_added,
cycle_timeout, drained, spin_timeout, door_lock, motor_on,
fill_value_on, drain_value_on, soap_wash, water_wash, done);
end
endmodule
DEPT. OF ECE, SJCIT 2022-23 Page 14
 Waveform

Transcript Window Result

DEPT. OF ECE, SJCIT 2022-23 Page 15

 Advantages
 Automatic washing machines save time, water and power
 Automatic washing machines are less labor-intensive than hand
washing clothes
 Automatic washing machines reduce the issue of clothes from
getting wrinkled or dirty in storage
 Automatic washing machines are helpful for people with allergies,
as they can wash clothes in a way that will not agitate them
 Automatic washing machines can be programmed to specific
temperatures and cycles best suited for different fabric and clothing
item
Disadvantages
 More expensive.
 Can have longer wash cycles.
 Heavier than top load models.
 Takes up more space than a top load machine.
 Needs to be fixed in one place – cannot be moved around easily once
installed.
 Takes small loading capacities.

Conclusion & Future Scope

 In this project automatic washing machine has been implemented on Verilog HDL
using Xilinx ISE
 The current project can be implemented on FPGA to demonstrate the code with
Hardware
 The project is based on Finite state machine (FSM) various other projects based on
FSM can be implemented using the current project code as the basis
 More functionality may be included like different modes to wash the clothes
based on the clothing, material temperature etc

DEPT. OF ECE, SJCIT 2022-23 Page 16

 References
[1]Chen Xizhen, Chen Guangjian, JiaJinling,Yuhan,ZhouTianpeng,
”Design of Automatic Washing Machine Based on Verilog HDL”
International Conference on Electronics and Optoelectronics,
29-31 July 2011, pp 38-40.
[2] P. Usha, C H .Karuna, “An Efficient Implementation of
Automatic Washing Machine Control System using Verilog”,
IJSET, volume 2,
issue 7, Sep-Oct 2014, pp 1575-1578.
[3] Thomas & Moorby, the Hardware Verilog Description
Language [M], Beijing tsinghua university press, 2001. 23‐36.
[4] YangJimin YangJiBing, digital system design and Verilog HDL
[M], Beijing: electronic industry press, 2003,
23(11):43‐45.
[5] YuanJunQuan, SunMinQi, CaoRui. Verilog HDL digital system
design and its application [M], concrete: Xian University
of electronic science and technology press, 2002 .

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