Multiple Choice Questions (MCQs)

2. The 8086 has two hardware interrupt

pins i.e. NMI and INTR. NMI is a non maskable segment: offset format.

interrupt and INTR is a maskable interrupt having lower When an interrupt is issued, the processor

automatically

priority. One more interrupt P in associated in INTA transfer the current flags. The code segment

CS and the

called interrupt acknowledge. instruction pointer EIP (or IP in 16 bit mode) on to the

stack. The interrupt number is internally multiplied by

99. What will be the contents of register AL after

four and then provides the offset in the segment 00H

the following has been executed

where the interrupt vector for handling the interrupt is

MOV BL, 8C

located. The processor then loads EIP and CS with the

MOV AL, 7E

values in the table. That way CS:EIP of the interrupt

ADD AL, BL

vector gives the entry point of the interrupt handler. The

(a) 0A

return to the original program that launched the (b) 0A and carry flag is set interrupt occurs

with an IRET instruction. (c) 6A and the carry flag is set

102. The ALU of a microprocessor performs (d) 6A and the carry flag is reset

81. If 8255 A chip is selected when A to A pins are microprocessor. These interrupts are either

edge-
 Multiple Choice Questions (MCQs)

27

1, what is the address of port C? triggered or level-triggered, so they can be disabled

(a) FC (b) FD INTR, RST 7.5, RST 6.5, RST 5.5 are maskable (c) FB (d) FE interrupts in

8085 microprocessor and TRAP is a non-

260. Pseudo instructions are basically-

Ans. (d) : In 8085 microprocessor, assume that the

(a) False instructions

stack pointer is pointer to the memory location 2000H (b) Instructions that are ignored by micro

and register DE contains value 1050H. After the processor

execution of instruction PUSH D, the stack pointer (c) Assembler directives

register is decrement by 2 from memory location and (d) Instructions that are treated like comments

8086. It is a single pin, non-

bidirectional. Hence can transfer in both direction.

maskable, hardware interrupt which can't be disabled.

5. In 8085 micro processor, data bus and address

bus are multiplexed in order to 10. In 8086 the overflow flag is set when

(A) Increase the speed of microprocessor (a) Signed numbers go out of their range after an

(B) Reduce the number of pins arithmetic operation

(C) Connect more peripheral chips (b) Carry and sign flags are set

Which of the above statements is/are correct? (c) During subtraction

(a) (B) only (b) (B) and (C) only (d) The sum is more than 16 bits (c) (A), (B) and (C) (d) (A)

only RPSC ACF & FRO 23.02.2021

60. A memory system of 64 Kbytes needs to be 64. Memory chips of four different sizes as below
 Multiple Choice Questions (MCQs)

designed with RAM chips of 1 Kbyte each, and are available:

a decoder tree constructed with 2:4 decoder 1. 32 K × 4 2. 32K×16

chips with "Enable" input. What is the total 3. 8 K × 8 4. 16 K ×4

number of decoder chips? All the memory chips as mentioned in the

(a) 21 (b) 64 above list are read/write memory. What (c) 32 (d) 25 minimum combination of

chips or chip alone

43. Which of the interrupts of 8085 microprocessor used for small systems.

has highest priority? ? Memory-mapped I/Os share the memory space with

(a) INTR (b) TRAP

external memory. So total addressed capacity is (c) RST 7.5 (d) RST 5.5 memory connected

only.

160. ??????? data transmission is more useful when

pair.

sending information for long distances

addressing mode direct Immediate

T-stable 13 10 (a) Serial (b) Parallel

Machine cycle 4 3 (c) Either (d) Neither

156. The total size and the total number of BSNL TTA (JE) 25.09.2016, Shift-I

Interrupts procedures that can be defined in Ans. (a) : The serial data transmission mode is a mode

this memory of 8086 is in which the data bits are sent serially one after the

(a) 256 Bytes, 256 Procedures

other at a time over the transmission channel. It needs a (b) 1K Bytes, 256 Procedures

single transmission line for communication. In serial (c) 256 Bytes, 1K Procedures
 Multiple Choice Questions (MCQs)

data transmission the system takes several clock cycles (d) 1K Bytes, 1K Procedures

106. Which one of the following is the software 1

1 byte can be transferred in second

interrupt of 8085 microprocessor? rN

(a) RST 7.5 (b) RST 7 b (c) TRAP (d) INTR b bytes can be transferred in second

3. Data transfer is 3. Data transfer is between data transfer in between input and output devices

I/O

between any register accumulator and I/O status check and I/O interrupt data transfer

method

and I/O device. devices. reliable low speed process because in execution of

192. A stack is normally send in digital computers every instruction, more time is needed.

to store the return address at the time of a 198. The length of a bus cycle in 8086/8088 is four

subroutine call because: clock cycles, T , T , T , T and an

1234

(a) Stack are nonvolatile memories indeterminate number of wait state clock cycles (b) Stacks

have large capacity denoted by T . The wait states are always

w (c) Information in a stack cannot be altered by inserted between.

other instructions (a) T1 and T2 (b) T2 and T3 (d) Stack peBrmSNit Lea TsyT nAe s(JtiEng) 2o7f

.s0u9b.2ro0u1t6in, e1 0 AM (c) T3 and T4 (d) T4 and T1 ESE-2001

313. Which device convert a decimal input number 316. If the memory chip size is 1024 ×4, the

number

to binary? of memory chips required to design 8K

 Multiple Choice Questions (MCQs)

(a) Accumulator memory is (b) Encoder (a) 8 (b) 256 (c) ALU (c) 16 (d) 32

319. In 8085, instruction ADD IMMEDIATE to

? Zero flag (Z) ACCUMULATOR WITH CARRY is

? Auxiliary carry flag (AC) represented by the opcode-

? Parity flag (P) (a) ADC (b) ACI

? Carry flag (CY) (c) ADD (d) ADI

? Overflow flag (0) BSNL TTA 27.09.2016, 3 PM

(b) Control flag- The control flags enable or disable Ans : (b) In 8085, instruction ADD

immediate to

certain operations of the microprocessor. accumulator with carry is represented by the opcode

The 3 control flags are- ACI which mean 8-bit data and the carry flag are added

? Directional flag (D) to the contents of the accumulator and the result is

? Interrupt flag (I) stored in the accumulator.

? Trap flag (T) Example ? ACI 55H

Electronics-II 906 YCT

3. An operational amplifier has a differential gain

IX. Operational Amplifier

of 100 and a common mode gain of 0.10. Its

CMRR will be

1. An ideal Op-amp has which of the following (a) 20 dB (b) 40 dB

characteristics? (c) 60 dB (d) 80 dB

(a) R = ? A = ? R = 0 NSCL Diploma Trainee 24.02.2021

i v 0 UKPSC JE 2013, PAPER-I (b) Ri = 0 Av = ? R0 = 0 BSNL TTA (JE) 14.07.2013 (c) R = ?

 Multiple Choice Questions (MCQs)

A=? R = ? RSEB JE 2013

i v 0 (d) R = 0 A = ? R =? A

168. I/O mapped system identify their input/output require 5 × 7 × 64 = 2240 bits.

devices by giving them an

172. The pin configuration of 8086 is available in

(a) 8 bit port number

the___ (b) 16 bit port number (c) 8 bit buffer number (a) 40 pin (b) 50 pin (d) 16 bit buffer

number (c) 30 pin (d) 20 pin

128. An output device is interfaced with an 8085

microprocessor as memory-mapped I/O. The

address of the device is 1000H. In order to output

data from the accumulator to the device, what

will be the sequence of instructions?

(a) LXIH, 1000H MOV A, M ?(3FFF)16 =(16383)10 (b) LXI H, 1000H MOV M, A 133. The

TIMER of PPI 8155 is of (c) LHLD 1000H MOV A, M (a) 16 bits (b) 14 bits (d) LHLD 1000H

MOV M, A (c) 12 bits (d) 8 bits

252. The??. is set (to 1) if there is a carry from the with registers pair.

low nibble (lowest four bits) to the high nibble 257. In an 8085 µP system, the RST instruction will

(upper four bits), or borrow from the high nibble- cause an interrupt-

(a) Carry flag (b) Auxiliary carry flag (a) Only if an interrupt service routine is not (c) Sign flag
 Multiple Choice Questions (MCQs)

(d) Parity flag being executed

1. Mode 0- Interrupt on terminal count 1

2. Mode 1- Hardware retriggerable one shot M1 = Available capacity

3. Mode 2- Rate generator M2 = Memory to be designed

4. Mode 3- Square wave generator 1024×8bit

n= =8

5. Mode 4- Software triggered strobe 256×4bit

6. Mode 5- Hardware triggered strobe

179. Intel 8085 is an____MPU:

174. Microprocessor 8085 can address location up (a) 8 bit NMOS (b) 8 bit CMOS

to (c) 8 bit PMOS (d) 8 bit HMOS

(a) 32K (b) 128K

BSNL TTA (JE) 27.09.2016, 10 AM (c) 64K (d) 1M

131. Instruction CALL of a 8085 microprocessor has

136. The program counter in a 8085 microprocessor

(a) 1 byte (b) 2 bytes is a 16-bit register, because (c) 4 bytes (d) 3 bytes (a) It counts 16 bits at

a time

217. ALU of an 8085 MPU consists of

achieve separation of address from data. (a) Accumulator, temporary register, arithmetic

212. Which section of the CPU affects and and logical circuit

sequences all events within the CPU and the (b) Accumulator, arithmetic, logical circuit, and

entire microcomputer? five flags

(a) Registers (c) Accumulator, temporary register, arithmetic, (b) ALU logical circuit, five flags
 Multiple Choice Questions (MCQs)

(c) Instruction decoding circuitry (d) None of these

20. Ans. (b) Synchronous DRAM :- Synchronous dynamic

186. The Programmable interrupt controller is

RAM is a memory which synchronized with watch

required to:

which is suitable for microprocessor. SDRAM speed is

(a) handle one interrupt request

measured in MHz rather than nano second. (b) handle one or more interrupt request at a time

Electronics-II 891 YCT

191. In 8085 microprocessor with memory mapped Ans. : (a) Address bus is unidirectional because

data

I/O, which one of the following is correct? flow in one direction, from microprocessor to memory

(a) I/O devices have 16 bit addresses or from microprocessor input/output device. Address

(b) I/O devices are accessed during In and Out bus carries address only.

instructions 196. The 8085 is an enhancement of the popular (c) There can be a maximum of 256

input and INTEL ______ microprocessor:

256 output devices (a) 8080 (b) 8155 (d) Logic operation cannot be performed (c) 8355 (d)

8086

299. Which one of the following 8085 assembly Subtraction (iii) OR, NOT, AND, XOR etc (iv)

Shift the

language instructions does not affect the information 1 bit right or left (v) Comparison.

contents of the accumulator? 304. Intel 8086 is a_______ bit microprocessor

 Multiple Choice Questions (MCQs)

(a) CMA (b) CMP B (a) 8 (b) 12 (c) DAA (d) ADD B (c) 16 (d) 32

48. An RRC instruction in 8085 will affect which

Mizoram PSC IOF 2019, Paper-III

flag?

BSNL TTA 21.02.2016

(a) CY (b) Z

BSNL TTA 28.09.2016, 10 AM (c) S (d) AC

296. The instruction that does not clear the Ans. (d) : In microprocessor there are two types

code.

accumulator of 8085 is - (a) OP code? It is a part of instruction that tells the

(a) XRA A (b) ANI 00H processor what should be done. (c) MVI A, 00H (d) None of these (b)

Operand? It is a part of instruction that contains the

244. Which of the following is a 16-bit register for Ans. (c) There are three types of buses-

8085 microprocessor (i) Address bus -: It is a group of conducting wires

(a) Stack pointer (b) Accumulator which carries address only. It is unidirectional because (c)

Register B (d) Register C data flow in one direction, from microprocessor to

23. Which of the following 8085 assembly language

28. 8086 microprocessor is designed to have ____

instructions does not affect the contents of the

data lines and _____ address line.

accumulator?

(a) 12; 16 (b) 16; 20

 Multiple Choice Questions (MCQs)

(a) CMA (b) CMPB (c) 16; 16 (d) 20; 16

121. Program counter (PC) register is an integral Mizoram PSC Nov. 2015, Paper-III

part of : BSNL TTA (JE) 14.07.2013

(a) Hard Disk (b) RAM

Ans. (c) In microprocessor architecture, flag indicates the

(c) Cache memory (d) CPU

46. An interrupt in which the external device

supplies its address as well as the interrupt

request is known as

(a) Vectored interrupt (b) Maskable interrupt 51. Which one of the following statement about

(c) Non-Maskable interrupt RAM is NOT correct? (d) Designated interrupt (a) RAM stands for

random-access memory

34. _______ are used to detect the occurrence of

on or off respectively.

external events. It is a retentive type of

39. In microprocessor, Stack pointer is a register

instruction and can be reset to zero using the

which comes into use whenever:

reset (RES) instruction.

(a) A data is written into the memory.

(a) Bit instructions (b) The output variable is sent out of the CPU.

(b) Base instructions (c) A data is read from the memory.

 Multiple Choice Questions (MCQs)

(c) Call instructions (d) An interrupt or high priority call comes from

3. Opcode is decode.

BSNL TTA (JE) 27.09.2016, 10 AM

190. SD RAM refers to:

Ans. (b) Five memory chips each size = 16×4

(a) Static DRAM (b) Synchronous DRAM

Here, data bus = 16 and address bus = 20 (because 5 × (c) Semi DRAM (d) All of these

245. The 8th bit of program status word (PSW) of 249. In 8085 microprocessor, the first machine

cycle

8086 microprocessor represents which of the of every instruction is:

following flags? (a) I/O Read Cycle

(a) Overflow flag (b) Direction flag (b) Memory Write Cycle (c) Interrupt enable flag (d) Trap flag

(c) Opcode Fetch Cycle

37. An intel 8085 processor is executing the 41. Which one of the following is not correct for

program given below. The number of times the the AAA instruction in 8086 microprocessors ?

(a) It works only on the AL register.

loop executed is (b) It updates AF and CF.

MVI A, 20H (c) It checks the result for correct unpacked BCD.

MVI B, 10H (d) It updates all the flags.

88. A handshake signal in a data transfer is the response of the computer to the uses.

Read/write
 Multiple Choice Questions (MCQs)

transmitted memory is volatile.

(a) Along with the data bits Read/write memory also known as random access (b) Before the

data transfer memory. (c) After the data transfer The flip-flops in a register are connected in

series. (d) Either along with the bits or after the data 93. In microprocessor 8085, LDA 2000H

is

270. At the output, the content of A is:

BSNL TTA 26.09.2016, 3 PM

UJVNL JE 2016 MOVA,#33H

Ans : (a) The 8085 MPU requires a power supply of ORL A,#01H

+5V single and clock frequency is 3 MHz. 8085 has 8 ANL A,#10H

bit data bus and 16 bit address bus. It has capable of (a) 0001 0000 (b) 0011 0010

addressing 64 kB of memory. It has 40-pin IC uses +5V (c) 0011 1011 (d) 0011 0011

for power. MPPEB Sub. Engineer 0.8.07.2017 Shift-I

Electronics-II 900 YCT

Ans. (a) : Ans : (d) The range of address where the interrupt

service procedures are stored is (00000?003FF ).

Interrupts can be classified into different categories

have different parameters.

(i) Hardware and software interrupts.

(ii) Vector and non-vector interrupts.

There are 8 software and vector interrupts RST 0, RST

 Multiple Choice Questions (MCQs)

1, RST 2, RST 3, RST 4, RST 5, RST 6, RST 7, &

Hardware interrupts- TRAP (RST 4.5), RST 5.5, RST

6.5, RST 7.5, INTR.

276. For CALL or For JUMP is to branch if

program area is outside ......... segment in 8086.

(a) 4K Byte (b) 16K Byte (c) 32K Byte (d) 64K Byte

167. As compared to 16 bit microprocessors. 8 bit

microprocessors are limited in-

(a) Speed So, RST 6 Instruction = CALL 0030H (b) Data handling capability 171. In a 5 × 7 dot

matrix format (c) Directly addressable memory (a) 64 bits are required to store 64 alphanumeric

(d) All of the above

300. A microprocessor has 24 address lines and 32 became Intel's most successful line of

processors.

data lines. If it uses 10 bits of op-code, the size 305. A microprocessor, on arrival of RESET signal

of its Memory Buffer Register is - returns from HALT state to ________

(a) 22 bits (b) 24 bits (a) fetch state (b) execute state (c) 32 bits (d) 14 bits (c) interrupt

state (d) none of these

303. Adder circuits are widely used in the

?JM?3byte ____section of a microprocessor.

(a) input device (b) memory

P??JPE? 3byte (c) control unit (d) ALU

45. What are the sets of commands in a program event counter, a square wave generator etc.
 Multiple Choice Questions (MCQs)

which are not translated into machine 50. Which of the following is a two byte instruction

instructions during assembly process, called? is 8085 microprocessor?

(a) Mnemonics (b) Directives (a) MOV (b) CMA (c) Identifiers (d) Operands (c) ADD (d) MVI

154. Which one of the following statements is not

would be 4 for (I) and 3 for (II).

correct?

151. The logic circuit used to generate the active low

(a) CMPA is a single byte instruction and CMA

()

chip select signal CS by in Intel 8085 is not an instruction (b) The instruction SUB a sets the

zero flag

microprocessor to address to address a (c) Bus is a group of wires

peripheral is shown in figure. The peripheral (d) Instruction INR does not affect carry flag

229. A microprocessor with a 12 bit address bus will

Ans. (c) : A program written in an assembly language

be able to access???????

for a particular machine can be processed only on that

(a) 0.4 kbytes memory (b) 8 kbytes memory

machine and not on any other. (c) 4 kbytes memory (d) 1 kbytes memory

4. Initialized with operational command words

Ans. (b) I/O processor control the flow of information

 Multiple Choice Questions (MCQs)

(OCW's)

between main memory and I/O devices for controlling

of data transfer , microprocessor generate control signal Which are the above statements are

correct?

From which read and write operation is done on (a) 1 and 2 (b) 2 and 3

microprocessor. (c) 3 and 4 (d) 1,2,3 and 4

ESE-2011

201. Choose the incorrect statement. During DMA

transfer, the processor Ans. (a) : The 8259 A interrupt controller can-

(a) Continues its normal operations (cid:1) Manage eight interrupt according to instructions (b)

Suspends its normal operations written into its control registers. (c) Needs to initiate read (write)

command (cid:1) Vector an interrupt request anywhere in the memory (d) Needs to check if the

I/O device is ready for map. However, all light interrupts are spaced at

272. At the beginning of a fetch cycle, the contents

278. Consider the symbol shown below.

of the program counter are

(a) incremented by one (b) transferred to address bus (c) transferred to memory address register

What function does the above symbol represent (d) transferred to memory data register

297. Effective address is calculated by adding or 301. The following is not true for RS 232

standard:

subtracting displacement value to - (a) It establishes the way data is coded

(a) immediate address (b) relative address (b) If defines signal voltage levels (c) absolute
 Multiple Choice Questions (MCQs)

address (d) base address (c) Does not decide data transmission rate

75. Suppose 64 kB, ROM ICs are available in

70. For 8085 microprocessor, the instruction RST6

abundance. 1 MB ROM can be obtained from

restarts subroutine at address (a) 16 ICs in a row

(a) 00H (b) 03H (b) 16 ICs in a column (c) 30H (d) 33H (c) 8 ICs in a column and 2 ICs in a

row

189. The correct sequence of steps to perform

"Fetch" operation in microprocessor is:

1. Opcode is decode

2. Places the address of first byte of instruction on

the address bus

3. Gets opcode on the data bus

(a) 1, 2, 3 (b) 3, 1 (c) 2, 1 (d) 2, 3, 1

11. Which of the following instructions is a 3-byte 17. How many Initialization command words are

instruction? essential if 8259 is used in single chip with

(a) LDA XB (b) MOV A, M special fully nested mode configuration? (c) JMP 2050 (d) MVIA (a)

2 (b) 3

253. In a 8085 microprocessor system with memory

mapped I/O, which of the following is true? Ans : (c) In 8085 microprocessor, the RST instruction

(a) Devices have 8-bit address line will cause an interrupt only if interrupts have been (b)

Devices are accessed using IN and OUT enabled by an EI instruction.

 Multiple Choice Questions (MCQs)

instructions 258. The operations executed by two or more (c) There can be maximum of 256

input devices control units are referred as

and 256 output devices (a) Micro-operations (d) Arithmetic and logic operations can be (b)

Macro-operations

242. "Cycle steal" operation is with

MOV CX, 1122H (a) DMA controller

ADD AX, CX (b) Interrupt controller

B B 1 1 H (c) Keyboard display controller

(d) Microcontroller

+1122H

BSNL TTA 28.09.2016, 3 PM

CC33H

Ans. (a) In cycle stealing Direct Memory Access

HLT (DMA) transfer, the DMA controller requests only one

The result of this program is AX = CC33H. or two memory cycles from the CPU at a time. If the

CPU is trying to access memory that time, it will wait

238. For which of the following devices, is DMA the

otherwise CPU can continue with its internal operation

most suitable-

that does not require access to the memory bus. So CPU

(a) Hard disk (b) Key board and DMA cycles can be overlapped. Cycle stealing (c) Mouse (d)

Joy stick mode is not suitable for large block transfers since the

111. Features of solid state drives (SSDs) are

1. High performance in input/output operations

 Multiple Choice Questions (MCQs)

per second

2. More power consumption than comparable

size HDDs

3. Lower access times and latency rates

4. More susceptible to physical shock and

Hence, Auxiliary carry (AC) = 1

vibration

Parity (even) (P) = 1

(a) 2 and 3 only (b) 2 and 4 only (c) 1 and 3 only (d) 1 and 4 only 116. Which one of the

following is the correct

180. A device or a peripheral equipment which is

= 64K not is direct communication with CPU of a

175. The smallest valid signed integer that can be computer is called

(a) off line device (b) on line device

stored in a memory location of a 4K × 8 bit (c) active device (d) slow device

224. The order of priority for interrupts in 8085

processing with memory. MPU is

(d) Data processing with registers takes fewer (a) RST 7.5, RST 6.5, RST 5.5, TRAP

cycles than that with memory. (b) TRAP, RST 7.5, RST 6.5, RST 5.5

ESE-2011, 2005 (c) RST 5.5, RST 6.5, RST 7.5, TRAP

Ans. (d) : Data processing with registers takes fewer (d) TRAP, RST 5.5, RST 6.5, RST 7.5

cycle than with memory which require extra memory UPRVUNL JE 21.10.2021, 9AM-12PM

read or write signal. MPPKVVCL (Jabalpur) JE 2018

 Multiple Choice Questions (MCQs)

So, a good assembly language programmer should uses BSNL TTA 28.09.2016, 10 AM

a GPRs rather than memory. BSNL TTA 28.09.2016, 3 PM

219. After completing the execution, the ESE- 2010

microprocessor returns to Ans. (b) : The order of priority for interrupts in 8085

(a) Halt state (b) Fetch state MPU is TRAP, RST 7.5, RST 6.5, RST 5.5 and INTR. (c) Execute

state (d) Interrupt state Each of these can be programmed. TRAP has the

177. Direct memory access channel (DMA)

facilitates data to move in and out of the system

(a) on first-come first serve basis (b) with equal time delay (c) without a sub-routine (d) without

program intervention

147. Which value a program counter will have when

UKPSC JE 2013, PAPER-I

non maskable interrupt of 8085 microprocessor

Ans. (d) : TRAP ? non maskable interrupt

is serviced?

RST ? 7.5 ? maskable interrupt

(a) 0004H (b) 0014H

RST ? 6.5 ? maskable interrupt (c) 0024H (d) 0034H

247. The register which holds the information about

input device or memory control unit controls the the nature of results of arithmetic or logic

instructions and flow of data within the computer and operations is called as
 Multiple Choice Questions (MCQs)

register array consists of registers identified by letters (a) Accumulator

like B, C, D, E, H, L and accumulator. (b) Condition code register

Block diagram of a Microcomputer- (c) Flag register

(d) Process status registers

ESE-2012

Ans. (c) : The flags generally reflect the status of

arithmetic or logic operation.

248. The address bus of 8085 MPU is-

(a) Multi directional (b) Bi-directional (c) Unidirectional (d) None of these

165. Debug is synonymous to ???????????

(a) Erase (b) exponent Ans. : (b) If a microprocessor is called 'n-bit (c) trouble shoot (d)

emulate microprocessor' then n refers to size to internal data bus.

42. A 512MB RAM is connected to a 47. Memory-mapped I/O-scheme for the allocation

microprocessor with data bus length of 8. The of address to memories and I/O devices, is used

size of memory that will remain unutilized is: for

(a) 256 MB (b) 128 MB (a) small systems (c) Zero (d) 192MB (b) large systems

162. In a microprocessor based system, DMA

Ans. (c) : Flynn?s classification is based on the number

of instruction and data streams. There are four facility is required to increase the speed of the
 Multiple Choice Questions (MCQs)

categories of computing systems- data transfer between the

? SISD system (a) microprocessor and the I/O memory

? SIMD system (b) microprocessor and I/O devices

? MISD system (c) memory and the I/O devices

? MIMD system (d) memory and register

MISD (Multiple instruction single data) is a ESE-2013

multiprocessor machine capable of executing different

Ans. (c) : ? DMA (Direct memory Access) is a feature

instructions on different PEs but all of them operating on

of computer systems that increases the speed of the data

the same data set. No practical system only theoretical

transfer between the memory and the I/O devices.

interest system has been developed based on it.

? DMA is used when a large amount of data is to be

158. NMI input is

printed out from the memory of a computer.

(a) Edge Triggered on Negative edge i.e. 1 to 0

? DMA allows certain hardware subsystem to access

transition

main system memory (RAM) independent of the CPU. (b) Edge Triggered on Positive edge i.e. 0 to

transition 163. The brain of any computer is (c) Level triggered on 1 (a) ALU (b) CPU (d)

Level triggered on 0 (c) ROM (d) RAM

 Multiple Choice Questions (MCQs)

143. The basic memory cell in a DRAM is a

read or I/O write are active data remains input of the (a) MOSFET

processor. (b) Capacitor

(c) Capacitor and a MOS switch

138. In mode '0' (zero) operation of 8255, the ports

(d) Flip-Flop

can be used as port:

(a) A as input port only UKPSC JE 2013, PAPER-I (b) B as output port only Ans.(c): Dynamic

random? access memory is a type of (c) A as output port only random?access semiconductor

memory that stores each (d) A as input or output port bit of data in a memory cell consisting of

a tiny

294. If the accumulator of an Intel 8085 A

ADD B; A?A+B?A?8F+68 microprocessor contains 37 H and the previous

A=F7=(1111 0111)2 operation has set the carry flag, the instruction

(cid:1) As the output has odd number of 1s in the binary ACI 56 H will result in -

format, the parity will be zero i.e. P = 0 (a) 8E H (b) 94 H

(cid:1) After the addition of MSB no carry is generated

(c) 7E H (d) 84 H

therefore CS =0

Mizoram PSC IOF 2019, Paper-III

(cid:1) After addition of first 4 bit (starting from LSB) a

Ans. (a) : ACI = 56H ; A + 56A+CY?A

carry of 1 is generated then AC = 1

(cid:1) Sign flag is the value of MSB of the accumulator, 37H+56H+1 = 8EH
 Multiple Choice Questions (MCQs)

hence S = 1 295. The contents of accumulator after the

execution of following instruction will be -

290. For a memory system, the cycle time is

(a) same as the access time MVI A, A7H (b) larger than the access time ORA A (c) shorter

than the access time RLC (d) sub-multiple of the access time (a) CFH (b) 4FH

1. ROMs are used for temporary program and

Pp

with immediate data data storage.

The higher order data goes into higher register (H) and 2. Dynamic RAM is less expensive than

static

lower order data goes into lower order register (L). RAM

SHLD address (16bit)? Data from higher order 3. MASK ROM is used in high volume

microprocessor based system.

register (H) is stored in higher order memory location

and data from lower order register (L) is stored in Which of these statements is/are correct?

higher order memory location. (a) 1 only (b) 1 and 2

(c) 2 and 3 (d) 1, 2 and 3

LXI H, 01FFH?[H] ?01

ESE 2005

[L] ?FF

SHLD 2050H, Ans. (c) : ? Dynamic RAM is less expensive than static

2050H?[H] ?01 RAM.

2051H?[L] ?FF ? Dynamic RAM speed is lower than static RAM.

 Multiple Choice Questions (MCQs)

? DRAM has higher packing density than SRAM.

63. The arithmetic operation NEG invert:

(a) each bit of a specified byte or word and adds 1 ? Mask ROM (MROM) chips are used in high

volumes (b) each bit of a specified byte or word microprocessor based system that requires

long-term (c) the least significant bit of a specified byte or sustainability.

word ? MROM are used in network operating system are (d) the least significant bit of a specified

byte or server operating system.

7. An I/O processor control the flow of

Carry flag (CY) information between

Parity flag (P) (a) Cache memory and I/O devices

Auxiliary Carry flag (AC) (b) Two I/O devices

Zero Flag (Z) (c) Cache and main memories

Sign flag (S) (d) Main memory and I/O devices

RPSC ACF & FRO 23.02.2021

2. In 8085 microprocessor, the general purpose

register (GPR) are: Ans. (d) : An input processor control the flow of

(a) A B C D E F (b) A B C D H F information between main memory and input output (c) B C D H

L M (d) B C D E H L device.

214. The 8085 MPU can address-

without interfacing with the CPU. Cycle stealing mode (a) 28 memory locations

of DMA operation takes place while the microprocessor (b) 212 memory locations

is executing a program and an interface circuit takes (c) 216 memory locations

over control of address, data and control buses when not (d) 232 memory locations

in use by microprocessor. BSNL TTA 26.09.2016, 10 AM

 Multiple Choice Questions (MCQs)

210. In Intel 8085 A microprocessor ALE signal is Ans. (c) : 8085 MPU has 8 bit data bus and 16 bit

made high to address bus, thus it is capable of addressing 64 kB (216

(a) Enable the data bus to be used as low order memory location) of memory.

address bus 215. An interrupt breaks the execution of (b) To latch data D0-D7 from data bus

instructions and diverts its execution to? (c) To disable data bus (a) Interrupt service routine (d)

To achieve all the functions listed above (b) Counter word register

185. Five memory chips of 16 × 4 size have their Ans. (d) The correct sequence of steps to

perform

address buses connected together. This system "Fetch" operation in microprocessor is-

will be of size: 1. Places the address of first byte of instruction on the

(a) 16 × 16 (b) 16 × 20 address bus. (c) 20 × 16 (d) 16 × 64 2. Gets opcode on the data bus.

164. Programmable logic Array (PLA) uses??????

? With multiplexing, 8 pins are common used

(a) PROM matrices (b) RAM matrices

between address and data pins and thus total pins (c) Silo memory (d) ROM matrices

44. In 8085 microprocessor, stack works on?

(CY).

(a) LILO (b) LIFO (c) FIFO (d) None of these 49. The interfacing device used for the generator of

108. The Central Processing Unit (CPU) consists of

operation of 8 bit two?s complement operands. (a) ALU and Control unit only
 Multiple Choice Questions (MCQs)

operation of 7AH ? A2H (b) ALU, Control unit and Registers only

= D8H negative flag is set (c) ALU, Control unit and System bus only

(d) ALU, Control unit, Registers and Internal bus

103. In 8085 microprocessor, database byte is of:

(a) 8 bit (b) 16 bit ESE 2019 (c) 4 bit (d) 24 bit Mizoram PSC Nov. 2015, Paper-III

32. Which of the following will be done in an 8085

microprocessor when an instruction LXI H

27. In an 8086 microprocessor, in order to enable

2070H is executed?

higher order byte of data, ______ signal is used.

(a) Content of the memory 2070H is loaded in H

(a) ALE (b) DEN register (c) BHE (d) DT/R (b) 70 H is loaded in H register and 20 H is

109. The total average read or write time T is

104. Which of the following does NOT take place total

1b1b

when 8085 processor is reset?

(a) T + + (b) T + +

(a) 8085 gives reset out signal to reset external S 2r N S 2r rN

hardware T b b

(b) 8085 resets program counter to FFFFH (c) S + (d) T +2r+

16. Which interrupt has the highest priority?

hazard, to occupy a branch delay slot, to render avoid an

(a) RST 7.5 (b) RST 7

 Multiple Choice Questions (MCQs)

existing instruction such as a jump, or as a place-holder (c) RST 6.5 (d) INTR

120. What is the number of machine cycles in the

TRAP

instruction LDA 2000H that consists of

ESE-2014, 2008

thirteen states?

Ans. (c) : In interrupts priority order is

(a) 2 (b) 3 TRAP>RST7.5>RST6.5>RST5.5>INTR. (c) 4 (d) 5

125. Three devices P,Q and R have to be connected

Crystal frequency = 13 MHz

to an 8085 microprocessor. Device P has the

In 8051 microcontroller clock frequency

highest priority and device R has the lowest

Crystal frequency priority. In this context, which of the following

is the correct assignment of interrupt inputs?

12

(a) P uses TRAP, Q uses RST 5.5 and R uses

13

= =1.08MHz RST 6.5

12 (b) P uses RST 5.5, Q uses RST 6.5 and R uses

1 1 RST 7.5

Time period (T) = = =0.92µ sec (c) P uses RST 7.5, Q uses RST 6.5 and R uses

f 1.08
 Multiple Choice Questions (MCQs)

RST 5.5

= 0.9 µ sec (d) P uses RST 5.5, Q uses RST 6.5 and R uses

222. Which type of RAM is easier to interface with a

227. Both the ALU and control section of CPU employ

microprocessor?

which special purpose storage locations?

(a) static (b) dynamic (a) Buffers (b) Decoders (c) both static and dynamic (d) none of these

(c) Accumulators (d) Registers

92. Consider the following statements:

87. An 8254 programmable interval timer consists 1. The output unit of a computer communicate

of independent 16-bit programmable counters. the response of the computer to the uses.

This number is 2. Read/write memory is volatile.

(a) 2 (b) 3 3. the flip-flops in a register are connected in (c) 4 (d) 5 parallel.

280. When a peripheral is connected to the

An instruction cycle consists of a fetch cycle and microprocessor in input/output mode, the

data

execute cycle. transfer takes place between

275. The range of address where the Interrupt (a) any register and I/O device

service procedures are stored is : (b) memory and I/O device

(a) 00000 ? 000FF (b) 00000 ? 001FF (c) accumulator and I/O device

HH
 Multiple Choice Questions (MCQs)

(c) 00000 ? 002FF (d) 00000 ? 003FF (d) HL register and I/O device

268. Identify the 4-bit microprocessor from the

n = 13

following list.

263. What will be the content of accumulator after

the execution of XRA A instruction? (a) Intel 8085 (b) Intel 4010

(a) 1 (c) Intel 4004 (d) Intel 8086 (b) 0 MPPEB Sub. Engineer 0.8.07.2017 Shift-I (c) Depends

upon the current content of the Ans. (c) :

accumulator

Intel 8085 ?8-bit µP (d) None of these

199. To address the full memory space of an Intel

control bus is a microprocessor.

8085 microprocessor four RAMs of different

194. In 8085 MPU, the flag flip flops have_____

sizes are available:

status indicators. 1. 8K ×8 2. 16 K×4

(a) 5 (b) 2 3. 32 K × 4 4. 32 K × 16 (c) 4 (d) 1 What minimal combination of chip (s) will

170. In 8085 microprocessor, the RST6 instruction

Ans. (c) : Debug is synonymous to trouble shoot. transfer programme execution to following

Debugging is subset of troubleshooting. It requires location

finding problems as they relate to computer code. As (a) 0030H (b) 0024H

programmer, when you are tasked with debugging a (c) 0048H (d) 0060H

module of code you find what is causing the problem Haryana SSC JE 08.04.2018, Shift-I
 Multiple Choice Questions (MCQs)

and then fix it.

Ans. (a) : In 8085 instruction set, RSTn is actually

166. Sixty-four number of 256×1 bit RAM IC is standing for "Restartn" and in this case, n has

value

arranged in 8 rows and 8 columns to get from 0 to 7.

memory

(a) 1 kB (b) 2 kB RSTn=CALLn×8 (c) 4 kB (d) 8 kB According questions-

25. The contents of the Accumulator after the

ports. They can be configured as either input or output

execution of the following programme will be

ports. Each port uses three lines from port C as

MVI A C5H

handshake signals for data transfer. The remaining three

ORA A

signals from port C can be used either as simple I/O or

(a) 45 H (b) C5H

as handshake for port B. (c) C4H (d) None of these

195. Address bus is If there are four RAMS

(a) Unidirectional (b) Bidirectional

32k×16 (c) Non-directional (d) Multi-directional Then the size of each = =32k×4

67. Which one of the following functions is

 Multiple Choice Questions (MCQs)

MPMKVVCL (Bhopal) JE 2018 performed by the 8085 instruction MOV H, C?

Ans. (a) : The arithmetic operation NEG inverts each (a) Moves the contents of H register to C

register

bit of a specified byte or word and adds 1. (b) Moves the contents of C register to H register

Electronics-II 877 YCT

(c) Moves the contents of C register to HL pair Ans. (d) : Data that are stored at a given address in

(d) Moves the contents of HL pair to C register random access memory are lost when-

ESE-2002 ? Power goes off

Ans. (b) : This instruction moves the content of a C ? New data are written at the address

register to H register and content of C register remains ? RAM is a volatile memory.

unchanged. ? RAM gives applications a place to store and access

1- byte instruction data on a short term basis.

Machine cycle-opcode fetch.

73. Assembly language uses abbreviated English

68. Find the physical address if

words like ADD, JUMP, MUL, etc. These

ss:50000

words

sp:FFE0

are called:

(a) 14 FE0 (b) 15 FF0

(a) mnemonics (b) thesaurus (c) 25 FF0 (d) 5 FEE0

 Multiple Choice Questions (MCQs)

211. The control signal ALE is sent by Intel-8085 in is again transferred to the main program.

order to- 216. Which one of the following statements for Intel

(a) Inform I/O device that address is being sent 8085 is correct?

over the AD line (a) Program counter (PC) specifies the address of (b) Achieve separation of

address from data. the instruction last executed (c) Inform the memory device that address is

(b) PC specifies the address of the instruction

being sent over the AD line being executed (d) Inform I/O and memory that data is being (c) PC

specifies the address of the instruction to

126. In microprocessor architecture, flag indicates

ESE-2008

(a) the number of the microprocessor

Ans. (c) : Instruction LDA 2000H required 3 bytes, 4 (b) the name of the manufacturer

machine cycles (Opcode Fetch, Memory Read, Memory (c) the internal status of the CPU

Read, Memory Read) and 13T states for execution. (d) the bit size of the microprocessor

188. A semiconductor ROM is preferred to a

from the microprocessor, converts it into serial data and semiconductor RAM because-

then transmits the serial data. (a) ROM is cheaper than RAM

184. Simple Delay Circuit can be constituted by: (b) ROM is faster

(a) Shift Registers (b) Flip Flops (c) ROM does not require power supply for their

(c) Multiplexer (d) All of these operation

209. Cycle stealing mode of DMA operation involve- Ans. (d) : We use timing and controlling unit in

8085 for

(a) DMA-controlled taking on the address, data the generation of timing signals and the signals
 Multiple Choice Questions (MCQs)

to control

and control buses while a block of data is all the operations and functions both interior and

exterior

transformed between memory and I/O device. of a microprocessor are controlled by this unit.

Thus, (b) While the microprocessor is executing a control and timing section of CPU affects and

sequences

program an interface circuit takes control of all events within the CPU and the microcomputer.

the address, data and control buses, when not 213. Output of the assembler in machine codes is

in use by the microprocessor. referred to as (c) Data transfer takes place, between I/O device (a)

Object program (b) Source program

and memory during every alternate clock cycle. (c) Macroinstruction (d) Symbolic

255. A bus connected between the CPU and the

abbreviation, for operation to be performed. It is used main memory that permits transfer of

mnemonics in instruction code to make easy and information between main memory and

the

suitable coding. CPU is known as

Mnemonics codes are widely used in computer (a) DMA bus (b) Memory bus

programming and communications system operations to (c) Address bus (d) Control bus

specify instructions. ESE-2014

251. When an instruction is read from the memory, Ans. (b) : Data bus (memory bus) is

bidirectional

it is called? because data flow in both directions, from µp to

 Multiple Choice Questions (MCQs)

(a) Memory read cycle memory or I/O devices and from memory or I/O (b) Fetch cycle

devices to microprocessor length of data bus of 8085 (c) Instruction cycle µp is 8 bit (That is, two

Hexadecimal disits) (d) Memory write cycle 256. Each Push and POP operation involves ?? at

84. Consider the following statements:

A1 A0 1. The process of entering data is called burning

Port A ? 0 0 in ROM.

Port B ? 0 1 2. ROMs are volatile memories.

Port C ? 1 0 3. ROMs are used in microcontroller security

systems.

Control register ? 1 1

What of these statements are correct?

(a) 1,2 and 3 (b) 1 and 2 (c) 2 and 3 (d) 1 and 3

292. The synchronization between microprocessor

and memory is done by -

2 times the instruction RAL must be executed so that

the accumulator reads A9H, at that instant CY will be 0. (a) ALE signal (b) HOLD signal

(c) READY signal (d) None of these

289. Check the following program in 8085

Mizoram PSC IOF 2019, Paper-III

microprocessor.

BSNL TTA (JE) 2013

MVIA, 8FH
 Multiple Choice Questions (MCQs)

MVIB, 68H Ans. (c) :

ADD B

The status of CY, AC, P and S for the program

is:

(a) AC = 1; CY = 0; S = 1; P = 0 (b) AC = 0; CY = 0; S = 1; P = 0 (c) AC = 0; CY = 1; S = 0; P = 1

READY SIGNAL- This is an active high input control (d) AC = 1; CY = 1; S = 0; P = 1 signal. It is

used by microprocessor to detect whether a

310. Why a ROM does not have data inputs?

reprogramming it is common to protect the EPROM (a) It does not have a WRITE operation

window indicated, with opaque sticker. The sticker over (b) Data input are integrated with data

outputs

the EPROM window protects the chip from ultraviolet (c) Data inputs are integrated with address

inputs

(UV) lights and sunlight. (d) ROM is sequentially accessed

ESE-2016

307. Access time in memories is equal to-

(a) Latency time (b) Seek time Ans. (a) : ROM ? Data stored in ROM cannot be (c) Transfer time

(d) Sum of all these electronically modified after the manufactured of the

82. A direct memory access (DMA) transfer

78. After an arithmetic operation, the flag register

implies
 Multiple Choice Questions (MCQs)

of a 8085 microprocessor has the following

(a) Direct transfer of data between memory and

look:

accumulator

D D D D D D D D

7 6 5 4 3 2 1 0 (b) Direct transfer of data between memory and

1 0 X 1 X 0 X 1 I/O device without the use of microprocessor

The arithmetic operation has resulted in (c) Transfer of data exclusively within

(a) A carry and an odd parity number having 1 as microprocessor registers

the MSB (d) A fast transfer of data between

6. The number of memory cycle required to

execute the following 8085 instructions:

1. The number of status flags in 8085 (I) LDA3000H (II) LXI D, F0F1 H would be

microprocessor is: (a) 4 for (I) and 3 for (II)

(a) 6 (b) 4 (b) 3 for (I) and 3 for (II) (c) 3 (d) 5 (c) 3 for (I) and 4 for (II)

11011011. The memory word could not be interpreted (a) 10 µs (b) 5µs

as BCD number. (c) 4 µs (d) 2.5µs

In BCD code each decimal number is represented by a 4 ESE-2008

bit binary number. In BCD only 4 bit binary number 1 1

valid from 0000 to 1001. Ans. (b) : T = = =0.5µsec

f 2MHz

119. The timer clock frequency and its period for Instruction cycle = 10 × T states
 Multiple Choice Questions (MCQs)

the crystal frequency of 13 MHz will be = 10 × 0.5 µ sec = 5 µsec

(a) Clock frequency = 1.08 Hz and Time Period 124. What language is understood by 'Micro

= 0.9s processor'? (b) Clock frequency = 1.08 Hz and Time Period (a) Binary (b) Fortran

= 0.9µs (c) Instruction (d) C++

72. Consider the following statements: contain the address of the next instruction to be fetch

Data that are stored at a given address in a from the main memory when the previous instruction

random access memory are lost. has been successfully completed. It is a 16 bit register.

1. When power goes off

77. If a memory has 10 address lines and the size of

2. When the data are read from the address

each addressable location (block) is 4 bytes,

3. When new data are written at the address

then what is the maximum storage capacity of

4 because it is non-volatile memory

the memory?

Which of these statements are correct?

(a) 1 and 2 (b) 1, 2 and 4 (a) 4 kilobyte (b) 2 kilobyte (c) 2 and 3 (d) 1 and 3 (c) 1 kilobyte (d)

3 kilobyte

26. Which of the following is not correct? 31. The 8251A programmable communication chip

(a) Bus is a group of wires. is designed for: (b) Bootstrap is a technique or device for loading (a)

synchronous and asynchronous serial data

first instruction. communication (c) An instruction is a set of bits that defines a (b) synchronous

and asynchronous parallel data

computer operation.
 Multiple Choice Questions (MCQs)

communication (d) An interrupt signal is required at the start of (c) synchronous parallel data

communication only

105. Which among the following is the basic Rotation speed = r revolution/second

memory cell of dynamic RAM? ?r revolution in 1 second

(a) MOSFET (b) Transistor and a capacitor 1 (c) Capacitance (d) Flip-flop ? revolution in

second

98. The non-maskable interrupt pointer of 8086 is

ESE 2005

stored at

(a) 00000 (b) 000FF Ans. (c) : In the real mode address space of the 8086,

HH

(c) 00000 - 00008 (d) 00000 - 0003FF 1024(1k) bytes are reserved for the interrupt vector

218. A good assembly language programmer should get the answer. The working style of dynamic

memory

uses general purpose registers rather than is simple which makes it easy to interface.

memory in maximum possible ways for data 223. In 8085 MPU, sequencing the execution of

processing. This is because. instructions is done by the

(a) Data processing with registers is easier than (a) accumulator (b) flag

with memory. (c) stack pointer (d) program counter

12. In a microprocessor, the address of the next modes being used.

instruction to be executed, is stored in 18. The programm counter in an 8085

(a) Stack pointer microprocessor is a 16 bit register because (b) Address latch (a) It counts 16 bit
 Multiple Choice Questions (MCQs)

at a time. (c) Program counter (b) There are 16 address lines. (d) General purpose register (c)

It facilitates the user storing 16 bit data

181. For a 4096 × 8 EPROM, the number of address

Maximum positive number =2n?1?1=28?1?1=+127 lines is:

(a) 14 (b) 12

Maximum negative number = ?2n?1=?28?1=?128 (c) 10 (d) 8

16. time and produces an n-bit output code that depends on

512

the activated input.

317. When the signal on RESET IN goes low, which

314. Each cell of a static RAM contains

of the following happens in 8085?

(a) 4 MOS transistors

(a) The program counter is set to zero (b) 4 MOS transistors and 1 capacitor

(b) The buses are tristated (c) 2 MOS transistors

(c) The MPU is reset (d) 4 MOS transistors and 2 capacitors

90. What is the total number of memory locations 94. In microprocessor 8085, CALL instruction

and input-output devices that can be addressed have ______.

with a processor having 16-bits address bus, (a) 3 bytes, 18 T states (b) 3 bytes, 16 T states

using memory maped I/O? (c) 2 bytes, 16 T states (d) 2 bytes, 10 T states

(a) 64K memory locations and 256 I/O devices PGVCL JE 2018 (b) 256 I/O devices and 65279
 Multiple Choice Questions (MCQs)

memory locations Ans. (a) : The instruction CALL requires 3 Bytes, 5- (c) 64 K memory locations

and no I/O devices machine cycles (OP code fetch, memory Read, Memory (d) 64K memory

locations or input-output Read, Memory write, Memory write ) and 18 T- states

4. An ideal Op-Amp has impedance

(cid:1) Infinite input impedance (a) Very high input and output

(cid:1) Zero output impedance (b) Very low input and out-put

(cid:1) Infinite Bandwidth (c) Low input impedance and high output

(cid:1) Zero offset voltage (d) Infinite input impedance and zero output

(cid:1) Infinite common mode rejection ratio (CMRR)

UPRVUNL AE 04.07.2021

2. The given circuit represents a Nagaland PSC CTSE (Diploma) 2017, Paper-I

BSNL TTA (JE) 14.07.2013

Ans. (d) : An ideal op-Amp should have infinite input

impedance and zero output impedance.

5. Virtual ground property of operational

amplifier indicates that

(a) inverting and non-invering terminals are

connected to ground (b) inverting and non-inverting terminals are at

the same potential (c) system is at rest (d) any one terminal is connected to ground

311. Which of the following instruction can alter the

example, the read/write head is on track 1 but we need

normal incrementing of the program counter?

 Multiple Choice Questions (MCQs)

to read data from another track or segment. Thus, the

(a) Interrupt (b) Call

read/write head will move to the data block location (c) Branch (d) All of these

56. In 8085, what is the output after the execution

? Used as cache memory of the following instructions:

? Faster, expensive and large size MVI A, 06H

? Long life and no need to refresh MVI L, 04H

ADD L

52. The interface chip used for data transmission

(a) 0A H (b) 10 H

between 8085 and a 16 bit ADC is

(a) Intel 8257 (b) Intel 8253 (c) 06 H (d) 04 H

8080. 8080 microprocessor is 8-bit

1. In this device address 1. In this I/O device microprocessor and also 8085 microprocessor is

8-bit

microprocessor.

is 16 bit. Thus A to address is 8 bit. Thus A

0 0 8080 microprocessor has 40-pin DIP It has 8-bit data bus

A lines are used to to A or A to A lines

15 7 8 15 and 16-bit address bus . It is made by 6000 transistor.

generate device are used to generate

address. device address. 197. Which of the following is a DMA controller?

(a) Intel 8257 (b) Intel 8259

2. MEMR and MEMW 2. IOR and IOWcontrol (c) Intel 8255 (d) Intel 8253
 Multiple Choice Questions (MCQs)

33. When light is produced by fittings that throw

all the light on the ceiling, from where it is 3rdA?B0H

reflected to the area to be lighted, this method RLCA?61H

of lighting arrangement is known as:

Hence, NOP instruction executes only 3 times.

(a) general diffusing system

38. Memory refreshing may be done by: (b) semi-direct system

(a) DMA controller (c) indirect lighting arrangement

(b) Stack pointer (d) direct lighting arrangement

308. Consider the following statements: to the stack, and it is changed to the first instruction

1. RAM is a non-volatile memory of the subroutine.

2. RAM is a volatile memory whereas ROM is a ? Branch instruction- The program counter is

non-volatile memory. changed to the new location.

3. Both RAM and ROM are volatile memories 312. A memory system has a total of 8 memory

but in ROM data is nor when power is chips, each with 12 address lines and 4 data

switched off. lines. The total size of the memory system is

Which of the above statements are correct? (a) 32 k bytes (b) 48 k bytes

(a) 1 only (b) 2 only (c) 64 k bytes (d) 16 k bytes

269. Assuming LSB is at position 0 and MSB at

Here source and destination operand both are same i.e. position 7, which bit positions are not

used
 Multiple Choice Questions (MCQs)

A. Therefore, the result after performing EX-OR

(undefined) in flag register of an 8085

operation, stored in the accumulator is 00.

microprocessor?

264. The first microprocessor to include virtu al (a) 1,3,5 (b) 2,3,5

memory in the Intel microprocessor family is

(c) 1,2,5 (d) 1,3,4

(a) 80286 (b) 80386 (c) 80486 (d) Pentium ESE-2015

29. In which of the following modes in 8255 A PPI

result of the operation so, all flags will be affected. can part A be used as a bidirectional data bus?

24. What is the number of machine cycles in the (a) BSR mode (b) Mode 1

instruction LDA 2000 H that consist of thirteen (c) Mode 2 (d) Mode 0

states? LMRC (SCTO) 17.04.2021

(a) 2 (b) 3

Ans. (c) : 8255A has three different operating modes-

(c) 4 (d) 5

259. Which one of the following is not a vectored

which µ.p can generate some address are given to the interrupt?

memory and some to the device. A I/O device is also (a) TRAP (b) RST 7.5

treated the same as a memory. (c) RST 3 (d) INTR

Mizoram PSC IOF- 2019 Paper-II

254. In 8085 microprocessor, assume that the stack

 Multiple Choice Questions (MCQs)

BSNL TTA- 26.09.2016, 3 PM

pointer is pointer to the memory location

ESE-2003

2000H and register DE contains value 1050H.

Ans : (d) Non vectored interrupts: Those vectored in

After the execution of instruction PUSH D, the

which vector address is not predefined. The interrupting

stack pointer would be pointing at:

(a) 2000H (b) 1FFDH device gives the address of sub routine for these

interrupts. INTR is the only non-vectored interrupt in (c) 1FFFH (d) 1FFEH

113. In microprocessor interface, the concept of

117. The instruction ANA M is

detecting some error condition such as 'no

(a) Four byte instruction

match found' is called (b) Three byte instruction

(a) Syntax error (b) Semantic error (c) Two byte instruction

(c) Logical error (d) Error trapping

22. The contents of the accumulator in an 8085

Ans. (a) : The 8085 microprocessor has five interrupt

microprocessor is altered after the execution of

signals that can be used to interrupt a program

the instruction:

execution.

(a) CMPC (b) CPI 3A

 Multiple Choice Questions (MCQs)

In interrupts priority order is (c) ANI 5C (d) ORA A

58. When RET instruction is executed by any

Printer port (port 631) is the parallel port of a computer subroutine then

used by printer. (a) the top of the stack will be popped out and

54. The address bus width of 8085 microprocessor assigned to the PC

is: (b) without any operation, the calling program

(a) 32 bit (b) 8 bit

would resume from instruction immediately (c) 16 bit (d) 64 bit following the call instruction

134. A microprocessor contains ROM chip which

memory location as pointed by HL register pair. contain

In order to output data from the accumulator to the (a) Control function

device the sequence of instructions will be LXIH,

(b) Arithmetic function

1000H MOV M, A.

(c) Instruction to execute data

129. Instruction RET (Return) of a 8085 (d) Memory functions

microprocessor Mizoram PSC Nov. 2015, Paper-III

(a) Stack Pointer and program counter

Ans. (d) : A microprocessor contain ROM chip which (b) Stack Pointer only

contain memory function. ROM (read only memory) is (c) Program counter only

an electronic storage elements which contain the data in (d) Set interrupt mask and accumulator
 Multiple Choice Questions (MCQs)

142. On receiving an interrupt the CPU of an 8085 Ans. (c) :.

microprocessor

Interrupt Triggering Vectored Maskable/No

(a) completes the current instruction and then

Address n-maskable

goes to the interrupt service routing

TRAP Edge and 0024H Non-maskable (b) Branches off the the interrupt service routing

level

immediately

RST 7.5 Edge 003CH Maskable (c) hands over control of address bus and data

bus to the interrupting device RST 6.5 Level 0034H Maskable (d) Goes to HALT state for pre

determined RST 5.5 Level 002CH Maskable

65. Which of the following flags is NOT present in

automatically do a type-1 interrupt after each instruction 8085?

executes. when the 8086 does a type 1 interrupt, it (a) Sign (b) Parity

pushes the flag register on the stack. (c) Trap (d) Auxiliary carry

MPMKVVCL (Bhopal) JE 2018

62. Consider the execution of the following

instructions by an 8085 microprocessor: Ans. (c) : In 8085 microprocessor, the flags register can

LXI H, 01FFH have a total of eight flag. Thus a flag can be represented

SHLD 2050H by 1 bit of information. But only five flags are

 Multiple Choice Questions (MCQs)

After execution the contents of memory implemented in 8085 and they are :

locations 2050 H and 2051 H and the registers ? Carry flag (CY)

H and L, will be ? Auxiliary carry flag (AC)

(a) 2050 H?FF; 2051H?01; H?FF;L?01 ? Sign flag (S) (b) 2050H?01;2051H?FF;H?FF;L?01 ?

Parity flag (P) (c) 2050H?FF;2051H?01;H?01;L?FF ? Zero flag (Z) (d)

2050H?FF;2051H?01;H?00;L?00 66. Consider the following statements: In

150. The number of memory cycles required to MVI A, B7H

execute the following 8085 instructions A = B7

(i) LDA 3000 H ORA A

(ii) LXI D, FOF 1 H A+A = A

would be? A = B7

(a) 2 for (i) and 2 for (ii) A = 1011 0111 (b) 4 for (i) and 3 for (ii) (c) 3 for (i) and 3 for (ii) (d) 3 for

(i) and 4 for (ii)

265. The 8085 MPU requires a power supply of- 7 6 5 4 3 2 1 0

(a) +5V single (b) +5V dual S Z X AC X P X CY (c) +12V single (d) +12V dual

140. After completing the execution, microprocessor

from 0000H to 03FFH.

returns to

(a) Halt state (b) Execute state 146. ALE stands for (c) Fetch state (d) Interrupt state (a)

Address latch enable

284. In 8086, the physical address of an instruction 288. In 8085 microprocessor, assume the

contains ......... bits : accumulator contains AAH and CY = 0. How

 Multiple Choice Questions (MCQs)

(a) 10 (b) 16 many times the instruction RAL must be (c) 18 (d) 20 executed so that the

accumulator reads A9H.

95. In a microprocessor, the service routine for a

Ans. (d) : Memory Mapped I/O ? In mapped I/O the certain interrupt starts from a fixed location of

I/O devices are also treated as memory location, under memory which cannot be externally set, but

the

that assumption they will be given 16 bit address. interrupt can be delayed or rejected such an

memory locations = 216 = 26 × 210 = 64 K memory interrupt is?

locations. (a) Non-maskable and non-vectored

91. What is the main purpose of Accumulator? (b) Maskable and non-vectored

(a) temporary data storage (c) Non-maskable and vectored (b) keeping track of the next

instruction to be (d) Maskable and vectored

executed BSNL TTA 29.09.2016, 3 pm

Electronics-II 880 YCT

Ans : (d) In a microprocessor, the service routine for a 100. An 8085 microprocessor based

system uses a

certain interrupts starts from a fixed location of memory 4k×8 bit RAM Whose starting address

is

which cannot be externally set, but the interrupt can be AA00H. The address of the last byte in this

delayed or rejected such an interrupt is maskable and RAM is

vectored. (a) 0FFF H (b) 1000 H

96. In Intel 8085, the interrupt enable flip-flop is (c) B9FF H (d) BA00 H

221. Which of the following does not constitute the

 Multiple Choice Questions (MCQs)

minimum architectural unit of a 226. The present microinstruction fetched from a

microprocessor? microprogrammed control unit is held in the

(a) ALU (a) next address register (b) Program Counter (b) control address register (c)

Programmable Timers (c) control data register (d) pipeline register

204. The number of hardware interrupts (which 208. A microprocessor is ALU

require an external signal to interrupt present (a) and control unit on a single chip

in an 8085 microprocessor are??????? (b) and memory on a single chip

(a) 1 (b) 4 (c) register unit and I/O device on a single chip

(c) 5 (d) 13 (d) register unit and control unit on a single chip

97. In how many different modes a universal shift

register operates

(a) 5 (b) 4 (c) 3 (d) 2 101. The interrupt vector table IVT of 8086 contains

8253. The MVI A, 06H ? A = 06H

interface chip used for data transmission between 8086 MVI L, 04H ? L = 04H

and a 16 bit ADC is Intel 8255.

ADD L ? A = A+L

53. Ports are used to connect the CPU to which of output = A+L

the following units? = 06H + 04H

1. Printer = 0AH

2. floppy disk drives

 Multiple Choice Questions (MCQs)

57. The total addressable memory size of 8085 is-

3. Video display unit

(a) 16 kb (b) 32 kb

4. Incoming power supply (c) 64 kb (d) 128 kb

298. A 8085 microprocessor program uses all ? The mechanical characteristics of the interface

available Jump instructions, each only once. ? The electrical signals across the interface

For this program, the total memory (in Bytes) ? The function of each signal

occupied by the Jump instructions is - ? Subsets of signals for certain applications.

(a) 30 (b) 27

302. The 8259 A programmable interrupt controller (c) 24 (d) 18

122. In a microprocessor when a CPU is

interrupted, it

(a) Stop execution of instructions

Electronics-II 884 YCT

127. What are the number of memories required of 132. To address the memory 14 bits are used.

Then

size 16 × 4 to design a memory of size 64 × 8 ? what is the address of the last memory

(a) 2 (b) 4 location? (c) 6 (d) 8 (a) 16382 (b) 16383

148. What is the functionality of the program given Ans. (d) : For given chip selection

below? A = 1, A = 0, A =0, A = 0, A = 0
 Multiple Choice Questions (MCQs)

15 14 13 12 11

MOV A, #0

MOV R2, #10

AGAIN: ADD A, # 03

DJNZ R2, AGAIN

MOV R5, A

(a) It clears the accumulator and add value 3 to Then range = 8800H-8FFFH

the accumulator 10 times.

152. In an 8085 microprocessor, the instruction (b) It adds the content of R2 and A and then

store

CMP B has been executed while the content of

the result in accumulator

the accumulator is less than that of register B. (c) It decrements the register R2 10 time and then

As a result

store value 3 to the accumulator.

(a) Carry flag will be set but Zero flag will be reset (d) It clears the accumulator and then add

value

256. I/O devices can be connected. ANI Data - 2

Electronics-II 883 YCT

In 8085 instruction set, ANA is mnemonic, which (b) Acknowledges interrupt and branches

off

stands for "AND Accumulated" and M stands for one subroutine

of the memory location pointed by HL register pair. (c) Acknowledges interrupt and continuous
 Multiple Choice Questions (MCQs)

There are eight op-codes for this type of instruction. It interrupt

is occupies only 1-byte in memory. (d) Acknowledges interrupt and waits for the

next instruction from the interrupting device.

118. The contents of memory location 4 FFFH are

RRB SSE Bilaspur Yellow paper, 21.12.2014

11011011. The memory word could not be

interpreted as which one of the following? Ans : (d) In a microprocessor when a CPU is

(a) 2's complement number interrupted, it acknowledges interrupt and waits for the (b) 1's

complement number next instruction from the interrupting device. (c) Octal number 123. An Intel

8085A microprocessor is operated at a (d) BCD number frequency of 2 MHz. If the instruction

LXIH,

243. Microprocessor is- It has the following configuration-

(a) ALU and memory on a single chip ? 8 - bit data bus (b) ALU and I/O devices on a single chip ?

16 - bit address bus, which can address up to 64 kB (c) ALU and control unit on a single chip ?

Requires + 5V supply to operate at 3.2 MHz single (d) ALU, register unit and control unit on a

phase clock

30. In 8085 microprocessors, MVI A, 23H is an

Ans. (a) : As given, example of which addressing mode?

(a) Direct addressing

MVI A, C5H ; C5H?A

ORA A ; Reset carry flag (b) Register addressing

RAL ; Rotate A left through (c) Indirect addressing

 Multiple Choice Questions (MCQs)

; Carry, A= 8AH (d) Immediate addressing

240. HOLD & HLDA pair provides the

15 14 13 12 11 8 7 4 3 o

handshaking signals required for ????????

0 1 1 0 0000 0000 0000

operation.

0 1 1 1 1111 1111 1111 (a) UART (b) USART

(c) DMA (d) All

If, A =0?6000-6FFF

12 BSNL TTA 28.09.2016, 3 PM

And, if A12 =1?7000-7FFF Ans. (c) Using a Direct Memory Access (DMA), the

Hence, 6000H-6FFF and 7000H-7FFF H device (DMA) requests the CPU to hold its data address

and control bus, so the device is free to transfer data

237. Consider the following 8086 assembly language

directly from the memory. The DMA data transfer is

program:

initiated only after receiving HLDA signal from the CPU.

MOV AX, BB11H

? HLDA?HOLD acknowledge

MOV CX, 1122H

241. The address bus of Intel 8085 is 16-bit wide and

ADD AX, CX

hence the memory which can be accessed by

HLT
 Multiple Choice Questions (MCQs)

this address bus is

The result of this program is: (a) 2 k bytes (b) 4 k bytes

(a) CX = CC33H (b) AX = CC33H (c) 16 k bytes (d) 64 k bytes

231. Normally a microprocessor cycles between????

(a) fetch and halt state The carry flag is set since the first operand is less than

the second operand. Since the result produces the (b) fetch and interrupt state

negative result sign flag is set. (c) fetch and execute state

i.e. CY=1 (d) halt and execute state

128. BSNL TTA (JE) 27.09.2016, 10 AM

176. Mnemonic codes are used

Ans. (b) 2N×M

(a) To denote address

Where N ? Address line (b) To employ hamming code

and M ? data lines (c) To denote errors

?Given as - 4096×8 (d) To assist human memory

318. Consider the following statements:

? Each cell of a DRAM contains 1 MOS transistor

1. SRAM is made up of flip-flops.

and 1 capacitor.

2. SRAM stores bit as voltage

? It has higher access time, so it is slower than

3. DRAM has high speed and low density

SRAM.
 Multiple Choice Questions (MCQs)

4. DRAM is cheaper than SRAM

? It costs less compared to SRAM.

Which of the above statements are correct?

315. There are ................. types of flags in 8086.

(a) 1,2, and 3 (b) 1, 3 and 4

(a) 8 (b) 9 (c) 2, 3 and 4 (d) 1, 2 and 4

193. Multiplexing of address and data lines is used w

inserted between T and T to the length of a bus cycle.

in: 2 3

(a) Intel 8086 (b) Z-80 (c) 6502 (d) MC-68000

200. An I/O processor control the flow of 205. The 8259 A programmable Interrupt controller

information between: can

(a) cache memory and I/O devices 1. Manage eight interrupts (b) main memory and I/O devices

2. Vector an interrupt request anywhere in (c) two I/O devices memory map (d) cache and

main memories 3. Have 8 bit or 16- bit interval between

233. The field, which is never present in an

was intel 4004. The Intel 4004 was a 4-bit central

assembly language statement, is

processing unit (CPU) released in 1971 by Intel

(a) Op-code (b) Operand

corporation. It was the first commercially available (c) Continue (d) Comment

285. If instruction RST-5 is written in a program.

 Multiple Choice Questions (MCQs)

a µp that send information into the computer. An output The programme will jump to location -

device is something you connect to a computer that has (a) 0020 H (b) 0024 H

information sent to it. (c) 0028 H (d) 002 CH

The accumulator is an 8-bit resister that is a part of Mizoram PSC IOF 2019, Paper-III

arithmetic logic unit (ALU). This resister is used to Ans. (c) : RST 5 = CALL 5×8

store 8-bit data and to perform arithmetic and logical = CALL 40

operations. The results of an operation is stored in the = CALL 0028H

accumulator. 286. In an 8085 microprocessor system with

281. The number of bytes in an instruction for 8085 memory mapped I/O -

can be : (a) I/O devices have 16 bit addresses

(a) One or two (b) One, two or three (b) I/O devices are accessed using IN and OUT (c) Two only

(d) One only instruction

13. The 8085 assembly language instruction that (cid:1) It has total 16 address lines with address

capacity of

stores the contents of H and L registers into the 64 KB.

memory locations 2050H and 2051H, 19. A programmable ROM has a decoder at the

respectively, is: input and OR gates at the output with

(a) SPHL 2050H (b) SPHL 2051H (a) both these blocks being fully programmable (c) SHLD

2050H (d) STAX 2050H (b) both these blocks being partially

137. When memory write or I/O read are active, Ans. (a) : When CPU of an 8085 µpreceives

an
 Multiple Choice Questions (MCQs)

data remains _______of the processor.

interrupt then-

(a) Input (b) Output

? First of all, the current task will finish. (c) Processor (d) None of these

291. When a subroutine is called, the address of the

Accumulator = AAH, CY = 0. instruction following the CALL instruction is

stored in/on the -

(a) Stack pointer (b) Accumulator (c) Program counter (d) Stack

35. _________ is a programming language that

(cid:2) A stack pointer is small register that stores the

utilises statements to determine what to

address of the last program request in a stack.

execute.

(a) Function block diagram 40. In microprocessor architecture, flag indicates (b) Structured text

programming the: (c) Sequential block diagram (a) Internal status of CPU. (d) Instruction

programming (b) Bit -size of microprocessor.

8. In 8085 processor SOD and SID pins are used

UJVNL JE 2016 for

Ans. (d) : Register B, C, D, E, H and L are general (a) Providing power supply to the processor

purpose register in 8085 microprocessor. All these (b) Serial communication

general purpose registers are 8- bits wide. (c) Providing system clock

(d) Providing reset signal to processor

 Multiple Choice Questions (MCQs)

3. In 8085 microprocessor system, the direct

RPSC ACF & FRO 23.02.2021

addressing instruction is -

(a) MOV A, B (b) MOV B, 0AH Ans. (b) : In 8085 processor SOD and SID pins are (c) MOV C, M

(d) STA addr used for serial communication.

2. (d) by increasing the clock frequency

and when shifting a binary number by one bit to right is

ESE-2015

divide by 2.

BSNL TTA (JE) 14.07.2013

183. Which one of the following is used for serial

Ans. (b) : When microprocessor needs to interface with

I/O transfer in 8085 based system?

a slow external memory. It starts placing the address of

(a) 8251 (b) 8255

the requested information on the address BUS. (c) 8259 (d) 8279

15. A microprocessor is Arithmetic logic unit 1 1

Ans. (b) : Time T= = =0.2µs

(a) And control unit on a single chip. f 5MHz (b) And memory on a single chip. Then, 18 T = 18 ×

0.2 µs = 3.6µs (c) Register unit and I/O device on a single chip

21. NOP instruction is used to (d) Register unit and control unit on a single chip.

40. 2 2

= log 212
 Multiple Choice Questions (MCQs)

203. A shift register can be used for- 2

= 12 {?log 2=1}

(a) Parallel to serial conversion only 2 (b) Serial to parallel conversion only 207. What are level

triggering interrupts? (c) Digital time delay only (a) INTR & TRAP (d) All of these (b) RST 6.5

& RST 5.5

4096. Ans. (b) The need of programmable interrupt control

182. Shifting the contents of a register, left by one unit is when more interrupt is managed of a time

in

place, is equivalent to: microprocessor, If INTR means interrupt request is

(a) Dividing the contents by 10 provided to microprocessor then we have to connect are (b)

Dividing the contents by 2 out side chip is needed. (c) Multiplying the contents by 2 187. To

interface a slow memory, wait states are (d) None of these added by

206. To address a memory location out of N

continues its normal operations, is the incorrect memory locations, the number of address lines

statement. required is-

202. The number of output pins of a 8085 (a) Log N (to the base 2)

microprocessor are (b) Log N (to the base 10)

(a) 40 (b) 27 (c) Log N (to the base e)

(c) 21 (d) 19 (d) Log (2N) (to the base e)

234. The contents of register (B) and accumulator

230. In an Intel 8085 A microprocessor, why is (A) of 8085 microprocessor are 49H and 3AH
 Multiple Choice Questions (MCQs)

READY signal used? respectively. The contents of A and status of

(a) To indicate to user that the micro-processor is carry (CY) and sign (S) after execution SUB B

working and is ready for use. instructions are- (b) to provide proper WAIT states when the (a)

A = F1, CY = 1, S = 1

microprocessor is communicating with a slow (b) A = 0F, CY = 1, S = 1

peripheral device. (c) A = F0, CY = 0, S = 0

(c) To slow down a fast peripheral device so as to (d) A = 1F, CY = 1, S = 1

287. The stack pointer in the 8085 microprocessor is

LDAX B

2-byte instruction a -

MVIA, 28H (a) 16 bit register that point to stack memory

IN 56H locations

3-byte instruction (b) 16 bit accumulator

LDA, 2005H (c) memory location in the stack

JMP, 2056H (d) flag register used for the stack

282. While execution of I/O instruction takes place, Mizoram PSC IOF 2019, Paper-III

the 8-bit address of the port is placed on Ans. (a) : In the programmer's view of 8085 only the

(a) lower address bus general purpose resisters A, B, C, D, E, H and L and the (b) higher address

bus flags registers were discussed so for but in the complete (c) data bus programmer's view of

8085 there are two more special (d) lower as well as higher order address bus purpose registers

each of 16 bit width.

293. In the 8085 microprocessor, the RST6

 Multiple Choice Questions (MCQs)

instruction transfers the program execution to

the following locations -

(a) 30H (b) 24H (c) 48H (d) 60H

145. Memory range of a memory chip 1 K is

general purpose register. An accumulator is a type of

(a) 0000H to 03FFH (b) 0001H to 01FFH

register included in a CPU it acts as a temporary storage (c) 0000H to 02FFH (d) 0000H to 04FFH

9. In 8086 microprocessor the following has the

4. The data bus of any microprocessor is always

highest priority among all type interrupts.

(a) unidirectional

(a) DIV 0 (b) TYPE 255

(b) bidirectional (c) OVER FLOW (d) NMI

283. The memory addressing capacity of 8086 is :

(a) 32 KB (b) 64 KB (c) 1 Megabyte (d) 32 Megabyte

161. Which of the following instruction of 8085

of 8086 is 1K Byte, 256 procedures. It is a two byte

instruction, the first byte provides the OP code and the microprocessor has maximum T states

when

second byte provides the interrupt type number. There compared to others?

are 256 interrupt types under this group. (a) DAD (b) ADI

157. According to Flynn's classification, which (c) XCHG (d) SUI

architecture is of only theoretical interest and TSPSC Manager (Engg.)HMWSSB 2020

 Multiple Choice Questions (MCQs)

no practical system has been developed based Ans. (a) : DAD instruction of 8085 microprocessor

has

on it? maximum T states (10) compared to others. In 8085

(a) Single instruction single Data (SISD) instruction. DAD SP instruction is a special case of (b)

Single Instruction Multiplied Data (SIMD)

DAD rp instruction. In this instruction contents of HL & (c) Multiple Instruction Single Data (MISD)

SP will get added and produced will get stored onto HL (d) Multiple Instruction Multiple Data

(MIMD)

309. In the instruction MOV A, M

microprocessor returns from the HALT state to the fetch (a) The content of memory addressed by

HL pair

state. In fetch operation, the microprocessor takes the is moved to A register

(b) The content of A register is moved to

address of first byte of instruction to the address bus

memory location addressed by HL pair

with a control signal and reads the instruction from the

memory location. (c) The 8 bit data is moved to A register

(d) None of these

306. The sticker over the EPROM window protects

BSNL TTA 27.09.2016, 3 PM

the chip from

Ans : (a) In 8085 instruction set, MOV R, M is an

(a) infrared light from sunlight

 Multiple Choice Questions (MCQs)

instruction where the 8-bit data content of the memory (b) UV light from fluorescent lights and

sunlight

location as pointed by HL register pair will be moved to (c) magnetic field

the register R. This is an instruction to load register R (d) electrostatic field

7. =T + +

Each of these would send the execution to a s 2r rN

predetermined hard wired memory location. The 110. Which one of the following statement

function of these ISR is defined by the user. corresponding to execution of SIM instruction

107. Which of the following memories requires is not correct?

refreshing cycle? (a) It will selectively mark all the interrupts of

(a) RAM (b) ROM 8085 (c) Dynamic MOS (d) All of these (b) Contents of bit (D7) are copies

on SOD pin

246. 8085 operates with-

(a) 1 MHz single phase clock 250. When referring to instruction words, a (b) 2 MHz single

phase clock mnemonic is (c) 2 MHz two phase clock (a) a short abbreviation for the operand

address. (d) 3 MHz single phase clock (b) a short abbreviation for the operation to be

71. What will be the maximum number of H e nce, we obtain 16 ICs a column.

addressable locations in a memory using 9

76. Which of the following CPU registers contains

address lines?

the address of the next instruction to be fetched

 Multiple Choice Questions (MCQs)

(a) 511 (b) 512

from the main memory when the previous (c) 128 (d) 256

173. In order to generate continuous square wave 178. The number of 256 × 4 bits RAM

chips

using 8254 timer, it must be programmed in required to get 1 K Byte of memory size is

(a) mode 0 (b) mode 1 (a) 1 (b) 8 (c) mode 2 (d) mode 3 (c) 4 (d) None

2. Ans. (b) : Handshaking mode of asynchronous data

130. For 16 bit address- but, if an 8K RAM chip is

transfer-

selected when A , A and A address bits are

13 14 15 ? The clock rates for sender and receiver may be

all one, then what is the range of the memory

address? quite different.

(a) E000H-EFFFH (b) E000H-FFFFH ? The sender needs to know whether the receiver has (c)

F000H-FFFFH (d) F000H-FEEEH received the information.

149. The appropriate return addresses are obtained Ans. (a) : In an 8085 microprocessor, the

instructions

with the help of ?????? in case of nested CMP B has been excuted while the content of the

routines. accumulator is less than that of register B. As a result

(a) Memory Address Register carry flag will be set but zero flag will be reset. (b) Memory Data

Register

153. The contents of accumulator after the (c) Buffers

 Multiple Choice Questions (MCQs)

execution of following instructions will be? (d) Stack-pointers

74. Which of the following acts as a temporary

69. The maximum number of bytes of instructions

storage location to hold an intermediate result

8086 bus interface unit consists of is:

in mathematical and logical calculations?

(a) 4 bytes (b) 6 bytes

(a) RAM (c) 8 bytes (d) 10 bytes

114. The maximum number of input or output

AND B - 1

devices that can be connected to 8085

AND C - 1

microprocessor are AND D - 1

(a) 8 (b) 16 AND E - 1 (c) 40 (d) 256 AND H - 1

220. Which of the following is not correct? TRAP> RST 7.5>RST 6.5> RST 5.5 > INTR.

(a) Bus is a group of wires 225. The cycle required to fetch and execute an (b) Bootstrap is a

technique or device for load instruction in a 8085 microprocessor is which (c) An instruction is a

set of bits that defines a one of the following?

computer operation. (a) Clock cycle (b) Memory cycle (d) An interrupt signal is required at the

start of (c) Machine cycle (d) Instruction cycle

112. Which of the following instructions of 8085 are

 Multiple Choice Questions (MCQs)

and Store data

the examples of implied addressing?

(d) Fetch instruction, Decode instruction, Read

1. CMA

operands, Execute instruction and Store data

2. IN byte

ESE 2020, 2012

3. RET

Ans. (d) : The basic steps in the instruction cycle-

(a) 1, 2 and 3 (b) 1 and 2 only

? First of all the op-code is fetched by microprocessor (c) 2 and 3 only (d) 1 and 3 only

141. Which one of the following is a non-maskable Ans. (a) : ALE is stand for address latch enable.

ALE is

control signal which is nothing but a positive going

interrupt?

(a) RST 7.5 (b) RST 6.5 pulse generated when a new operation is started by (c) RST 5.5 (d)

TRAP microprocessor so when pulse goes high means ALE=1.

273. The peripheral that belongs to the category of

specific task, package as a unit.

special purpose peripherals is:

(a) Programmable interval timer 279. Which of the following functions is not (b) Programmable

DMA controller performed by a microprocessor ? (c) Programmable interrupt controller (a)

Controlling timing of information flow (d) Programmable keyboard and display interface (b)

Performing the computing tasks specified in

 Multiple Choice Questions (MCQs)

8086. 271. The condition for 8086 microprocessor to work

as multiprocessor system is: 277. Which of the following instructions are not

used by the 8080 MPU?

(a) M/IO is high (b) M/IO is low

(a) RIM, STA (b) SIM, STA (c) MN/MX is low (d) MN/MX is high (c) STA, XCHG (d) RIM,

SIM

55. How many and which types of machine cycles

are needed to execute PUSH PSW by an Intel popped out and assigned to the program counter

and the

8085 A microprocessor? program counter begins at the new address when RET

(a) 2; Fetch and Memory write instruction is executed by any subroutine. (b) 3; Fetch and 2

Memory write 59. 8086 has maximum clock frequencies ranging (c) 3; Fetch and 2 Memory read

from: (d) 3; Fetch, Memory read and Memory write (a) 5 MHz - 8 MHz (b) 6 MHz - 10 MHz

232. A shift register is operating/connected with 100

various mathematical and logical operation. For kHz clock. The time taken to feed the 2 bytes of

example in the process of adding two 8-bit numbers one data serially in to it is-

number may be in an accumulator and the other in a (a) 2 µsec (b) 80 µsec

memory or register. The result of mathematical (c) 160 µsec (d) 16 µsec

operations are stored in the accumulator. This Resistor BSNL TTA 28.09.2016, 3 PM

is called A and it is also represented by ACC. Ans. (c) Given, f=100 kHz = 100 × 103 Hz

228. The number of first practical microprocessor 2 byte = 16 bit, t = ?

was? ?T = 1 = 1 =10?5

(a) Intel 4004 (b) M 6800 f 100×103 (c) Intel 8080 (d) Intel 4001 T =10µs
 Multiple Choice Questions (MCQs)

135. Handshaking mode of data transfer is

Ans. (d) : RET is the instruction used to mask the end

(a) Synchronous data transfer

of sub routine. It has no parameter after execution of (b) Asynchronous data transfer

this instruction program control is transferred back to (c) Interrupt driven data transfer

main program from where it had stopped. A value of PC (d) Level mode of DMA data transfer

274. The relation among IC (instruction cycle), FC

BSNL TTA 25.09.2016, 3:00 P.M.

(Fetch cycle) and EC(execute cycle) is

(a) IC = FC-EC (b) IC = FC+EC Ans : (d) Storing results and data are not performed by (c) IC =

FC+2EC (d) EC=IC+FC the microprocessor. Microprocessor is a multi purpose

80. NMI stands for in ROM. ROMs are used in microcontroller security

(a) Non-mask interface systems. ROM is non volatile memory. In ROM data (b) Non-maskable

interrupt stored permanently. (c) Non-mask interaction 85. In 8085 microprocessor, how many

interrupts (d) None of there are maskable?

262. Number of address lines necessary to connect

ESE-2015

8K memory chip is

(a) 10 (b) 11 Ans. (c) : During T-state contents of OP-code from

(c) 12 (d) 13 memory are loaded into IR (instruction register) then

155. To execute the following instructions Ans. (b) : NMI input is an edge triggered and positive

(i) LDA 2100H

edge i.e. 0 to 1 transition.

 Multiple Choice Questions (MCQs)

(ii) LXIH, 2100H

In computing, a non-maskable interrupt (NMI) is a

By an Intel 8085 microprocessor the numbers

hardware that can not ignore standard interrupt masking

of memory cycles required are

(a) 2 for (i) and 2 for (ii) technology in the system. This usually indicates (b) 4 for (i) and 2 for (ii)

attention to non-recoverable hardware error. (c) 3 for (i) and 3 for (ii) 159. An example of

8085-instruction that uses direct (d) 4 for (i) and 3 for (ii) addressing is

266. Cache memory is inserted between-

directives which are provided by the assembler tools. (a) The memory and CPU

All pseduo instructions are 2-5 letters in length and they (b) The secondary storage and main

memory

varied from version to version of assembler. (c) The archival storage and secondary storage

261. Which of the following statement is true? (d) The secondary storage and CPU

(a) The group of machine cycle is called state

BSNL TTA 26.09.2016, 3 PM (b) A machine cycle consists of one or more

instruction cycles Ans : (a) Cache memory is used to reduce the average (c) An instruction cycle is

made up of machine time to access data from main memory. It is inserted

cycles and a machine cycle is made up of between main memory and CPU. The size of cache

number of states memory is much smaller than main memory. (d) All of these 267. During which

T-state, contents of OP code

115. The contents of the accumulator and register C

? RST 7.5 can reset without executing ISR for RST 7.5 are 2EH and 6CH respectively. The
 Multiple Choice Questions (MCQs)

instruction

? If bit D in accumulator is one then contain of bit D ADD C is used. The values of AC and P flags

67

are copies on SOD pin. are

(a) 0 and 0 (b) 1 and 1 (c) 0 and 1 (d) 1 and 0

139. Both the ALU and control section of CPU 144. Which of the following are 3 byte

instruction set?

employ which special purpose storage (a) MVI A, 32 H (b) JMP 2085 H

locations? (c) MOV C, A (d) ADD B

(a) Buffers (b) Decoders UKPSC JE 2013, PAPER-I (c) Accumulators (d) Registers Ans. (b) :

MVIA, 32 H ? 2 byte instruction

61. In 8086, single step interrupt belongs to: = 216 × 8 bits

(a) TYPE-1 (b) TYPE-2 = 26 × 210 × 8 bits (c) TYPE-3 (d) TYPE-4 = 25 × 210 × 2 × 8

bits

83. In a microprocessor, op- code fetch cycle is?

Parity flag P = 0 i.e. odd parity (a) Last part of instruction cycle

(b) First part of instruction cycle

Auxiliary carry = 1

(c) Intermediate part of instruction cycle

Zero flag = 0

(d) Data reception through bus

Sign flag = 1 i.e., at MSB

 Multiple Choice Questions (MCQs)

ISRO TA 2016

79. If 8255 a chip is selected when A to A bits are

2 7 ESE -2011, 2008

all 1, what is the address of port A?

Ans. (b) : The op-code fetch cycle, fetches the instruction

(a) 80 (b) FA

from memory and delivers it to the instruction register of (c) FB (d) FC

235. Which components are NOT found on chip in a

fetch and execute state. In the fetch operation, the

microprocessor but may be found on chip in a

microprocessor takes the address of the first byte of the

microcontroller?

instruction to the address bus with a control signal and (a) SRAM and USART

reads the instruction from the memory location. Execute (b) EPROM and PORTS

operation after receiving all instructions, the (c) EPROM, USART and PORTS

microprocessor finishes the tasks given in these special (d) SRAM, EPROM and PORTS

instructions. This process is called execution.

ESE-2011

Electronics-II 896 YCT

Ans. (c) : Erasable programmable that PROM, which Ans. (a) In Direct Memory Access (DMA)

transfer, the

can be erased by ultraviolet rays and can be DMA controller sends a DMA request to the CPU,

in

reprogrammed, is called EPROM. To erase the EPROM response to which CPU puts all its
 Multiple Choice Questions (MCQs)

address, data and

control bus lines in the high impedance states. The

the chip is removed from the circuit and ultraviolet rays

DMA controller can then transfer data directly between

are injected into it for some time.

device and memory without CPU intervention. Clearly,

USART- USART stands for universal synchronous,

it is more suitable for devices with high data transfer

Asynchronous Receiver Transmitter. it is some times rates like hard disk.

called the serial communication Interface or SCI. The

239. The output data lines of microprocessors and

must common use of the USART in asynchronous

memories are usually tristated because

made is to communicate to a PC serial port using the (a) More than one device can transmit

RS-232 Protocol. information over the data bus by enabling

236. If CS = A A A is used as the chip select only one device at a time

15 14 13 (b) More than one device can transmit over the

logic of a 4K RAM in an 8085 system, then its

data bus at the same time.

memory range will be- (c) The data lines can be multiplexed for both

(a) 3000 H - 3 FFF H input and output (b) 7000 H - 7 FFFH (d) It increases the speed of data

transfer over the (c) 5000 H - 5 FFF H and 6000 H - 6 FFF H data bus (d) 6000 H - 6 FFF H and

7000 H - 7 FFF H ESE-2011

14. In an 8085 microprocessor, after the execution

 Multiple Choice Questions (MCQs)

of XRA A instruction Ans. (c) : A programmable ROM has a decoder at the

(a) the carry flag is set input and OR gates at the output with only the latter (b) the accumulator

contains FFH block being programmable. (c) the zero flag is set 20. In 8085, if the clock

frequency is 5 MHz, the (d) the accumulator contents are shifted left by time required to execute an

instruction of 18 T-

16. BSNL TTA (JE) 25.09.2016, Shift-I

Ans. (d) : Programmable logic array (PLA) uses ROM 169. A microprocessor is call ed an 'n-bit

microprocessor' depending on-

matrices. The desired output for each combination of

(a) Register length

input is programmed into the ROM, with the input (b) Size of the internal data bus.

loaded into address bus and read as output data. (c) Size of external data base

Programmable connection for both AND and OR arrays (d) None of these

36. ____________ is used to store program codes Ans. (a) :

(a) System memory (b) Data memory (cid:2) The flag register is the status register that contains

(c) User memory (d) Executive memory the current status of CPU. The size and meanings of

86. The power failure alarm must be connected to (c) selecting which peripheral should be

which of the following inputs of 8085? addressed

(a) RST 7.5 (b) TRAP (d) Storing instructions (c) INTR (d) HOLD (e) for carrying out logical

operations

89. In a µP based system, the stack is always in Ans. (a) : In 8085 Instruction set LDA is a

mnemonic

(a) µP (b) RAM that stands the contents of a memory location, specified (c) ROM (d) EPROM by
 Multiple Choice Questions (MCQs)

a 16-bit address in the operand, are copied to the