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DEPARTMENT
OF
ELECTRONICS AND COMMUNICATION ENGINECRING

EC204RI
DIGITAL SYSTEM DESIGN LABORATORY

LAB INSTRUCTIONS FOR CARRYING OUT PRACTICAL

ON

EXPERIMENT NO - 11

UP/DOWN COUNTER

BIRLA INSTITUTEOF TECHNOLOGY

MESRA RANCHI
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AIN: Design a pre scttable up and downcounter

Detailed objectivc of the cxperimcnt:
ii) Design abinary up and down counter uslng IC
iv)Design a pre settable up and down counter for any randorn preset
value
APPARATUS REQUIRED:
1. Wish board or Trainer Kit.
2. D.C.Power Supply
3, C.R.0.
CIRCUIT COMPONENTS:
1, CD4029 Decade counter 1C4029

PIN DIAGRAM:

CD4029BMS
TOP VIEW

PRESET ENABLE1|
16] VOD
Q4
2 |15) CLOCK

JAH4|3

JAM 1|4| 13 JAM 3

CARRY IN 5 12 JAM 2

Q16 11| 02
CARRY
OUT7 |10| UPIDOWN

VSS8| 9BINARYIDECADE

THEORY:
Up-Dowvn Counter. Counters are used in many different applications. Some count
up from zero and provide a change in state output upon reaching a predetermined value:
of

others count down fronn a preset value to zero to provide an output. state change.
The counters are synchronous, but they are asynchronously pre settable. In this experiment
vOu will use IC CD 4029 and implement following counter configurations.

i. 4 bit Binary UP Counter

ii. 4 bit Binary DOWN Counter

ii. 4 bit Binary UP Counter with preset value
iv. 4 bit Binary Down Counter with preset valuc
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Description of IC4029
CO4029BMS consisls of a lour-slage binary or BCD-decade up
down counler wilh provisions lor look-uhead carry in bolh count
ing modes. The inpuls cornsisl o a stgle CLOCK. CARRY-IN
(CLOCK ENABLE), BINARY:DECADE. UPIDOVN, PRESETa
ENABLE, and lour individuat JAM sienals. O1. O2, 03.Q4 and
CARRY OUT signal are provIded as culputs.
A high PRESET ENABLE signal allos inforation or he JAM
INPUTS to presel he counter to any stale asynchronoUsly wih
the clOck. A low on each JANM ie when he PRESET-ENABLE
SIgngl is high, tesels the counter to its zero coLInL The counter is
of he clock v/hen
advanced one cunt at the pOsitive Lransi l'on signals
the CARRY-JN nd PRE-SET ENABLE are iow.
CARRY-IN or PRESET
Advancement is inhibiled vhen the is normally
ENABLE signa!s are high. The CARRY-OUT sIgnal
high and goes loyv when the courler reaches ils maxinum
cOunt
in the UP mode or the mínirTIuI cOunL in the DOWN node pro
vided the CARRY-IN signal is lov. The CARRY-IN signai in the
a CLOGK ENABLE. The
low sale can hus be consicered in Use.
CARRY-IN lerinal must be cornecled lo VSS zhen nol
is accoTplisted wien the BINARYIDECADE
Binary couiing
inpul is high; the cOunter courls
un
the decade TYOde when he
BINARY/DECADE lnput is low. The counler counts
up when the
the UP/DONN nput is
UP/DOWN input is high, and down when in
Iow. Muliple packages can be connected either a parallel
arrargemenl as shown inFigure 17.
docking or a ripple-clocking
syncronoS Control and hence fasler
Paralel clocking pIvides for
respornse fiom all counng outpuls. Ripple-clocking allos
tumes.
longer cdock uipuL rise and fail
The CD4029BMS is supplied in these 16-lead oulline packages:
Braze Seal DIP H4X
Frit Seal DIP HIF
Flatpack HGW
Ceraic
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Functional Diagram
JAJA INPUTS
PRESET
ENABLE VDD
123 4

CARRY IN
(CLOCK 16
ENABLE) 6 6Q1

BINARYI
DECADE
1s 2
9

IC CD BUFFERED
4029 OUTPUTS
UP:DOWN 10
04

CLOCK 15

CARRY
OUT
VSS

PROCEDURE:
1. Fix the IC's on the bread board.
2. Make connections according to the circuit.
3. Give the external Clock signal
IC4029 HIGH for binary counting.
4. Make Binary/ Decade input (pin9) of the
For binary UP Counter
IC4029 HIGH for UP-Counting.
5. Make UP/ Down input (pinl0) the
of

6 Observe the output Ql, Q2, Q3, Q4.

7. Verifythe truth table of the binary UP-Counter
For binary DOWN Counter
of the IC4029 LOW for DOWN-Counting.
8. Make UP/ Down input (pin10)
9. Observe the output Ql, Q2, Q3, Q4.
DOWN-Counter
10. Verify the truth table of the binary
Counter
For Pre-settable binarv UP/DOWN
HIGH.
II. Make Preset input of the IC4029
to the JAM inputs (pin 4, 12, 13, 3).
12. For presetting, apply any random value
13. Repeat steps 5 -7 for
up counting.
counting.
14. Repeat steps 8 -10 for down

OBSERVATION TABLE:
are connected to 5V)
A. Binary UP Counter (Pin 9 & 10
a. Truth table for /UP/DOWN Counter

Clock
Q4 Q3 02 Q1

3
4
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Functional Diagram
JAM INPUTS
PRESET
ENABLE 3 4 VDD
1 2
CARRY IN
16
(LOCK
ENABTE) 5 l6 Q1

BINARYI Q2
11
0ECADE 9

IC CD 14 Q3
BUFFERED
4029 OUTPUT7S
UP/DOWN 10
04

CLOCK 15

CARRY
OUT
yss

PROCEDURE:
Fix the 1C's on the bread board.
2 Make connections according to the circuit.
3. Give the external Clock signal
4 Make Binary/ Decade input (pin9) of the 1C4029 HIGH for binary counting.
For binary UP Counter
5. Make UP/ Down input (pinl0) of the IC4029 HIGH for UP-Counting.
6. Observe the output Q1, Q2, Q3, Q4.
7. Verify the truth table ofthe binary UP-Counter
For binary DOWVN Counter
8. Make UP/ Down input (pin10) of the IC4029 LOW for DOWN-Counting.
9. Observe the output Q1, Q2, Q3, Q4.
10. Verify the truth table of the binary DOWN-Counter
For Pre-settable binary UP/DOWN Counter
11. Make Preset input ofthe 1C4029 HIGH.
12. For presetting, apply any randon value to the JAM inputs (pin 4, 12, 13, 3).
13. Repeat steps 5 -7 for up counting.
14. Repeat steps 8 -10 for down counting.

OBSERVATION TABLE:
A. Binary UP Counter (Pin 9 10 are connecied to 5V)
&

a. Truth table for /UP/DOWNCounter

Clock
Q4 Q3 Q2 Ql

4
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10

12
13
14
15
16

Counter
B. Truth table for Pre-settable UP/DOWN
i) Value of the NAM Signal=

Clock
Q4 Q3 Q2 Q1
1

2
3
4
5
6
7
8

10

12
13
14
15

RESULTS& DISCUSSION:

CONCLUSION:

PRECAUTION: pin diagram

a) Make the conncctions according to the IC
b) The connection should be tight
c The Voc and ground should be applied carefully at the specified pins only.

DESIGN TASK: Design a non-binary up/down asynchronous counter,