ultraviolet light into the chip through a window provided for that purpose, or by the

application of a high voltage similar to that used in a write operation. If ultraviolet light is
used, all cells in the chip are erased at the same time. When electrical erasure is used,
however, the process can be made selective. An electrically erasable EPROM, often
referred to as EEPROM. However, the circuit must now include high voltage generation.

Some EEPROM chips incorporate the circuitry for generating these voltages o the chip
itself. Depending on the requirements, suitable device can be selected.

Flash memory:

 Has similar approach to EEPROM.

 Read the contents of a single cell, but write the contents of an entire block
of cells.

 Flash devices have greater density.

▪ Higher capacity and low storage cost per bit.

 Power consumption of flash memory is very low, making it attractive for

 Single flash chips are not sufficiently large, so larger memory modules are
implemented using flash cards and flash drives.

(REFER slides for point wise notes on RoM and types of ROM)

5.4 Speed, Size and Cost

Static RAM: Very fast, but expensive, because a basic SRAM cell has a complex circuit
making it impossible to pack a large number of cells onto a single chip.

Dynamic RAM: Simpler basic cell circuit, hence are much less expensive, but
significantly slower than SRAMs.

Magnetic disks: Storage provided by DRAMs is higher than SRAMs, but is still less than
what is necessary. Secondary storage such as magnetic disks provides a large amount of
storage, but is much slower than DRAMs.
Fastest access is to the data held in processor registers. Registers are at the top of the
memory hierarchy. Relatively small amount of memory that can be implemented on the
processor chip. This is processor cache. Two levels of cache. Level 1 (L1) cache is on the
processor chip. Level 2 (L2) cache is in between main memory and processor. Next level
is main memory, implemented as SIMMs. Much larger, but much slower than cache
memory. Next level is magnetic disks. Huge amount of inexpensive storage. Speed of
memory access is critical, the idea is to bring instructions and data that will be used in the
near future as close to the processor as possible.
5.5 Cache memories
Processor is much faster than the main memory. As a result, the processor has to spend
much of its time waiting while instructions and data are being fetched from the main
memory. This serves as a major obstacle towards achieving good performance. Speed of
the main memory cannot be increased beyond a certain point. So we use Cache
memories. Cache memory is an architectural arrangement which makes the main memory
appear faster to the processor than it really is. Cache memory is based on the property of
computer programs known as “locality of reference”.

Analysis of programs indicates that many instructions in localized areas of a program are
executed repeatedly during some period of time, while the others are accessed relatively
less frequently. These instructions may be the ones in a loop, nested loop or few
procedures calling each other repeatedly. This is called “locality of reference”. Its types
are:

Temporal locality of reference: Recently executed instruction is likely to be executed

Spatial locality of reference: Instructions with addresses close to a recently instruction

A simple arrangement of cache memory is as shown above.

• Processor issues a Read request, a block of words is transferred from the main
memory to the cache, one word at a time.

• Subsequent references to the data in this block of words are found in the cache.

• At any given time, only some blocks in the main memory are held in the cache.
Which blocks in the main memory are in the cache is determined by a “mapping
function”.
 • When the cache is full, and a block of words needs to be transferred from the main
memory, some block of words in the cache must be replaced. This is determined
by a “replacement algorithm”.

Cache hit:

Existence of a cache is transparent to the processor. The processor issues Read and
Write requests in the same manner. If the data is in the cache it is called a Read or Write
hit.

Read hit: The data is obtained from the cache.

Write hit: Cache has a replica of the contents of the main memory. Contents of the cache
and the main memory may be updated simultaneously. This is the write-through protocol.

Update the contents of the cache, and mark it as updated by setting a bit known as the
dirty bit or modified bit. The contents of the main memory are updated when this
block is replaced. This is write-back or copy-back protocol.

Cache miss:

• If the data is not present in the cache, then a Read miss or Write miss occurs.

• Read miss: Block of words containing this requested word is transferred from the
memory. After the block is transferred, the desired word is forwarded to the
processor. The desired word may also be forwarded to the processor as soon as it
is transferred without waiting for the entire block to be transferred. This is called
load-through or early-restart.

• Write-miss: Write-through protocol is used, then the contents of the main memory
are updated directly. If write-back protocol is used, the block containing the
addressed word is first brought into the cache. The desired word is overwritten
with new information.

Cache Coherence Problem:

A bit called as “valid bit” is provided for each block. If the block contains valid data, then
the bit is set to 1, else it is 0. Valid bits are set to 0, when the power is just turned on.

When a block is loaded into the cache for the first time, the valid bit is set to 1. Data
transfers between main memory and disk occur directly bypassing the cache. When the
data on a disk changes, the main memory block is also updated. However, if the data is
also resident in the cache, then the valid bit is set to 0.

The copies of the data in the cache, and the main memory are different. This is called the
cache coherence problem
Mapping functions: Mapping functions determine how memory blocks are placed in the
cache.

A simple processor example:

 Cache consisting of 128 blocks of 16 words each.

Three mapping functions can be used.

1. Direct mapping
2. Associative mapping
3. Set-associative mapping.
 Main
memory Block 0 •Block j of the main memory maps to j modulo 128 of
Block 1
the cache. 0 maps to 0, 129 maps to 1.
Cache
tag
•More than one memory block is mapped onto the same
Block 0 position in the cache.
tag •May lead to contention for cache blocks even if the
Block 1
cache is not full.
Block 127
•Resolve the contention by allowing new block to
Block 128 replace the old block, leading to a trivial replacement
tag
Block 127 Block 129
algorithm.
•Memory address is divided into three fields:
- Low order 4 bits determine one of the 16
words in a block.
- When a new block is brought into the cache,
Block 255 the the next 7 bits determine which cache
Tag Block Word
5 7 4 Block 256 block this new block is placed in.
- High order 5 bits determine which of the possible
Main memory address Block 257
32 blocks is currently present in the cache. These
are tag bits.
•Simple to implement but not very flexible.
Block 4095
 Main Block 0
memory

Block 1
•Main memory block can be placed into any cache
Cache
tag
position.
Block 0 •Memory address is divided into two fields:
tag
Block 1 - Low order 4 bits identify the word within a block.
- High order 12 bits or tag bits identify a memory
Block 127
block when it is resident in the cache.
Block 128 •Flexible, and uses cache space efficiently.
tag
Block 127 Block 129
•Replacement algorithms can be used to replace an
existing block in the cache when the cache is full.
•Cost is higher than direct-mapped cache because of
the need to search all 128 patterns to determine
whether a given block is in the cache.
Block 255
Tag Word
12 4 Block 256

Main memory address Block 257

Block 4095
 Cache
Main Block 0 Blocks of cache are grouped into sets.
memory
tag Block 0 Mapping function allows a block of the main
Block 1
tag
memory to reside in any block of a specific set.
Block 1
Divide the cache into 64 sets, with two blocks per set.
tag Block 2 Memory block 0, 64, 128 etc. map to block 0, and they
tag Block 3 can occupy either of the two positions.
Block 63 Memory address is divided into three fields:
Block 64 - 6 bit field determines the set number.
tag - High order 6 bit fields are compared to the tag
Block 126 Block 65
fields of the two blocks in a set.
tag
Block 127 Set-associative mapping combination of direct and
associative mapping.
Number of blocks per set is a design parameter.
Tag Block Word
Block 127 - One extreme is to have all the blocks in one set,
Block 128 requiring no set bits (fully associative mapping).
5 7 4
- Other extreme is to have one block per set, is
Block 129
Main memory address the same as direct mapping.

Block 4095