Computer organization and

architecture

Chapter 6:
Central Processing Unit
 outlines

 Introduction
 General Register Organization
 Stack Organization
 Instruction Formats
 Addressing Modes
 Data Transfer and Manipulation
 Program Control
 Reduced Instruction Set Computer (RISC) vs Complex
instruction set computer
(CISC)
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 CPU
 CPU performs the data processing operations in a
computer.
 The CPU is made up of three major parts.
A. The register set stores intermediate data used during the
execution of the instructions.
B. The arithmetic logic unit (ALU) performs the
required microoperations for executing the
instructions.
C. The control unit supervises the transfer of
information among the registers and instructs the
ALU as to which operation to perform.
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MAJOR COMPONENTS OF CPU

Figure :Major components of CPU.

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 General Register Organization
 memory locations are needed for storing pointers, counters,
return addresses, temporary results, and partial products
during multiplication.
 Having to refer to memory locations for such applications is
time consuming because memory access is the most time-
consuming operation in the computer.
 it is more convenient and more efficient to store these
intermediate values in processor registers.
 When a large number of registers are included in the CPU, it
is most efficient to connect them through a common bus
system.
 The registers communicate with each other not only for direct
data transfers, but also while performing various
microoperations. 5
GENERAL REGISTER ORGANIZATION …cont’d
Clock Input

R1
R2
R3
R4
R5
R6
R7
Load
(7 lines)
SELA { MUX MUX } SELB
3x8 A bus B bus
decoder

SELD
OPR ALU

Output
3 3 3 5
SELA SELB SELD OPR

Figure: bus organization for seven CPU registers.

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 OPERATION OF CONTROL UNIT
The control unit directs the information flow through ALU by:
- Selecting various Components in the system
- Selecting the Function of ALU

Example: R1 <- R2 + R3
[1] MUX A selector (SELA): BUS A  R2
[2] MUX B selector (SELB): BUS B  R3
[3] ALU operation selector (OPR): ALU to ADD
[4] Decoder destination selector (SELD): R1  Out Bus
3 3 3 5
Control Word SELA SELB SELD OPR

Encoding of register selection fields

Binary
Code SELA SELB SELD
000 Input Input None
001 R1 R1 R1
010 R2 R2 R2
011 R3 R3 R3
100 R4 R4 R4
101 R5 R5 R5
110 R6 R6 R6
111 R7 R7 R7
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 Control

ALU CONTROL
Encoding of ALU operations OPR
Select Operation Symbol
00000 Transfer A TSFA
00001 Increment A INCA
00010 ADD A + B ADD
00101 Subtract A - B SUB
00110 Decrement A DECA
01000 AND A and B AND
01010 OR A and B OR
01100 XOR A and B XOR
01110 Complement A COMA
10000 Shift right A SHRA
11000 Shift left A SHLA

Examples of ALU Microoperations

Symbolic Designation
Microoperation SELA SELB SELD OPR Control Word
R1  R2 - R3 R2 R3 R1 SUB 010 011 001 00101
R4  R4  R5 R4 R5 R4 OR 100 101 100 01010
R6  R6 + 1 R6 - R6 INCA 110 000 110 00001
R7  R1 R1 - R7 TSFA 001 000 111 00000
Output  R2 R2 - None TSFA 010 000 000 00000
Output  Input Input - None TSFA 000 000 000 00000
R4  shl R4 R4 - R4 SHLA 100 000 100 11000
R5  0 R5 R5 R5 XOR 101 101 101 01100
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 Stack organization
 A stack is a storage device that stores information in such a
manner that the item stored last is the first item retrieved
(LIFO).
 The register that holds the address for the stack is called a
stack pointer (SP) because its value always points at the top
item in the stack.
 The physical registers of a stack are always available for
reading or writing
 The two operations of a stack are the insertion (push) and
deletion (pull) of items.

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 Example for stack
Stack of cafeteria plates

CDs in CD Container

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Push operation(insertion)

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Pop operation (deletion)

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 Stack organization cont’’’d
 There are two types of stack organization
1. Register stack – built using registers
2. Memory stack – logical part of memory allocated as stack

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REGISTER STACK ORGANIZATION
 A stack can be placed in a portion of a large memory or it can be
organized as a collection of a finite number of memory words or
registers.
 The SP register contains a binary number whose value is equal to
the address of the word that is currently on top of the stack.
 In a 64-word stack, the stack pointer contains 6 bits because
26 = 64.
 Since SP has only six bits, it cannot exceed a number greater than
63 (111111 in binary).
 Figure below shows the organization of a 64-word register stack.

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 REGISTER STACK ORGANIZATION
 The one-bit register FULL is set to 1 when the stack is full, and the
one-bit register EMTY is set to 1 when the stack is empty of items.
 DR is the data register that holds the binary data to be written into or
read out of the stack.
Register Stack
stack Address
63
Flags
FULL EMPTY

Stack pointer 4
SP C 3
B 2
A 1
Push, Pop operations 0
DR
/* Initially, SP = 0, EMPTY = 1, FULL = 0 */

PUSH POP
SP  SP + 1 DR  M[SP]
M[SP]  DR SP  SP - 1
If (SP = 0) then (FULL  1) If (SP = 0) then (EMPTY  1)
EMPTY  0 FULL  0
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memory STACK ORGANIZATION
 A stack can be implemented in a random-access memory attached to a
CPU.
 The implementation of a stack in the CPU is done by assigning a
portion of memory to a stack operation and using a processor
register as a stack pointer.
 The program counter PC:-
 points at the address of the next instruction in the program
 used during the fetch phase to read an instruction.
 The Address register (AR):- points at an array of data
 used during the execute phase to read an operand.
 The stack pointer SP:- points at the top of the stack and used to push
or pop items into or from the stack.
 assume that the items in the stack communicate with a data register
DR.
 Figure shows a portion of computer memory partitioned into three 16
segments: program, data, and stack.
 memory STACK ORGANIZATION
1000
Program
Memory with Program, Data, PC (instructions)
and Stack Segments
Data
AR (operands)

SP 3000
stack
3997
3998
3999
4000
- A portion of memory is used as a stack with a 4001
processor register as a stack pointer DR

- PUSH: SP  SP - 1
M[SP]  DR
- POP: DR  M[SP]
SP  SP + 1

- Most computers do not provide hardware to check

stack overflow (full stack) or underflow(empty stack)
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 Reverse Polish Notation
 The common mathematical method of writing arithmetic
expressions imposes difficulties when evaluated by a computer.

 The common arithmetic expressions are written in infix notation.

 The Polish mathematician Lukasiewicz showed that arithmetic
expressions can be represented in prefix notation as well as postfix
notation.
Infix Prefix or Polish Postfix or reverse Polish
A+B + AB AB +

A*B+C*D AB * CD * +
Reverse Polish
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 INSTRUCTION FORMAT
 The bits of the instruction are divided into groups called fields.
 The most common fields found in instruction formats are:

 OP-code field - specifies the operation to be performed

 Address field - designates memory address(s) or a processor
register(s)
 Mode field - specifies the way the operand or the effective
address is determined
 Instructions are categorized into different formats with respect to the
operand fields in the instructions.
1. Three Address Instructions
2. Two Address Instruction
3. One Address Instruction
4. Zero Address Instruction
5. RISC Instructions 19
 THREE ADDRESS INSTRUCTIONS
 Computers with three-address instruction formats can use each
address field to specify either a processor register or a memory
operand.
 Example:-The program in assembly language that evaluates
 X = (A + B) * (C + D) is shown below.
ADD R1, A, B R1← M[A]+ M[B]
ADD R2, C, D R2← M[C]+ M[D]
MUL X, R1, R2 M[X]← R1 * R2
 The advantage of three-address format is that it results in short
programs when evaluating arithmetic expressions.
 The disadvantage is that the binary-coded instructions require too
many bits to specify three addresses.

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 TWO-ADDRESS INSTRUCTIONS
 Two address instructions are the most common in commercial
computers.
 Here again each address field can specify either a processor
register or a memory word.
 Example:- The program to evaluate X = (A + B) * (C + D) is as
follows: MOV R1, A R1← M[A]
ADD R1, B R1← R1+ M[B]
MOV R2, C R2← M[C]
ADD R2, D R2← R2+ M[D]
MUL R1, R2 R1← R1 * R2

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ONE ADDRESS INSTRUCTIONS
 use an implied accumulator (AC) register for all data manipulation.
 For multiplication and division these is a need for a second register.
 However, here we will neglect the second register and assume that
the AC contains the result of all operations.
 Example;- The program to evaluate X = (A + B) * (C + D) is

LOAD A AC← M[A]

ADD B AC← AC+M[B]
STORE T M[T]←AC
LOAD C AC← M[C]
ADD D AC← AC+M[D]
MUL T AC← AC*M[T]
 All operations are done between the AC register and a memory
operand.
 T is the address of a temporary memory location required for storing
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the intermediate result.
 ZERO-ADDRESS INSTRUCTIONS
 A stack-organized computer does not use an address field for the
instructions ADD and MUL.
 The PUSH and POP instructions, however, need an address field to
specify the operand that communicates with the stack.
 To evaluate arithmetic expressions in a stack computer, it is
necessary to convert the expression into reverse polish notation.
 The program to evaluate X = (A + B) * (C + D) will be written for a
stack-organized computer.
PUSH A TOS← M[A]
PUSH B TOS← M[B]
ADD TOS←(A+B)
PUSH C TOS← M[C]
PUSH D TOS← M[D]
ADD TOS←(C+D)
MUL TOS←(C+D)*(A+B)
POP X M[X] ← TOS
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 Addressing Mode
 The addressing mode specifies a rule for interpreting or modifying
the address field of the instruction before the operand is actually
referenced.
 The job of a microprocessor is to execute a set of instructions
stored in memory to perform a specific task.
 Operations require the following:
1. The operator or opcode which determines what will be done
2. The operands which define the data to be used in the operation
 For example, if we wanted to add the numbers 1 and 2 and get a
result, mathematically we would likely write this as 1 + 2. In this
case, our operator is (+), or the addition, and our operands are the
numbers 1 and 2.

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 Addressing Mode ….cont’d
 In a microprocessor, the machine needs to be told how to get the
operands to perform the operation.
 The effective address is a term that describes the address of an
operand that is stored.
 in memory. There are several methods to designate the effective
address of those operands or get them directly from the register.
 The method of specifying source of operand and output of result in
an instruction is known as addressing mode.
 Computers use addressing mode techniques for the purpose of
accommodating one or both of the following provisions:
 to give programming flexibility to the user
 to use the bits in the address field of the instruction efficiently

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 Types of addressing modes
 The way the operands are chosen during program execution is
dependent on the addressing mode of the instruction.
 There are various methods of giving source and destination
address in instruction,
 thus there are various types of Addressing Modes. These are:-
1. Implied Mode
2. Immediate Mode
3. Direct Address Mode
4. Indirect Address Mode
5. Register Mode
6. Register Indirect Mode

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 Implied addressing mode

 In implied addressing the operand is specified in the instruction

itself.
 In this mode the data is 8 bits or 16 bits long and data is the part of
instruction.
 Zero address instruction are designed with implied addressing mode.

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 Immediate Addressing Mode
 According to this addressing mode, the value of the operand is (immediately)
available in the instruction itself.
 In other words, an immediate mode instruction has an operand field
rather than an address field. The operand field contains the actual
operand to be used in conjunction with the operation specified in the
instruction.
 Operand is part of instruction
 Operand = operand field

opcode operand

Data is directly stored

here

 No memory reference to access data and it is fast

 Range of operands limited to # of bits in operand field (< word size) 28
 Direct Addressing Mode
 According to this addressing mode, the address of the memory
location that holds the operand is included in the instruction.
 Instruction specifies the memory address which can be used directly
to the physical memory
 Faster than the other memory addressing modes
 Too many bits are needed to specify the address for a large physical
memory space

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 Indirect Addressing Mode

In the indirect mode, what is included in the instruction is not the
address of the operand, but rather a name of a memory location that
holds the (effective) address of the operand.
Memory cell pointed to by address field contains the
address of (pointer to) the operand
opcode address A
MEMORY

A c

C operand

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 Register Addressing Mode:
 In this addressing mode, the source of data or destination of result is
Register.
 In this type of addressing mode the name of the register is given in the
instruction where the data to be read or result is to be stored.

 Advantages:
 Very small address field
 Shorter instructions
 Faster instruction fetch
 Faster memory access to operand(s)
• Disadvantage:
– Very limited address space 31
 Register Indirect Addressing Mode:
 as its name suggests the data is read/stored in register indirectly. i.e
 we provide the register in the instruction, in which the address of the
other register is stored or which points to other register where data is
stored or to be stored.
 Operand is in memory cell pointed to by contents of register R

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Data transfer & manipulation instructions
 Most computer instructions can be classified into three
categories:
I. Data transfer instructions
II. Data manipulation instructions
III. Program control instructions

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 Data transfer instructions
 Data transfer instructions move data from one place in the computer to
another without changing the data content.
 The most common data transfers are between:
memory and processor registers,
 processor registers and input or output,
 the processor registers themselves.
Table:- Typical Data Transfer Instructions
Name Mnemonic
Load LD
Store ST
Move MOV
Exchange XCH
Input IN
Output OUT
Push PUSH
Pop POP
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 Data manipulation instructions
 Data manipulation instructions perform operations on data and
provide the computational capabilities for the computer.
 The data manipulation instructions in a typical computer are
usually divided into three basic types:
1. Arithmetic instructions
2. Logical and bit manipulation instructions
3. Shift instructions

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 DATA MANIPULATION INSTRUCTIONS
Arithmetic Instructions
Name Mnemonic
Increment INC
Decrement DEC
Add ADD
Subtract SUB
Multiply MUL
Divide DIV
Add with Carry ADDC
Subtract with Borrow SUBB
Negate(2’s Complement) NEG
Logical and Bit Manipulation Instructions Shift Instructions
Name Mnemonic Name Mnemonic
Clear CLR Logical shift right SHR
Complement COM Logical shift left SHL
AND AND Arithmetic shift right SHRA
OR OR Arithmetic shift left SHLA
Exclusive-OR XOR Rotate right ROR
Clear carry CLRC Rotate left ROL
Set carry SETC Rotate right thru carry RORC
Complement carry COMC Rotate left thru carry ROLC
Enable interrupt EI
Disable interrupt DI

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 program control instruction
 At instruction which alters the sequence of program execution. i.e
 It changes the value of program counter due to the execution of
program changes.
 A program control type of instruction, when executed, may change
the address value in the program counter and cause the flow of
control to be altered.
 The change in value of the program counter as a result of the
execution of a program control instruction causes a break in the
sequence of instruction execution.
 Table:-program control instruction
Name Mnemonic
Branch BR
Jump JMP
Skip SKP
Call CALL
Return RTN
Compare(by - ) CMP
Test (by AND) TST 37
 Micro Processor Architecture
There are two types of micro processors
1. RISC (Reduced Instruction Set Computer)
2. CISC (Complex Instruction Set Computer)
The architecture of a processor helps to get the desired output for a
specific input.
for each instruction in an instruction set, the insides of the
processor have a specific method of operation.
The architecture is essentially the way the hardware of a
processor is configured, placed and positioned on a transistor level.
RISC and CISC are the characterizations of computer instruction
sets which is a part of computer architecture;
they differ in complexity, instruction and data formats,
addressing modes, registers, opcode specifications, and flow
control mechanisms, etc 38
 Reduced Instruction Set Computers (RISC)
Historical Background
IBM System/360, 1964
- The real beginning of modern computer architecture
- Distinction between Architecture and Implementation
- Architecture: The abstract structure of a computer
seen by an assembly-language programmer

Compiler -program
High-Level Instruction
Language Hardware
Set
Architecture Implementation

 It is a type of microprocessor that has a limited number of instructions.

 It can execute their instructions very fast because instructions are very
small and simple.

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 Characteristics of RISC
 Relatively few instructions
 Relatively few addressing modes
 Memory access limited to load and store instructions
 All operations done within the registers of the CPU
 Fixed-length, easily decoded instruction format
 Single-cycle instruction execution
 Hardwired rather than microprogrammed control
 A relatively large number of registers in the processor unit

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COMPLEX INSTRUCTION SET COMPUTERS:
CISC

 A much richer and complicated instruction sets

 High Performance General Purpose Instructions
Characteristics of CISC:
 A large number of instructions (from 100-250 usually)
 Some instructions that performs a certain tasks are not used
frequently.
 Many addressing modes are used (5 to 20)
 Variable length instruction format.
 Instructions that manipulate operands in memory.

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 Difference Between CISC and RISC
RISC CISC
RISC stands for Reduced Instruction Set CISC stands for Complex Instruction Set
Computer Computer.
It has fewer instructions It has more instructions
Less addressing modes. More addressing modes.
RISC requires more RAM CISC requires a minimum amount of RAM
Small Code Size. Large Code Size.
RISC processors have a fixed instruction CISC processors have variable instruction
format format.
Multiple register sets are present Single register set
RISC processors are highly pipelined. CISC processors are not highly pipelined or
less pipelined.
Low power consumption. High power consumption
Focus on software to optimize performance. Focus on hardware to optimize performance.
Uses multiple registers Uses a single register

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 interrupt
• In computer architecture, an interrupt is a signal to the
processor emitted by hardware or software indicating an
event that needs immediate attention.
• An interrupt signal alerts the processor and serves as a request for
the processor to interrupt the currently executing code.

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External interrupts:-
types of interrupt
If the signal for the processor is from external device or
hardware is called hardware interrupts.
External Interrupts initiated from the outside of CPU and Memory
- I/O Device -> Data transfer request or Data transfer complete
- Timing Device -> Timeout
- Power Failure

Internal interrupts (traps)

Internal Interrupts are caused by the currently running program
- Register, Stack Overflow
- Divide by zero
- OP-code Violation
- Protection Violation

Software Interrupts
Both External and Internal Interrupts are initiated by the computer Hardware.
Software Interrupts are initiated by executing an instruction.
- Supervisor Call -> Switching from a user mode to the supervisor mode
-> Allows to execute a certain class of operations
which are not allowed in the user mode
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 thank you!!!
QUESTION??

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