Digital Logic Design DLD Lab Report 1
Digital Logic Design DLD Lab Report 1
Muhammad Faisal
Section: C
Lab Task 1:
(NAND Gate)
A
(A.B)’
B
Inputs
Outputs
A B
0 0 1
0 1 1
1 0 1
1 1 0
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Lab Task 2:
(AND Gate)
A
A.B
B
Inputs
Outputs
A B
0 0 0
0 1 0
1 0 0
1 1 1
Lab Task 3:
(NOT Gate)
A A’
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Input
Output
A
0 1
1 0
Lab Task 4:
(NOR Gate)
A
(A+B)’
B
Inputs
Outputs
A B
0 0 1
0 1 0
1 0 0
1 1 0
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Lab Task 5:
(OR Gate)
A
A+B
B
Inputs
Outputs
A B
0 0 0
0 1 1
1 0 1
1 1 1
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Lab Task 6:
(XOR Gate)
A
A B
B
Inputs
Outputs
A B
0 0 0
0 1 1
1 0 1
1 1 0
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Post Lab:
A
C
F1
F2
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A B C D F1 F2
0 0 0 0 0 0
0 0 0 1 1 1
0 0 1 0 1 0
0 0 1 1 1 1
0 1 0 0 1 1
0 1 0 1 0 1
0 1 1 0 1 1
0 1 1 1 0 1
1 0 0 0 1 0
1 0 0 1 1 1
1 0 1 0 1 0
1 0 1 1 1 1
1 1 0 0 1 0
1 1 0 1 1 1
1 1 1 0 1 0
1 1 1 1 1 1
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