This article can be cited as G. Kaur, S. S. Gill and M.

Rattan, Whale Optimization Algorithm for Performance Improvement of

Silicon-On-Insulator FinFET, International Journal of Artificial Intelligence, vol. 18, no. 1, pp. 63-81, 2020.
Copyright©2020 by CESER Publications

Whale Optimization Algorithm for Performance

Improvement of Silicon-On-Insulator FinFET

Gurpurneet Kaur1, Sandeep Singh Gill2 and Munish Rattan3

1,3
Guru Nanak Dev Engineering College, Ludhiana, Punjab 141006, India;
2
National Institute of Technical Teachers Training and Research, Chandigarh, Punjab,
160019, India;
1
gurpurneetkaur@gmail.com; ssg270870@yahoo.co.in; 3rattanmunish@gndec.ac.in
2

ABSTRACT

Geometry parameters, fin height (HFin) & fin width (WFin), critically affect the performance
of FinFET devices. These parametric variations have been assessed in the present work
by designing silicon-on-insulator (SOI) fin-shaped field effect transistor (FinFET) device
with optimum metrics. In this work, the designed devices show diminished Short channel
effects and ameliorated analog parameters for the different range of HFin /Lg & WFin/Lg
using 3D Visual Technology Computer-Aided Design (TCAD) simulator. Further after
training the artificial neural network with a set of parameters and delineating the fitness
function, genetic algorithm (GA) and Whale optimization algorithm (WOA) have been
implemented. Corresponding to the minimal fitness function, a pair of optimized metrics
has been provided in less time using the weighted sum approach. It is observed that the
taller and wider fins serve the need of high ION, larger intrinsic gain and a better early
voltage whereas narrow fin provides SCEs immunity for device. The results seized
through optimization techniques are in good reconciliation with the results of Physical
device simulator’s with a deviation less than 7%.

Keyword: FinFET, Leakage current, SRAM, Subthreshold Swing, Whale Optimization

Algorithm.

Mathematics Subject Classification: 90C15, 90-80

Computing Classification System: Hardware~Transistors;500, Mathematics of computing~

Evolutionary algorithms;500, Mathematics of computing~ Combinatorial optimization;500.

1. INTRODUCTION

In the era of downscaling, leading Semiconductor companies like Intel, Samsung, TSMC etc are
formulating scaled FinFET (device of a vertical channel with the gate wrapped in different planes) in
their processors due to its superior electrical characteristics, suppressed short channel effects, high
drive current, low leakage current & better scaling capability (Schaller, 1997; Ho et al., 2013,
Bhattacharya and Jha, 2014, Lee, 2016). For multifin SOI FinFET device, Ion/Ioff ratio in order of 1011,
leakage current in order of 10-19 for SiC3C and reduced Subthreshold Swing (58mV/dec) for GaAs as
channel material has been obtained as compared to conventional devices (Kaur et al., 2017). SOI
technology is preferred in low power and high switching applications due to diminished leakage path
near the junction of source/drain regions. The exceptional SCEs such as DIBL and leakage current for
designed FinFET structures are 15.8mV/V and 1.37e-17 A respectively (Aujla and Kaur, 2019). For

1
wireless communication system, Fully depleted SOI MOSFET is served as prominent device due to
enhanced analog and RF performances such as higher cut-off frequency and improved
transconductance (Raskin, 2019). The comparative analysis of partially depleted SOI, FD-SOI and
bulk MOSFET devices along with the impact of HALO implantation on analog and RF process
parameters has been done for the gate length of 0.08µm (Kilchytska et al., 2003). An improvement in
transconductance, intrinsic gain, cut-off frequency and On/Off drain current ratio has been obtained
for scaled trigate bulk FinFET device (bha et al., 2019). Moreover, fully-depleted (FD) SOI MOSFET is
an appropriate device for analog applications as it results in high transconductance to drain current
ratio and this advantage can make them to work efficiently at high temperature or at high frequency
(Colinge, 1998).
Utilization of Meta-heuristic approaches for designing and optimization of engineering problems has
appeared as a significant tool in obtaining optimum process parameters. Because they do not require
gradient information, can bypass local optima and easy to implement (Mirjalili and lewis, 2016).The
electrical characteristics of 20nm bulk FinFET with triangular shaped fin have been optimized using
artificial neural network (ANN) and Genetic algorithm (GA). It was demonstrated that the performance
metrics viz. Drain induced barrier lowering (DIBL), leakage current, drive current has been improved
after optimization (Gaurav et al., 2016). The device optimization using Whale optimization Algorithm
(WOA) has also been done due to its less convergence time as compared to others algorithms
(Mukherjee et al., 2017).Traffic path planning system has been implemented with the modified Fuzzy
cognitive maps (Vascak, J., 2012). A novel gas optimization algorithm has been demonstrated with
benchmark functions and showed improved efficiency w.r.t GA and particle swarm optimization (PSO)
algorithms (Shams et al., 2017). An optimum Traffic Light system has been realized with modified
Fuzzy model (Gil et al., 2018). An efficient novel algorithm based on search and rescue operation has
been proposed for real world applications (Shabani et al., 2019).Fuzzy controlled system has been
created using several advanced nature inspired algorithms (Precup and David, 2019).
Research on the development of FinFET is on-going at 10 nm and even 7 nm technology node (Kang
et al., 2013; Eneman et al., 2013). However, no systematic design guideline for the design of the
channel and source/drain contact has been presented. Hence this article is focused on design of
14nm SOI FinFET using GA and WOA optimization techniques.
This paper is arranged as follows: Section 2 discusses the device design and the Simulation
framework. The analysis of FinFET performance using metrics like SCEs and analog parameters are
indicated in the section 3. Device optimization using GA and WOA via ANN and the summary
comparison of MATLAB and TCAD results with previous literature are demonstrated in section 4.
Section 5 concludes the work done.

2. DEVICE DESIGN AND SIMULATION FRAMEWORK

The structure of the vertical body profile in the n-channel region SOI FinFET is shown in Figure 1. A
FinFET with SiO2 as interfacial oxide and N-poly-silicon as a gate electrode in underlap regions has
been modeled. The design considerations of the device are shown in Table 1. The doping

2
concentration for channel, source/drain and substrate are 1017 cm-3, 3×1020 cm-3 and 1x1016 cm-3
respectively. The gate work function for the device is 4.5 eV at 300K temperature and the thickness of
SiO2 as gate dielectric and buried oxide is 1nm and 20nm respectively (Colinge, 2008; Sun et al.,
2011)

(a) (b)

Figure 1. Bird eye views of designed SOI FinFET devices(a) 2-D view (b) 3D view with device
dimensions
Table 1 : Process Parameters of designed FinFET
*
Design Parameters Intel Present work
Gate length, Lg (nm) 14 14
Oxide thickness, Tox (nm) 1.0 1.0
Supply Voltage (V) 0.8 0.7
*as per ITRS dimensions (2013),http://public.itrs.net

Table 2 : Typical Cases Taken For Simulation

Design Parameters HFin/Lg WFin/Lg
(Colinge, 2008; Ho
0.72,1.43,2.15,2.9,3.58 0.36,0.5,
et al., 2013; Sun et
0.65,0.79,0.93,1,1.08
al., 2011, Mohapatra
et al., 2015)

Typical cases of WFin/Lg and HFin/Lg for simulation of designed device are mentioned in Table 2. The
proposed device is designed, simulated and analyzed using Cogenda Visual TCAD. The device is
designed using GDS and process file and the file obtained through this process is in tif3D format. The
process file involves the description of the device structure including the doping profiles, electrical
contact, meshing and material regions. The simulator adopted various physical models viz. Drift
Diffusion, Lucent mobility, Band-to-Band tunnelling, along with Shockley–Read–Hall (SRH) and Auger
recombination models for solving diffusion and transport equations .Further, the device performance

3
parameters are extracted and their analysis has been done using numerical methods (Kaur et al.,
2019 ; Mohapatra et al., 2015 ; De Andrade et al., 2012). The validation of simulator has been
examined by comparing TCAD results with existing research work. Figure 2 illustrates that the
simulation results are in good agreement with the published work (De Andrade et al., 2012). Figure 3,
demonstrates the V-I characteristic of the device at the drain voltage of 0.7V and 50mV with gate
ramp from 0 to 0.7V. It is depicted that higher drain voltage (0.7V) has more drive current as
compared to corresponding drain voltage of 50mV. The output characteristic curve of the device is
shown in Figure 4 in which graph is plotted for 0.7V and 50mV gate voltages with corresponding ramp
drain voltages from 0 to 0.7V.

0 .0 0 0 0 2 5
S im u la tio n
R E F (D e A n d ra d e e t a l., 2 0 1 2 )
0 .0 0 0 0 2 0 Vd= 50m V
L g = 180 n m
Drain current, Id (A)

0 .0 0 0 0 1 5 W F in = 1 30n m
H F in = 65 n m
0 .0 0 0 0 1 0

0 .0 0 0 0 0 5

0 .0 0 0 0 0 0

0 .0 0 .1 0 .2 0 .3 0 .4 0 .5 0 .6
G a te V o lta g e , V g (V )

Figure 2. Identical Id-Vg simulation results of designed FinFET structure with reference results (De
Andrade et al., 2012)

0.0000085
0.0000080
0.0000075 Vd (50mV)
0.0000070
Vd (0.7V)
Drain Current, Id (A)

0.0000065
0.0000060
0.0000055 Lg= 14nm
0.0000050 W Fin=5nm
0.0000045
0.0000040 H Fin =10nm
0.0000035
0.0000030 Tox=1nm
0.0000025
0.0000020
0.0000015
0.0000010
0.0000005
0.0000000
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
Gate Voltage, Vg (V)

Figure 3. V-I characteristic curve in Linear and saturation region of designed FinFET device

3. FINFET PERFORMANCE
The impact of device fin parameters (WFin/Lg and HFin/Lg ) variation on various performance metrics
such as short channel effects viz. on-current or drive current (ION), off-current or leakage current
(IOFF), the ratio of ION and IOFF (ION/IOFF), Subthreshold Swing (SS) and analog parameters viz.
Transconductance (gm), Transconductance Generation Factor (TGF), output conductance (gd),
intrinsic gain (Av) and early Voltage (VEA) are presented systematically.

4
 0.0000085
0.0000080
0.0000075 Vd (50mV)
0.0000070
Vd (0.7V)

Drain Current, Id (A)

0.0000065
0.0000060
0.0000055 Lg= 14nm
0.0000050 W Fin=5nm
0.0000045
0.0000040 H Fin =10nm
0.0000035
0.0000030 Tox=1nm
0.0000025
0.0000020
0.0000015
0.0000010
0.0000005
0.0000000
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
Gate Voltage, Vg (V)

Figure 4. Output characteristics of SOI FinFET device

3.1. Effects of Fin Height

The drive current is defined as the value of current calculated at Vd= 50mV and Vg= 0.7 V. Leakage
current is referred as current value when applied input gate voltage is zero (Vg= 0V).Subthreshold
Swing (SS) is the inverse of sub-threshold slope (S); it is stated as the ratio of change in applied gate
voltage to the decade change in drive current.
∂Vg
SS = (1)
∂ log10 I d

The performance parameters ION, ION/IOFF ratio and SS are calculated for designed devices as
shown in Figure 5 and 6 .From Figure 5 it is observed that higher drive current is obtained for
increased Fin height where as in Figure 6 reduction of on-off current ratio occur because of
enhancement of leakage current with increased fin height. The better SS is required for the high
speed switching capability of device for digital circuits. The SS presented in Figure 6 is near to ideal
value i.e. 60mV/dec at 300K (Sakhi and Chowdhury, 2013), also it is observed that SS is less affected
by fin height variation, it fluctuates between 62.5mV/dec to 62.8 mV/dec. This happens because of
the structure of FinFET device, as the gate is wrapped from three sides of channel with thin Fin width.
Therefore, the device has more immunity to SCEs and greater electrostatic control over the channel.
Transconductance (gm) can be calculated by taking the ratio of variable drain current (∂Id) to the
variable gate voltage (∂Vg) at constant value of drain source voltage (Vd). Basically, gm represents its
capability of converting input voltage change into output current. It also describes the switching
capability of device, which means that higher the transconductance, faster the device can switch on
and off. Therefore, higher clock frequencies can be supported for this type of device. Figure 7 show
the trend of the variation of transconductance (gm = ∂Id /∂Vg) and transconductance generation factor
(gm/Id) w.r.t gate voltage for fin height 10nm and fin width 5nm. Both gm and Id are increasing with the
increase in HFin/Lg ratio of the designed devices, extracted gm for height variation is presented in
Figure 8. For producing higher drive current, taller fins are preferred whereas for reduced SCEs, thin
fin is required because it may reduce the cause of an electric field in silicon surface which further
lessen IOFF. The decreased gd is detected in Figure 9 for lower HFin for designed device. CMOS based

5
analog circuits require transistors with low value of output transconductance (gd=∂Id /∂Vd) and high
value of gain. Both are obtained for the case of low fin height ratio i.e. 1.43 and high HFin/L g= 2.9
respectively. Further, TGF is directly proportional to gm and is suitable for the realization of analog
circuits at low voltage supply. Due to brevity, the extracted values of higher intrinsic gain (AV= 20*log10
(gm/gd)) and early voltage (VEA= Id/gd) are 125dB and 3.7V respectivley, achieved at the lower fin
height of 10nm (Sun et al., 2011 ; Mohapatra et al., 2015)

-6
6 .0 x 1 0
(A)

-6
5 .5 x 1 0
ON

-6
5 .0 x 1 0
Drive Current, I

-6
4 .5 x 1 0
-6
Lg= 14nm
4 .0 x 1 0
-6
W F in = 5 n m
3 .5 x 1 0
Tox=1nm
-6
3 .0 x 1 0
Vd=50m V
-6
2 .5 x 1 0 V g = 0 .7 V
-6
2 .0 x 1 0
0 .5 1 .0 1 .5 2 .0 2 .5 3 .0 3 .5 4 .0
H F in /L g

Figure 5. ION variation w.r.t HFin/Lg for FinFET device.

6
6 .5 x 1 0
6 L g = 14n m 62.80

Subthreshold Swing(mV/dec)
6 .0 x 1 0
W F in = 5n m
6 62.75
5 .5 x 1 0 T o x = 1n m
5 .0 x 1 0
6
V g = 0.7V 62.70
ION/IOFF

6 V d = 50m V
4 .5 x 1 0 62.65
6
4 .0 x 1 0 62.60
6
3 .5 x 1 0 62.55
6
3 .0 x 1 0
62.50
6
2 .5 x 1 0
0 .5 1 .0 1 .5 2 .0 2 .5 3 .0 3 .5 4 .0
H F in /L g

Figure 6. SS and ION /IOFF variation w.r.t HFin/Lg for FinFET device.
Transconductance Generation Factor (V )

-5
3 .0 x 1 0
25
-5
2 .5 x 1 0
Transconductance, g (S)
m

-5 Lg= 14nm 20
2 .0 x 1 0
W F in = 5 n m
-5
1 .5 x 1 0 H F in = 1 0 n m
15

-5 Vd=50m V
1 .0 x 1 0 10
V g = 0 .7 V
-6
5 .0 x 1 0
5
0 .0
0
0 .0 0 .1 0 .2 0 .3 0 .4 0 .5 0 .6 0 .7
G a te V o lta g e , V g (V )
-1

Figure 7. Gate voltage versus gm and TGF for FinFET device

6
 Lg=14nm

Transconductance, g (S)
-5
6 .0 x 1 0
W F in = 5 n m H F in /L = 2 .9
g

m
H F in /L = 2 .1 5
5 .0 x 1 0
-5 Tox=1nm g
V g = 0 .7 V
-5 H F in /L = 1 .4 3
4 .0 x 1 0 Vd= 50m V g

-5
3 .0 x 1 0

-5
2 .0 x 1 0 H F in /L = 0 .7 2
g

-5
1 .0 x 1 0

0 .0
0 .5 0 .8 1 .0 1 .3 1 .5 1 .8 2 .0 2 .3 2 .5 2 .8 3 .0 3 .3
H F in /L g

Figure 8. Transconductance for HFin/Lg variation.

Ouput Conductance, gd(S)

-5
1 .8 x 1 0 Lg=14nm H F in /L g (2 .9 )
-5
1 .6 x 1 0 W F in = 5 n m H F in /L g (2 .1 5 )
-5 Tox=1nm H F in /L g (1 .4 3 )
1 .4 x 1 0
-5 Vg= 50m V
1 .2 x 1 0
-5
1 .0 x 1 0
-6
8 .0 x 1 0 g d in c r e a s e s w ith in c r e a s e in
-6
6 .0 x 1 0 H F in /L g r a tio
-6
4 .0 x 1 0
-6
2 .0 x 1 0
0 .0
0 .0 0 .1 0 .2 0 .3 0 .4 0 .5 0 .6 0 .7
D r a in V o lta g e , V d (V )

Figure 9. Drain voltage versus output conductance for HFin/Lg variation.

3.2. Effect of Fin Width

The sensitivity of fin width for ION/IOFF and SS of designed device is shown in Figure 10. Here, it is
observed that for high fin width, SCEs arises because of larger longitudinal electric field at the
source side and larger distance between multiple gates, which in turns leads to high leakage current,
SS and reduced ION/IOFF .Therefore, it is depicted that for SCEs immunity narrow fin width is suitable.
The analog parameters like TGF and VEA are plotted for WFin/Lg variation in Figure 11 and 12. Larger
TGF is required for producing highly efficient device. It is predicted that higher value of TGF is
obtained at least WFin/Lg as shown in Figure 11.TGF is dependent parameters of transconductance,
which further depends on Id. More drive current is demonstrated for larger fin width because of
immense accommodation of charge carriers in the larger area of the device. Better early voltage
(VEA) is demonstrated for lower value of WFin/Lg, because of reduction in substrate effects, body
heating effects and higher immunity towards SCEs. The gd shows degradation by the order of 104 for
increased fin width of the device (Mohapatra et al., 2015 ; Nandi et al., 2013).

7
 6
7x10
78

Subthreshold Swing (mV/dec)

6 Lg= 14nm
6x10 76
H F in = 1 0 n m
6
5x10 V g = 0 .7 V 74
Vd= 50V
4x10
6 72
ION/IOFF 6 70
3x10
6
68
2x10
66
6
1x10 64
0 62

0 .3 0 .4 0 .5 0 .6 0 .7 0 .8 0 .9 1 .0 1 .1 1 .2
W F in /L g

Figure 10. ION /IOFF and SS variation w.r.t WFin/Lg for FinFET device.

30
W F in /L g ( 1 .0 8 )
25 W F in /L g (0 .9 3 )
W F in /L g (0 .6 5 )
20
W F in /L g (0 .3 6 )
TGF (V )
-1

15 Lg=14nm
H F in = 1 0 n m
10 Tox=1nm
Vd= 50m V
5
W F in in c r e a s e ,T G F d e c r e a s e s

0
0 .0 0 .1 0 .2 0 .3 0 .4 0 .5 0 .6 0 .7
G a t e V o lt a g e , V g ( V )

Figure 11. TGF variation for different WFin/Lg ratios

5 W F in /L g (1 .0 8 )
W F in /L g (0 .9 3 )
W F in /L g (0 .6 5 )
4 W F in /L g (0 .3 6 )
Early Voltage, VEA (V)

W F in /L g v a r ie s
Lg=14nm a s 0 .3 6 - 1 .0 8
3 H F in = 1 0 n m
Tox=1nm
2 Vd= 50m V

1
V E A d e c re a s e s
0
0 .0 0 .1 0 .2 0 .3 0 .4 0 .5 0 .6 0 .7
G a te V o lta g e , V g (V )

Figure 12. VEA variation for different WFin/Lg ratios

4. PARAMETER OPTIMIZATION WITH GA AND WOA through ANN Training

8
 4.1. Training of Artificial Neural Network
ANN is defined as a computing system which consists of highly interconnected multiple neurons
which mimic the biological behaviour of human brain. The multilayer feed-forward model of neural
network contains three interconnected layers: an input, an output and the hidden layer as shown in
Figure 13.The input layer brings the input signal into system through consecutive layers of neurons for
further processing. The intermediate hidden layer solves the desired problem using sigmoid transfer
function (activation function) and a set of associated weighted inputs. The output layer produces the
output of the network using linear transfer function. In this way, ANNs can be trained by amending the
weight values of interconnected neurons.The given network is trained with Levenberg-Marquardt
backpropagation algorithm (trainlm).TRAINLM is preferred because it require less memory and has
more speed as compared to other algorithms. Although, this algorithm provides training with validation
and test vectors and also its network has derivative functions for their transfer function, weight and net
input. Backpropagation is used to calculate the Jacobian ‘jX’ of performance ‘perf’ with respect to the
weight and bias variables ‘X’. Each variable is adjusted according to Levenberg-Marquardt equation,
jj = jX ∗ jX 2(a)
je = jX ∗ E 2(b)

dX = −( jj + I ∗ mu ) je 2(c)

where E is all errors and I is the identity matrix (Hagan and Menhaj, 1994; Sapna et al., 2012)
Training is stopped after satisfying few of conditions viz. Maximum number of epoches (repetitions) is
reached, Performance is minimized to the goal etc.

i).Through ANN network, two input elements (WFin & HFin) and five output elements (SS, ION, gm,
VEA & TGF) has been created with 20 hidden neurons by giving 70 data samples for optimizing
FinFET parameters. As each input have corresponding five output parameters in the output
dataset.

ii).Separately created datasets for device has been applied to NN (Neural Network) Toolbox of
MATLAB for obtaining the required net files. The total data samples considered for training the
network has been divided as 70% (48 samples) for training samples, 15% (11 samples) for
validation and remaining 15% (11 samples) for testing samples. After finishing the training
process, mean squared error (mse) of the trained network is 0.10125 obtained at the 8th epoch
is shown in Figure 14. MSE determines the network’s performance and is measured as an
average squared difference between targets and outputs. Through ANN network, two input
elements (WFin & HFin) and five output elements (SS, ION, gm, VEA & TGF) has been created with
20 hidden neurons by giving 70 data samples for optimizing FinFET parameters. As each input
have corresponding five output parameters in the output dataset.

9
 Figure 13. ANN Architecture

Figure 14. Performance of Levenberg-Marquardt Backpropagation Algorithm

iii).Separately created datasets for device has been applied to NN (Neural Network) Toolbox of
MATLAB for obtaining the required net files. The total data samples considered for training the
network has been divided as 70% (48 samples) for training samples, 15% (11 samples) for
validation and remaining 15% (11 samples) for testing samples. After finishing the training
th
process, mean squared error (mse) of the trained network is 0.10125 obtained at the 8 epoch
as shown in Figure 14. MSE determines the network’s performance and is measured as an
average squared difference between targets and outputs. The value is nearer to zero which
indicates improved performance for device. Another measuring parameter is Regression (R)
which is defined as the correlation between targets and the output. The regression values for
FinFET device is: Training = 0.99999, Validation=0.99983, Testing= 0.99983 and all=0.99994 as
outlined in Figure 15. R near to 1 value shows close relationship between target and output
(https://in.mathworks.com/discovery/neural-network.html).The results obtained by improved
trained networks are saved in MATLAB and further used for optimization (Aujla and Kaur, 2019;
Kipli et al., 2012).

10
 Figure 15. Regression Analysis Plot for Levenberg-Marquardt Backpropagation Algorithm

4.2. Optimizing Algorithms

In the present research, a single objective function has been used for optimizing FinFET
parameters which produces a single global optimal (minimum) value. The objective function ‘f’ for
the defined problem (optimized fin width and fin height) of device is given as

f = SS − I ON × 10 6 − g m × 10 5 − VEA − TGF × 10 −1 (3)

where SS is Subthreshold Swing (mV/dec), ION denotes drive current (A), gm (S), indicates
Transconductance, Early voltage is VEA (V) and TGF is Transconductance generation factor measured
-1
as V . In order to attain the optimized parameters, the objective function mentioned in equation (3) is
required to be reduced through optimization algorithms such as Genetic Algorithm and Whale
Optimization Algorithm.

4.2.1. Genetic Algorithm

GA is a heuristic search algorithm used in artificial intelligence and computing. It is based on the
concept of natural selection where the fittest individual are selected for producing optimum results for
the defined problem with fitness function, ‘f’ as mentioned in equation (3).The constraints given as
input to GA for the defined problem are : Lower bounds = [5 10] ; Upper bounds= [15 55]. The main
operators of this algorithm are mutation, selection and crossover. To perform these operations, the
selected population type is ‘double vector’ due to the integer constraints. The initial size of population
is selected as 40 and the ‘rank’ has been chosen as fitness scaling function for generation of new
population of individuals. The ‘rank’ of individual represents its location sorted in increasing order

11
instead of its raw score. The ‘stochastic uniform’ selection function has been used for selecting
parents for generation of new offsprings. The Probability values of ‘0.8’ for crossover and ‘0.2’ for
mutation have been used for generation of new offsprings. Migration defines how an individual moves
between subpopulation numbers (https://in.mathworks.com/discovery/genetic-algorithm.html). The
stopping criteria for this algorithm includes number of generations (taken as 100) and function
tolerance (a point where a weighted average change in fitness function is less than the function
tolerance of 10-12 (Aujla and Kaur, 2019).The optimal input and output parameters of FinFET obtained
through GA toolbox have been mentioned in Table 3.

4.2.2. Whale Optimization Algorithm

WOA algorithm imitates the hunting behaviour of humpback whales. This algorithm begins with the
random population of whales. These whales find the optimum position of prey’s and attack them using
one of these methods.
(i) Encircling technique: The whales update their location depending upon best position as given in
equation (4) and (5)

D = C ⊗ X ∗ (t ) − X ( t ) (4)

X (t + 1) = X ∗ (t ) − A ⊗ D (5)

D is the distance between prey and whale, X*(t) indicate whale earlier best position and X (t+1) is the
whale current position. The coefficient vectors, ‘A’ and ‘C’ are defined as follows:
A = 2a ⊗ r − a (6)
C = 2r (7)
where r is a random vector having range [0,1] and the value of ‘a’ decreases from 2 to 0 as the
iterations proceed. The value of ‘A’ and ‘C’ coefficients lie between [-2, 2] and [0, 2].
(ii) Bubble-net attacking technique: This technique contains two methods. The first method includes
the shrinking encircling, which can be explained by diminishing the variable ‘a’ and also ‘A’ as quoted
in equation (6). The second is the spiral updating position. This activity of whales for making spiral
shape around prey can be expressed as:
X (t + 1 ) = D ' ⊗ e bl ⊗ cos( 2πl ) + X ∗ (t ) (8)

D' = X ∗ (t ) − X (t ) is the difference between humpback whale and prey, ‘b’ is a constant variable,

⊗ represents element-by-element multiplication and ‘l’ is random variable with range = [-1,1].
The probability of 50% is taken as an assumption for choosing either of two methods for catching the
prey during iterations of the algorithm. The whales can swim around the prey along a spiral-shaped
path and at the same time the circle shrunk using as follows:
⎧ X ∗ (t ) − A ⊗ D p ≥ 0 .5 ⎫
X (t + 1 ) = ⎨ ' ⎬ (9)
⎩D ⊗ e ⊗ cos(2πl ) + X (t )
bl ∗
p < 0 .5 ⎭

where ‘p’ is a random probability value lies between 0 and 1. The randomness of probability make
effective transition between exploration and exploitation phases. It interprets the probability of
deciding either of the spiral model or the shrinking encircling method to adjust the position of whales.

12
(iii) Search for prey : In this method, the whales randomly searches the position of prey instead of
the best search agent as follows :
D = C ⊗ Xrand − X (t ) (10)

X (t + 1) = X rand − A ⊗ D (11)

Xrand is randomly search position vector.

(https://in.mathworks.com/matlabcentral/fileexchange/55667-the-whale-optimization-algorithm).
The defined fitness function ‘f’ quoted in equation (3) has been applied to WOA algorithm for
optimizing the parameters of designed FinFET. The WOA started randomly with population size of 40
in search domain of input elements : height and width range of [10 55] and [5 15] respectively for 100
iterations. For each pair of input parameters, the fitness function mentioned in equation (3) is
calculated for best solution. The ‘A’ and ‘C’ parameters are determined depending on decreased
value of ‘a’ and better solution is updated based on probability metric ‘p’.The preceding steps are
repeated until stopping criteria is reached (number of iterations=100) and optimized parameters are
obtained as shown in Table 3 Therefore, WOA algorithm has the capability of providing high local
optima avoidance and convergence speed over the course of iterations. WOA algorithm converges
earlier as compared to GA algorithm because it eliminate the problem of staying in local optima and
hence the speed of WOA algorithm incresed with respect to others. The flowchart for WOA operation
is shown in Figure 16.
WOA converges at 8th iteration and whereas GA converges at 17th iteration for FinFET device with
lesser time i.e.51s (approx.) as compared to GA as shown in Table 3 (Aziz et al., 2018 ; Mathworks,
2020 ) and in Figure 17. The source code of WOA is available at http://www.alimirjalili.com/WOA.html.

13
Figure 16. Flowchart for WOA operation

14
 Table 3 : Optimized Input parameters obtained through GA and WOA for FinFET

Applied Total Optimum

Input
Algorithm in Function fitness Output Parameters Time
Parameters
MATLAB Evaluations function, f
ION=6.0542 X 10-5 A
SS= 62.7092
Genetic mV/dec WFin =5nm 64.367
4000 47.662
Algorithm gm =3.1474 X 10-5 A HFin =45nm sec
VEA=3.433 V
TGF= 24.123 V-1
ION=6.0542 X 10-5 A
SS= 62.7091
Whale
mV/dec WFin=5nm 50.972
Optimization 4000 47.662
gm =3.1474 X 10-5 A HFin =45nm sec
Algorithm
VEA=3.433 V
TGF= 24.123 V-1

Figure 17. Convergence Curves for both devices created through GA and WOA algorithms

The comparison of results obtained through MATLAB optimizing tools (GA & WOA) and TCAD has
been mentioned in Table 4. MATLAB provides two optimal input metrics viz. Height =45nm &
width=5nm and their corresponding output parameters such as ION, SS, gm VEA and TGF. The same
input dimensions has been used for designing a optimal FinFET device in TCAD tool. Then, the
difference between output parameters result obtained through MATLAB and TCAD has been
evaluated in terms of percentage change in order to validate the tool. The results obtained after
applying optimization tool to a proposed device are compared with previous literature. It is observed
that the designed device illustrate the improvement for analog parameters and have comparable
values of ION & gm, along with reduced leakage current, output transconductance and higher value
of early voltage as compared to previous work.

15
 Table 4 : Verification of Optimized results and comparison of obtained optimized results with
existing work

Proposed FinFET SOI FINFET

FinFET
(Lg= 14nm,WFin= 5nm, HFin= 45nm, Tox=1nm, Vg=0.7V, (Lg= 14nm,
(Lg= 20nm,
Vd=50mV) WFin= 8nm,
WFin= 10nm,
HFin= 26nm,
HFin= 26nm,
Percentage Tox=1nm,
MATLAB Tox=0.9nm,
TCAD change Vd=Vg=0.9V)
Vd=Vg=0.7V)
(%)
(Han, 2017)
(Lee, 2016)

-5
4.51 ION=14 X 10
-6 ION=5.78 X 10-6 A ION=0.35 X 10-6 A
ION=6.0542 X 10 A A

SS=62.7092
SS=77.562.7
mV/dec SS= 62.7 mV/dec 0.014 ----
mV/dec

gm =3.1474 X 10-5
gm =2.9406 X 10-5
S 6.57 gm =10 X 10-5 S ----
S

VEA=3.433 V VEA=3.444 V 0.31

VEA=1V ----
-1
TGF= 24.123 V -1
TGF= 24.247 V 0.514 ---- ----

IOFF= 0.5 X 10-12 IOFF= 1 X 10-9

---- IOFF= 1.84 X 10-12 A ----
A A

---- gd =5.4 X 10-12 S ---- gd =10 X 10-8 S ----

5. CONCLUSION
This research work provides a comprehensive analysis of geometry parameters variations for
designing a FinFET device. The device with larger dimensions have higher ION and gm and have
lesser Leakage current, ION/IOFF and SS because of limited control of gate over channel. Therefore, it
is summarized that for high drive current taller fin height is suitable whereas for reduced SCEs narrow
fin width is preferred. The impact of fluctuations of HFin/Lg and WFin/Lg shows that for better
performance in terms of intrinsic gain, early voltage, TGF and output conductance the device
dimensions should be reduced. Population based evolutionary algorithms GA and WOA have
effectively maximized the performance of device by giving optimized performance metrics for
particular fin height and fin width. The optimized dimensions created by algorithms are utilized for
designing a device in TCAD and its process parameters are evaluated and compared to check the
validation of the simulator. With this, it is concluded that the valuable results obtained from designing
of multigate underlap SOI FinFET device could satisfy the need of low power standby applications.
Further, for future scope the techniques like spacer engineering; work function variation; channel
material variation etc. can be applied to proposed device for getting better performance of device and
their application in memory circuits.

16
 ACKNOWLEDGMENT
The research work presented in this paper is done using software which is purchased through TEQIP-
II grant received by organization. The authors are grateful to MHRD, Govt. of India for sanctioning this
grant to Guru Nanak Dev Engineering College, Ludhiana. Authors would also like to extend gratitude
to Dean RIC, I. K .Gujral Punjab for support in completion of this research work.

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