D. Y.

PATIL COLLEGE OF ENGINEERING, AKURDI, PUNE-44

DEPARTMENT OF ELECTRONICS & TELECOMMUNICATIONS
Subject: Microcontrollers T.E. (E&TC)

Experiment No. 7

Aim: Write a program in Embedded C to interface serial port with PC for both
side Communications.

Hardware Requirements: PIC 18F4550 trainer kit

Software Requirements: MPLAB IDE & C18 Compiler, Embedded C programming.

Theory:
The USART(universal synchronous asynchronous receiver transmitter) in PIC18F has both the
synchronous and asynchronous feature. The synchronous mode can be used to transfer data between the
PIC and external peripherals such as ADC and EEPROMs. The asynchronous mode is used to connect
PIC18F system with IBM PC serial port for full duplex serial data transfer.
These are the registers associated with the USART module:

1) SPBRG: Baud Rate Generator Register Low Byte

2) TXREG: USART Transmit Register
3) RCREG: EUSART Receive Register
4) TXSTA: Transmit Status and Control
5) RCSTA: Receive Status and Control
6) PIR1: Peripheral interrupt request register1

1) SPBREG register and Baud Rate in PIC18:

For a given crystal frequency the value loaded in SPBRG decides the baud rate. Relation between
baud rate and oscillator frequency is given below:
Desired Baud Rate = Fosc / (64X+64) = Fosc / 64(X+1)
Where X is the value we load into SPBGR register.
If Fosc=20MHz then
Desired Baud Rate = 20MHz / (64X+64) = 20MHz / 64(X+1)
Desired Baud Rate = 312500/(X+1)
To get X value for different baud rate we can solve as
X= (Desired baud rate/312500) -1
TXSTA: TRANSMIT STATUS AND CONTROL REGISTER
CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D

bit 7 CSRC: Clock Source Select bit

Asynchronous mode:Don’t care.
Synchronous mode:
1 = Master mode (clock generated internally from BRG)
0 = Slave mode (clock from external source)
bit 6 TX9: 9-Bit Transmit Enable bit
1 = Selects 9-bit transmission 0 = Selects 8-bit transmission
bit 5 TXEN: Transmit Enable bit(1)
1 = Transmit enabled 0 = Transmit disabled
bit 4 SYNC: EUSART Mode Select bit
1 = Synchronous mode 0 = Asynchronous mode
bit 3 SENDB: Send Break Character bit
Asynchronous mode:
1 = Send Sync Break on next transmission (cleared by hardware upon completion)
0 = Sync Break transmission completed
Synchronous mode: Don’t care.
bit 2 BRGH: High Baud Rate Select bit
Asynchronous mode:
1 = High speed 0 = Low speed
Synchronous mode: Unused in this mode.
bit 1 TRMT: Transmit Shift Register Status bit
1 = TSR empty 0 = TSR full
bit 0 TX9D: 9th bit of Transmit Data
Can be address/data bit or a parity bit.
(Note 1: SREN/CREN overrides TXEN in Sync mode with the exception that SREN has
no effect in Synchronous Slave mode.)

RCSTA: RECEIVE STATUS AND CONTROL REGISTER

SPEN RX9 SREN CREN ADDEN FERR OERR RX9D

bit 7 SPEN: Serial Port Enable bit
1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins)
0 = Serial port disabled (held in Reset)
bit 6 RX9: 9-Bit Receive Enable bit
1 = Selects 9-bit reception 0 = Selects 8-bit reception
bit 5 SREN: Single Receive Enable bit
Asynchronous mode: Don’t care.
Synchronous mode – Master:
1 = Enables single receive 0 = Disables single receive
This bit is cleared after reception is complete.
Synchronous mode – Slave:Don’t care.
bit 4 CREN: Continuous Receive Enable bit
Asynchronous mode:
1 = Enables receiver
0 = Disables receiver
Synchronous mode:
1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides
SREN)
0 = Disables continuous receive
bit 3 ADDEN: Address Detect Enable bit
Asynchronous mode 9-bit (RX9 = 1):
1 = Enables address detection, enables interrupt and loads the receive buffer when
RSR<8> is set
0 = Disables address detection, all bytes are received and ninth bit can be used as
parity bit
Asynchronous mode 9-bit (RX9 = 0):Don’t care.
bit 2 FERR: Framing Error bit
1 = Framing error (can be updated by reading RCREG register and receiving next
valid byte)
0 = No framing error
bit 1 OERR: Overrun Error bit
1 = Overrun error (can be cleared by clearing bit CREN)
0 = No overrun error
bit 0 RX9D: 9th bit of Received Data
This can be address/data bit or a parity bit and must be calculated by user
firmware.

PIR1(Peripheral interrupt request register 1):

Two of the PIR1 register bits are used by UART. They are TXIF( transmit interrupt flag)
and RXIF(receive interrupt flag). We monitor TXIF flag to make sure that all the bits are
transmitted before we write another byte into TXREG. We monitor RCIF flag to see if a
byte data has come or not.
Steps in Programming PIC18 to transfer data serially:
1) The TXSTA is loaded with 20H indicating asynchronous 8-bit mode, low baud
rate and transmit enabled.
2) Make TX pin on PORTC(RC6) an output for transmitting data.
3) SPBRG and SPBRGH are loaded with appropriate values for baud rate.
4) SPEN bit in RCSTA is set high to enable serial port of PIC18.
5) The character byte to be transmitted is loaded in TXREG register
6) Monitor the TXIF bit of the PIR1 register to make sure UART is ready for next
byte.
7) To send next character go to step 5.

Steps in Programming PIC18 to receive data serially:

1) The RCSTA is loaded with 90H to enable continuous receive 8-bit data.
2) The TXSTA is loaded with 00H to choose the low baud rate option.
3) SPBRG and SPBRGH are loaded with appropriate values for baud rate
4) Make RX pin on PORTC(RC7) an input for receiving data.
5) Monitor the RCIF bit of the PIR1 register to make sure UART has received entire
8-bit data.
6) To receive next character go to step 5.

There are two ways to increase the baud rate

1) Use a higher- frequency crystal:
As crystal is fixed so it is not a feasible solution.
2) Change a bit BRGH=0 in the TXSTA register:
This is the software way to quadruple the baud rate of the PIC18 while crystal
frequency is same.
When BRGH=0, the PIC18 divides Fosc/4 by 16 once more and uses this
frequency for UART to set the baud rate.
When BRGH=1, the PIC18 divides Fosc/4 by 4 once more and uses this
frequency for UART to set the baud rate.
Thus by making BRGH=1, user can quadruple the baud rate.
Conclusion: