Scribd
Upload
3 views7 pages

Exercise 1

The document contains exercises related to the analysis and design of VHDL models for finite state machines. It includes questions about sequential logic types, signal behavior, initial output values, and the number of processes in a given VHDL model. Additionally, it provides a framework for writing a VHDL model of a state machine and instructions for implementing an asynchronous reset feature.

Uploaded by

rohulsibi
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
3 views7 pages

Exercise 1

The document contains exercises related to the analysis and design of VHDL models for finite state machines. It includes questions about sequential logic types, signal behavior, initial output values, and the number of processes in a given VHDL model. Additionally, it provides a framework for writing a VHDL model of a state machine and instructions for implementing an asynchronous reset feature.

Uploaded by

rohulsibi
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 7

Design and Programming Embedded Multicore Architectures

Prof. Dr.-Ing. Diana Göhringer

Hardware Modelling and Simulation


Exercise 1
Chair of Adaptive Dynamic Systems

1) Analysis of a VHDL Model


Given is the VHDL Model of Listing 1.

a) What type of sequential logic is described by the VHDL model? Explain your answer.

b) Which function does the signal rst have? How does the signal “behave” regarding its
timing and level control?

c) What is the initial output value of y and p?

d) How many concurrent processes and statements are executed in the VHDL model?

1
Design and Programming Embedded Multicore Architectures

ENTITY unknown IS
PORT (clk, rst, dir: IN std_ulogic;
y: INOUT std_ulogic_vector(1 DOWNTO 0):= "00";
p: OUT std_ulogic);
TYPE state_type IS (s1, s2, s3, s4);
END unknown;

ARCHITECTURE behavioural OF unknown IS

SIGNAL new_state, state : state_type;

BEGIN

p1: PROCESS(clk)
BEGIN
IF clk='1' AND clk'EVENT THEN
IF rst='1' THEN
state <= s1;
ELSE
state <= new_state;
END IF;
END IF;
END PROCESS p1;

p2: PROCESS(state, dir)


BEGIN
IF dir = '1' THEN
CASE state IS
WHEN s1 => new_state <= s2;
WHEN s2 => new_state <= s3;
WHEN s3 => new_state <= s4;
WHEN s4 => new_state <= s1;
END CASE;
ELSE
CASE state IS
WHEN s1 => new_state <= s4;
WHEN s2 => new_state <= s1;
WHEN s3 => new_state <= s2;
WHEN s4 => new_state <= s3;
END CASE;
END IF;
END PROCESS p2;

p3: PROCESS(state)
BEGIN
CASE state IS
WHEN s1 => y <= "00";
WHEN s2 => y <= "01";
WHEN s3 => y <= "11";
WHEN s4 => y <= "10";
END CASE;
END PROCESS p3;

p <= y(1) XOR y(0);

END behavioural;

2
Design and Programming Embedded Multicore Architectures

Listing 1: An Unknown VHDL Model

e) Which function is represented by the given VHDL Model? (Disregard the p output!)

f) Draw the corresponding flow chart of the finite state machine. (You do not need to take
into account the clk and rst signals for drawing the flow chart!)

3
Design and Programming Embedded Multicore Architectures

g) Simulate the given code and fill in the following timing diagrams for the signals state,
new_state and the outputs y and p according to the given stimuli signals clk, rst
and dir. In order to do this, first determine the values of state and new_state. Sepa-
rate different values by a vertical line.

1
clk
0
t
1
rst
0
t
1
dir
0
t

new_state
t

state
t
1
y(1)
0
t
1
y(0)
0
t
1
p
0
t
Figure 1: Timing diagram for state machine

4
Design and Programming Embedded Multicore Architectures

2) Design of a Finite State Machine


A finite state machine is given as a state transition graph:

Figure 2: Finite State Machine (FSM) as state transition graph

a) What kind of state machine is described by this state transition graph? Give reasons for
your answer!

b) Write a VHDL model of the state machine by filling in the following framework. (Each
dot “●“ denotes a line that you should change.)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fsm IS
PORT (clk: IN std_logic;
a: IN std_logic_vector (1 DOWNTO 0);
y: OUT std_logic_vector (3 DOWNTO 0) );
TYPE fsm_state IS (state_0, state_1, state_2);
END;

5
Design and Programming Embedded Multicore Architectures

ARCHITECTURE behavioural OF fsm IS


SIGNAL sreg, next_sreg : fsm_state;
BEGIN
● PROCESS ( )
BEGIN
●
●
●
END PROCESS;
● PROCESS ( )
BEGIN
CASE sreg IS
● WHEN
● IF ( ) THEN
●
●
END IF;
● IF ( ) THEN
●
●
END IF;
● IF ( ) THEN
●
●
END IF;
● WHEN
● IF ( ) THEN
●
●
END IF;
● IF ( ) THEN
●
●
END IF;
● IF ( ) THEN
●
●
END IF;
● WHEN
● IF ( ) THEN
●
●
END IF;
● IF ( ) THEN
●
●
END IF;
● IF ( ) THEN
●
●
END IF;
END CASE;
END PROCESS;
END behavioural;

6
Design and Programming Embedded Multicore Architectures

c) Change in the framework given above in order to introduce an asynchronous low-active


reset to state_0!

You might also like

pFad - Phonifier reborn

Pfad - The Proxy pFad of © 2024 Garber Painting. All rights reserved.

Note: This service is not intended for secure transactions such as banking, social media, email, or purchasing. Use at your own risk. We assume no liability whatsoever for broken pages.


Alternative Proxies:

Alternative Proxy

pFad Proxy

pFad v3 Proxy

pFad v4 Proxy