CD4066B-Q1

www.ti.com SCHS383 – APRIL 2011

CMOS QUAD BILATERAL SWITCH

Check for Samples: CD4066B-Q1

1FEATURES • 5-V, 10-V, and 15-V Parametric Ratings

• Qualified for Automotive Applications • Latch-Up Exceeds 100mA per JESD78 - Class I
• 15-V Digital or ±7.5-V Peak-to-Peak Switching • Meets All Requirements of JEDEC Tentative
• 125-Ω Typical On-State Resistance for 15-V Standard No. 13-B, Standard Specifications for
Operation Description of "B" Series CMOS Devices
• Switch On-State Resistance Matched to Within
APPLICATIONS
5 Ω Over 15-V Signal-Input Range
• Analog Signal Switching/Multiplexing: Signal
• On-State Resistance Flat Over Full
Gating, Modulator, Squelch Control,
Peak-to-Peak Signal Range
Demodulator, Chopper, Commutating Switch
• High On/Off Output-Voltage Ratio: 80 dB
• Digital Signal Switching/Multiplexing
Typical at fis = 10 kHz, RL = 1 kΩ
• Transmission-Gate Logic Implementation
• High Degree of Linearity: <0.5% Distortion
Typical at fis = 1 kHz, Vis = 5 V p-p, • Analog-to-Digital and Digital-to-Analog
VDD – VSS ≥ 10 V, RL = 10 kΩ Conversion
• Extremely Low Off-State Switch Leakage, • Digital Control of Frequency, Impedance,
Resulting in Very Low Offset Current and High Phase, and Analog-Signal Gain
Effective Off-State Resistance: 10 pA Typical E, F, M, NS, OR PW PACKAGE
at VDD – VSS = 10 V, TA = 25°C (TOP VIEW)
• Extremely High Control Input Impedance
(Control Circuit Isolated From Signal Circuit): SIG A IN/OUT 1 14 VDD
1012 Ω Typical SIG A OUT/IN 2 13 CONTROL A
• Low Crosstalk Between Switches: –50 dB SIG B OUT/IN 3 12 CONTROL D
Typical at fis = 8 MHz, RL = 1 kΩ SIG B IN/OUT 4 11 SIG D IN/OUT
CONTROL B 5 10 SIG D OUT/IN
• Matched Control-Input to Signal-Output
CONTROL C 6 9 SIG C OUT/IN
Capacitance: Reduces Output Signal
VSS 7 8 SIG C IN/OUT
Transients
• Frequency Response, Switch On = 40 MHz
Typical
• 100% Tested for Quiescent Current at 20 V

DESCRIPTION/ORDERING INFORMATION
The CD4066B-Q1 is a quad bilateral switch intended for the transmission or multiplexing of analog or digital
signals. It is pin-for-pin compatible with the CD4016B, but exhibits a much lower on-state resistance. In addition,
the on-state resistance is relatively constant over the full signal-input range.
The CD4066B-Q1 consists of four bilateral switches, each with independent controls. Both the p and the n
devices in a given switch are biased on or off simultaneously by the control signal. As shown in Figure 1, the well
of the n-channel device on each switch is tied to either the input (when the switch is on) or to VSS (when the
switch is off). This configuration eliminates the variation of the switch-transistor threshold voltage with input signal
and, thus, keeps the on-state resistance low over the full operating-signal range.
The advantages over single-channel switches include peak input-signal voltage swings equal to the full supply
voltage and more constant on-state impedance over the input-signal range. However, for sample-and-hold
applications, the CD4016B is recommended.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright © 2011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
CD4066B-Q1
SCHS383 – APRIL 2011 www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

ORDERING INFORMATION
ORDERABLE TOP-SIDE
TA PACKAGE
PART NUMBER MARKING
–40°C to 125°C SOIC – D Reel of 2500 CD4066BQDRQ1 CD4066BQ

Switch

Control
In
Vis

p n

p
Out
n Vos

Control n
VC †
VSS

VDD

VSS

† All control inputs are protected by the CMOS protection network.

NOTES: A.All p substrates are connected to V DD.
B. Normal operation control-line biasing: switch on (logic 1), VC = VDD; switch off (logic 0), VC = VSS
C. Signal-level range: VSS ≤V is ≤ VDD

Figure 1. Schematic Diagram of One-of-Four Identical Switches and Associated Control Circuitry

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ABSOLUTE MAXIMUM RATINGS

(1)
over operating free-air temperature range (unless otherwise noted)
VALUE UNIT
DC supply-voltage range, VDD (voltages referenced to VSS terminal) –0.5 to 20 V
Input voltage range, Vis (all inputs) –0.5 to VDD + 0.5 V
DC input current, IIN (any one input) ±10 mA
(2)
Package thermal impedance, θJA D package 86 °C/W
Human-Body Model (HBM) 500
ESD Electrostatic discharge (3) Machine Model (MM) 150 V
Field_Induced_Charged Device Model (CDM) 1000
Lead temperature (during soldering): At distance 1/16 ± 1/32 inch (1,59 ± 0,79 mm) from case for 10 s max 265 °C
Storage temperature range, Tstg –65 to 150 °C

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The package thermal impedance is calculated in accordance with JESD 51-7.
(3) Tested in accordance with AEC-Q100.

THERMAL INFORMATION
CD4066B-Q1
THERMAL METRIC (1) D PACKAGE UNITS
14 PINS
θJA Junction-to-ambient thermal resistance 92.4
θJCtop Junction-to-case (top) thermal resistance 52.5
θJB Junction-to-board thermal resistance 46.7
°C/W
ψJT Junction-to-top characterization parameter 46.4
ψJB Junction-to-board characterization parameter 46.4
θJCbot Junction-to-case (bottom) thermal resistance N/A

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

RECOMMENDED OPERATING CONDITIONS

MIN MAX UNIT
VDD Supply voltage 3 18 V
TA Operating free-air temperature –40 125 °C

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ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
LIMITS AT INDICATED TEMPERATURES

VIN VDD 25°C UNIT

PARAMETER TEST CONDITIONS –40°C 125°C
(V) (V) TYP MAX
0.5 5 0.25 7.5 0.01 0.25
0.10 10 0.5 15 0.01 0.5
IDD Quiescent device current µA
0.15 15 1 30 0.01 1
0.20 20 5 150 0.02 5
SIGNAL INPUTS (Vis) AND OUTPUTS (Vos)
VC = VDD, RL = 10 kΩ returned 5 850 1300 470 1050
10 330 550 180 400
ron On-state resistance (max) V DD V SS Ω
to ,
Vis = VSS 2
15 210 320 125 240
to VDD
5 15
On-state resistance
Δron difference between any two RL = 10 kΩ, VC = VDD 10 10 Ω
switches
15 5
VC = VDD = 5 V, VSS = –5 V,
THD Total harmonic distortion Vis(p-p) = 5 V (sine wave centered on 0 V), 0.4%
RL = 10 kΩ, fis = 1-kHz sine wave
3-dB cutoff frequency VC = VDD = 5 V, VSS = –5 V, Vis(p-p) = 5 V
40 MHz
(switch on) (sine wave centered on 0 V), RL = 1 kΩ
–50-dB feedthrough VC = VSS = –5 V, Vis(p-p) = 5 V
1 MHz
frequency (switch off) (sine wave centered on 0 V), RL = 1 kΩ
Input/output leakage current VC = 0 V, Vis = 18 V, Vos = 0 V; and VC = 0 V,
Iis 18 ±0.1 ±1 ±10-5 ±0.1 µA
(switch off) (max) Vis = 0 V, Vos = 18 V
VC(A) = VDD = 5 V,
–50-dB crosstalk frequency VC(B) = VSS = -5 V, 8 MHz
Vis(A) = 5 Vp-p, 50-Ω source, RL = 1 kΩ

RL = 200 kΩ, VC = VDD, VSS = GND, 5 20 40

Propagation delay (signal
tpd CL = 50 pF, Vis = 10 V 10 10 20 ns
input to signal output)
(square wave centered on 5 V), tr, tf = 20 ns 15 7 15
Cis Input capacitance VDD = 5 V, VC = VSS = –5 V 8 pF
Cos Output capacitance VDD = 5 V, VC = VSS = –5 V 8 pF
Cios Feedthrough VDD = 5 V, VC = VSS = –5 V 0.5 pF

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ELECTRICAL CHARACTERISTICS (continued)

over operating free-air temperature range (unless otherwise noted)
LIMITS AT INDICATED TEMPERATURES

VIN VDD 25°C UNIT

PARAMETER TEST CONDITIONS –40°C 125°C
(V) (V) TYP MAX
CONTROL (VC)
5 1 1 1
Control input, low voltage |Iis| < 10 mA, Vis = VSS, VOS = VDD, and
VILC 10 2 2 2 V
(max) Vis = VDD, VOS = VSS
15 2 2 2
5 3.5 (MIN)
VIHC Control input, low voltage See Figure 6 10 7 (MIN) V
15 11 (MIN)
IIN Input current (max) Vis ≤ VDD, VDD – VSS = 18 V, VCC ≤ VDD – VSS 18 ±0.1 ±1 ±10-5 ±0.1 µA
Crosstalk (control input to VC = 10 V (square wave),
10 50 mW
signal output) tr, tf = 20 ns, RL = 10 kΩ
5 35 70
Turn-on and turn-off VIN = VDD, tr, tf = 20 ns,
10 20 40 ns
propagation delay CL = 50 pF, RL = 1 kΩ
15 15 30
Vis = VDD, VSS = GND, RL = 1 kΩ to GND, 5 6
Maximum control input CL = 50 pF, VC = 10 V (square wave 10 9 MHz
repetition rate centered on 5 V), tr, tf = 20 ns,
Vos = 1/2 Vos at 1 kHz 15 9.5
Ci Input capacitance 5 pF

SWITCHING CHARACTERISTICS
SWITCH INPUT SWITCH OUTPUT,
VDD Vos (V)
Vis Iis (mA)
(V)
(V) –40°C 25°C 125°C MIN MAX
5 0 0.61 0.51 0.36 0.4
5 5 –0.61 –0.51 –0.36 4.6
10 0 1.5 1.3 0.9
10 10 –1.6 –1.3 –0.9
15 0 4 3.4 2.4 1.5
15 15 –4 –3.4 –2.4 13.5

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TYPICAL CHARACTERISTICS
TYPICAL ON-STATE RESISTANCE TYPICAL ON-STATE RESISTANCE
vs vs
INPUT SIGNAL VOLTAGE (ALL TYPES) INPUT SIGNAL VOLTAGE (ALL TYPES)
600 Supply Voltage (VDD − VSS) = 5 V
r − Channel On-State Resistance − Ω

300 Supply Voltage (VDD − VSS) = 10 V

ron − Channel On-State Resistance − Ω

TA = 125°C
500 250 TA = 125°C

400
200
+25°C
300 150
+25°C
−55°C
200 100
−55°C
100 50
on

0 0
−4 −3 −2 −1 0 1 2 3 4
−10 −7.5 −5 −2.5 0 2.5 5 7.5 10
Vis − Input Signal Voltage − V Vis − Input Signal Voltage − V 92CS-27327RI
92CS-27326RI

Figure 2. Figure 3.

TYPICAL ON-STATE RESISTANCE TYPICAL ON-STATE RESISTANCE

vs vs
INPUT SIGNAL VOLTAGE (ALL TYPES) INPUT SIGNAL VOLTAGE (ALL TYPES)
Supply Voltage (VDD − VSS) = 15 V TA = 125°C
r − Channel On-State Resistance − Ω
r − Channel On-State Resistance − Ω

300 600

500 Supply Voltage (VDD − VSS) = 5 V

250

200 400
TA = 125°C
150 300

100 +25°C 200

10 V
−55°C
100 −15 V
50

0 0
on
on

−10 −7.5 −5 −2.5 0 2.5 5 7.5 10 −10 −7.5 −5 −2.5 0 2.5 5 7.5 10

Vis − Input Signal Voltage − V V is − Input Signal Voltage − V 92CS-27330RI

92CS-27329RI
Figure 4. Figure 5.

Iis CD4066B
Vis Vos
1 of 4 Switches

|Vis − Vos|
ron =
|Iis|
92CS-30966

Figure 6. Determination of ron as a Test Condition for Control-Input High-Voltage (VIHC) Specification

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TYPICAL CHARACTERISTICS (continued)

Keithley
VDD 160 Digital
Multimeter

TG
10 kΩ 1-kΩ
On
Range Y
H. P.
VSS X-Y
Moseley
Plotter 7030A

92CS-22716

Figure 7. Channel On-State Resistance Measurement Circuit

TYPICAL ON CHARACTERISTICS POWER DISSIPATION PER PACKAGE
FOR 1 OF 4 CHANNELS vs
SWITCHING FREQUENCY
3 104
6 TA = 25°C
4
PD − Power Dissipation Per Package − μ W

2 2

103
VO − Output Voltage − V

Supply Voltage
1 6
4 (VDD) = 15 V

2
10 V
0 102
VC = VDD VDD
6 5V VDD

14
CD4066B Vos 4 5
−1 Vis 1 of 4
Switches 2 6
RL
101 CD4066B
VSS
12
−2 6
13
All unused terminals are 4
connected to VSS 7
−3 2 VSS
−3 −2 −1 0 1 2 3 4 10 2 4 6 2 4 6
VI − Input Voltage − V 10 102 103
92CS-30919
f − Switching Frequency − kHz
92C-30920
Figure 8. Figure 9.

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TYPICAL CHARACTERISTICS (continued)

Cios VDD
VC = VSS
Vos
CD4066B
Vis = VDD
1 of 4
VC = −5 V VDD = 5 V Switches I

CD4066B
1 of 4 VSS
Switches 92CS-30922
All unused terminals are connected to VSS.
Cis Cos
VSS = −5 V

92CS-30921
Measured on Boonton capacitance bridge, model 75a (1 MHz);
test-fixture capacitance nulled out.
Figure 10. Typical On Characteristics for One of Four Figure 11. Off-Switch Input or Output Leakage
Channels

VDD +10 V VC VDD

VC = VDD
Vos Vis Vos
CD4066B tr = tf = 20 ns CD4066B
Vis
1 of 4 1 of 4
Switches Switches
1 kΩ 10 kΩ
200 kΩ
VSS 50 pF VSS
VDD
tr = tf = 20 ns 92CS-30924

92CS-30923 All unused terminals are connected to VSS.

All unused terminals are connected to VSS.
Figure 12. Propagation Delay Time Signal Input (Vis) to Figure 13. Crosstalk-Control Input to Signal Output
Signal Output (Vos)

VDD VDD
tr = tf = 20 ns VC = VDD
Vos
VDD CD4066B
1 of 4
Switches
1 kΩ
VSS 50 pF

NOTES: A.All unused terminals are connected to V SS. 92CS-30925

B. Delay is measured at Vos level of +10% from ground (turn-on) or on-state output level (turn-off).

Figure 14. Propagation Delay, tPLH, tPHL Control-Signal Output

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TYPICAL CHARACTERISTICS (continued)

tr tf
VC 10 V
90%
10% 50%
0V
Repetition
Rate
tr = tf = 20 ns
Vos V OS at 1kHz
V OS
2

VDD = 10 V
VC V OS at 1kHz
V OS
2
Vis = 10 V CD4066B
1 of 4
Switches
50 pF 1 kΩ
VSS

All unused terminals are connected to VSS. 92CS-30925

Figure 15. Maximum Allowable Control-Input Repetition Rate

VDD

Inputs

VDD

VSS

VSS 92CS-27555

Measure inputs sequentially to both VDD and VSS. Connect all unused inputs to either VDD or VSS. Measure control inputs only.

Figure 16. Input Leakage-Current Test Circuit

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TYPICAL CHARACTERISTICS (continued)

10 2 3 7 9 12
10 2 3 7 9 12 Clock
Clock 14 PE J1 J2 J3 J4 J5
14 PE J1 J2 J3 J4 J5 External
Reset 15 CD4018B
15 CD4018B 13 Reset
1 Q1 Q2
1 Q1 Q2
5 4
1 1/4 CD4066B 2
5 4

13 12 9 8 6 5 2 1
1
3
2 7 6

3 1/3 CD4049B
2 5
4 9 10 CD4001B
CD4001B

1/3 CD4049B 6
11 10 4 3
5 4
8
10
9
12 6 5 11 Signal
12 6 5 13 Outputs
11
13 Channel 1
Signal 2 LPF
12 11 12
Inputs 10 k Ω
Channel 1 1/6 CD4049B
1 2
1
Channel 2 5
4 CD4066B 3 Channel 2
4 3 LPF
Channel 3
8 9 10 kΩ
4 1/4 CD4066B CD4066B
Channel 4 3 8
11 10
11 Channel 3
Package Count 9 LPF
10 kΩ
2 - CD4001B 10 kΩ
1 - CD4049B
3 - CD4066B
2 - CD4018B VDD 10 LPF Channel 4
Clock
Maximum 10 kΩ
Allowable 30% (VDD − VSS)
VSS
Signal Level Chan 1 Chan 2 Chan 3 Chan 4

92CM-30928

Figure 17. Four-Channel PAM Multiplex System Diagram

5V
Analog Inputs (±5 V)
0
−5 V
VDD = 5 V
VDD = 5 V

CD4066B
5V SWA
0 SWB
IN CD4054B
SWC

SWD
Digital
Control
Inputs
VSS = 0 V
VEE = −5 V VSS = −5 V
Analog Outputs (±5 V)

92CS-30927

Figure 18. Bidirectional Signal Transmission Via Digital Control Logic

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APPLICATION INFORMATION

In applications that employ separate power sources to drive VDD and the signal inputs, the VDD current capability
should exceed VDD/RL (RL = effective external load of the four CD4066B-Q1 bilateral switches). This provision
avoids any permanent current flow or clamp action on the VDD supply when power is applied or removed from the
CD4066B-Q1.
In certain applications, the external load-resistor current can include both VDD and signal-line components. To
avoid drawing VDD current when switch current flows into terminals 1, 4, 8, or 11, the voltage drop across the
bidirectional switch must not exceed 0.8 V (calculated from ron values shown).
No VDD current will flow through RL if the switch current flows into terminals 2, 3, 9, or 10.

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PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Top-Side Markings Samples
(1) Drawing Qty (2) (3) (4)

CD4066BQDRQ1 ACTIVE SOIC D 14 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 CD4066BQ
& no Sb/Br)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)

(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF CD4066B-Q1 :

• Catalog: CD4066B

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 11-Apr-2013

• Military: CD4066B-MIL

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

• Military - QML certified for Military and Defense Applications

Addendum-Page 2
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