19ECE347 Electronic System Level Design and Verification

Answer key for midsem (Sep-2024)

1) i) c ii) a iii) c iv) 1111 v) one hot encoding vi) b (one mark each: 6 marks)

2) ESL Design flow (6 marks)

Steps 1 and 2: 0.5 marks each, 1 mark for all other steps in flow diagram

3) The given code X is a Gray code. Using basic design steps, the following can be inferred about the design.
The most significant bit (MSB) of the Gray code is the same as the MSB of the binary code. (1 mark)
The second bit is obtained by XOR-ing the first and second bits of the binary code. (1 mark)
The third bit is obtained by XOR-ing the second and third bits of the binary code (1 mark)

SystemVerilog code. //Using always block:

module binary_to_gray_3bit ( (1 marks) always_comb begin ( 1 mark)
input logic [2:0] B, // 3-bit binary input
output logic [2:0] G // 3-bit Gray code G[2] = B[2]; // MSB remains same
output ); G[1] = B[2] ^ B[1]; // B2 xor B1
//Using assign statement: G[0] = B[1] ^ B[0]; // B1 xor B0
assign G[2] = B[2]; // MSB remains same // (0.5 marks for each statement)
assign G[1] = B[2] ^ B[1]; // B2 xor B1 end
assign G[0] = B[1] ^ B[0]; // B1 xor B0
// (0.5 marks for each statement) endmodule

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4) The system to be designed is a D flipflop with active high synchronous reset, using a T flipflop ( 1 mark)

D flip flop design using T (2 marks)

To use only 2x1 multiplexers: the XOR gate is replaced with 2x1 multiplexer with select line as A and I0=
B, I1 = B_bar (1 mark)

To include the active high synchronous reset, we include another multiplexer with the following:
Select line = reset, I0= ground, I1 = output of previous multiplexer (1 marks)

5) Constraint Random (approach 1)

Constrained random testing, on the other hand, is a Directed testing (approach 2)
testing approach in which test cases are generated • Using specifications, write verification plan
randomly based on a set of constraints. The goal of with list of tests, focusing on each feature
constrained random testing is to create a large • Apply corresponding stimulus and verify log
number of diverse and complex test scenarios that files and waveforms manually
the design may encounter during its lifetime. • Incremental procedure, where tests are
Advantages: covered one by one
• Each test shares this common test bench (with • Produces immediate results, since we check
a few lines of code added for stimulus and creation of every stimulus vector.
checking for exceptions), while in directed Advantage: covers all test, 100% coverage
testing each test is written from scratch. Disadvantages :
• Find bugs faster. • Time consuming/ excessive man power and
Disadvantages : resources required
• Requires lot of time in the beginning to set • Rate of progress (slope) remains same. Hence
up the test structure if complexity doubles, time required doubles)
• Most of bugs found but some bugs have to be
found only by directed testing For each approach: 0.5 marks for naming, 1 mark for
explanations, 1 mark for adv. & disadv (5 marks)

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6) Path 1: tpd (FF1) + tpd (xor) + tpd (nand) + tsu(FF2) = 3 + 2 + 2 + 4 = 11 ns (2 marks)
Path 2: tpd (FF2) + tsu(FF1) = 8 + 5 = 13 ns (2 marks)
critical path = path 2
TMIN (clk) = max (Tpath1, Tpath2) (1 mark)
Maximum frequency of operation = 1/13 ns = 76.92 MHz. (2 marks)

To ensure that the input signal can also accounted for, the input needs to be registered ie: the IN signal should
have been given from the previous stage through a flipflop and not given directly. (1 mark)
7) States for the design:
a. Idle
b. Got 1
c. Got 11
d. Got 110
e. Unlock, (1101 is obtained); door unlock signal is asserted high

State diagram:
States transitions from a -> e when inputs occur in the order 1,1,0,1; else it goes back to idle state (2 marks)

module door_lock_fsm ( (1 mark) IDLE: begin (2 marks:0.5 for each state)

input logic clk, if (key_in == 1)
input logic reset, next_state = S1;
input logic key_in, end
output logic unlock ); S1: begin
if (key_in == 1)
// (Parameters can also be used) next_state = S11;
typedef enum logic [4:0] { (2 marks:encoding) else
IDLE = 5'b00001, // next_state = IDLE;
GOT1 = 5'b00010, // end
GOT11 = 5'b00100, // S11: begin
GOT110 = 5'b01000, // if (key_in == 0)
UNLOCK= 5'b10000 } state_t; (1 mark:states) next_state = S110;
else
state_t current_state, next_state; next_state = IDLE;
end
// State transition logic (1 mark:logic) S110: begin
always_ff @(posedge clk or posedge reset) begin if (key_in == 1)
if (reset) (1 mark: reset) next_state = UNLOCK;
current_state <= IDLE; else
else next_state = IDLE;
current_state <= next_state; end
end UNLOCK: begin (1 mark)
unlock = 1;
// Next state and output logic ( next_state = IDLE;
always_comb begin (1 mark) end
next_state = current_state; default: next_state = IDLE;
unlock = 0; endcase
end
case (current_state) endmodule

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