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Course Outcomes
• CO1: Analyse static and dynamic characteristics of digital CMOS circuits.

• CO2: Design static and dynamic CMOS logic circuits for a given functionality,
speed, power consumption and area requirements.
• CO3: Demonstrate the performance of CMOS logic circuits designed using various
EC2013E VLSI DESIGN logic styles with the help of CAD tools.

• CO4: Design arithmetic circuits and memories using CMOS.

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Evaluation Policy Reference Books

— Relative Grading
1. J.M. Rabaey, A. Chandrakasan and B. Nikolic, Digital Integrated Circuits- A Design
— Mark Distribution: 0 Marks Perspective, 2nd Edn., Pearson Education, 2016
o Mid Test – 30
o Assmt - 20 2. N.H.E. Weste and David M. Harris, CMOS VLSI Design - a Circuits and System
o Final Exam – 50
Perspective, 4th Edn., Pearson Education Asia, 2010

3. S.M. Kang, Y. Leblebici and Chul Woo Kim CMOS Digital Integrated Circuits
Analysis and Design, 4th Edn., McGraw Hill, 2019

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3 4

History
— MOS field-effect transistor - Lilienfeld (1925), Heil (1935)
— Invention of the transistor (BJT) 1947 - Shockley, Bardeen, Brattain – Bell Labs
— First Bipolar digital logic: Harris (1956)
— First integrated circuit flip-flop with two transistors 1958 - Jack Kilby – Texas

Introduction
Instruments
— PMOS and NMOS transistors on the same substrate: Weimer (1962), Wanlass
(1965)
— PMOS-only logic until 1971 when NMOS technology emerged
— NMOS-only logic until late 1970s, when CMOS technology took over
— Invention of CMOS logic gates 1963 - Wanlass & Sah – Fairchild Semiconductor
— First microprocessor (Intel 4004) 1970 - 2,300 MOS transistors, 740 kHz clock
frequency
— Very Large Scale Integration 1978 - Chips with more than ~20,000 devices
— System on Chip (SoC) - 20 ~ 30 million transistors in 2002
— 2008: Intel Core2 Duo – 291,000,000 transistors
— 2012: NVIDIA GK110 (Kepler) ~7,000,000,000 transistors

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VLSI : Very Large Scale

Integration —
—
The 4004 had a feature size of 10 μm in 1971.
The Core 2 Duo had a feature size of 45 nm in 2008.
— Moore’s Law - Transistor count doubles every 18 months. — Manufacturers introduce a new process generation (also called a technology
node) every 2–3 years with a 30% smaller feature size to pack twice as many
— Integration: Integrated Circuits transistors in the same area.
o multiple devices on one substrate — Scaling can’t go on forever because transistors cannot be smaller than atoms.
— For feature sizes below 180 nm, transistors also leak a significant amount of
— How large is Very Large? current even when they should be OFF. Thus, chips now draw static power even
— SSI (small scale integration) - <10 gates when they are idle.
o 7400 series — One of the central challenges of VLSI design is making good trade-offs between
— MSI (medium scale) - < 100 gates performance and power for a particular application.
o 74161 counter — The cost of a chip includes nonrecurring engineering (NRE) expenses for the
— LSI - < 1,000 gates design and masks, along with per-chip manufacturing costs related to the size of
o 8-bit microprocessors the chip. In processes with smaller feature sizes, the per-unit cost goes down
— VLSI (1978) > 1,000 gates because more transistors can be packed into a given area, but the NRE increases.
— ULSI — The latest manufacturing processes are only cost-effective for chips that will sell in
— SoC (System On Chip) – 20 / 30 Million transistors in 2002 huge volumes

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7 8

Transistors in microprocessors Process generations

•20 μm – 1968
•10 μm – 1971
•6 μm – 1974
•3 μm – 1977
• 1.5 μm – 1981
•1 μm – 1984
•800 nm – 1987
•600 nm – 1990
•350 nm – 1993
•250 nm – 1996
•180 nm – 1999
•130 nm – 2001
•90 nm – 2003
•65 nm – 2005
•45 nm – 2007
•32 nm – 2009
•28 nm – 2010
•22 nm – 2012
•14 nm – 2014
•10 nm – 2016
•7 nm – 2018
•5 nm – 2020
•3 nm – 2022

•Future2 nm ~ 2024
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9 10

Clock frequencies of Intel Intel Core2 Duo…

microprocessors
— Even 291 million is a LOT of transistors
— Where are they used?
o Mostly for memory!
o Intel Core2 Duo: 4MB shared L2 cache, 32K Icache 32K Dcache on
each core
o 4*10242*8 + 2(64*1024*8) = 34,603,008 bits
o Around 6 transistors per bit of memory
o ~35,000,000 bits * 6 = ~210,000,000 transistors

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Why MOS/CMOS VLSI Design Flow

— CMOS (complementary metal oxide semiconductor) technology
continues to be the dominant technology for fabricating
integrated circuits (ICs or chips).
o CMOS contains two MOSFETs – NMOS and PMOS

— Advantages of CMOS technology

o Low power dissipation
o High noise margins in both states
o Relatively high speed
o Low cost
o Scalability.

— Complementary MOSFET (CMOS) technology is widely used in

today’s computers, CPUs and cell phones.

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14 16

17 18

17 18

Classification of CMOS digital

circuits

Digital Circuits

Static Circuits Dynamic Circuits

Classical Transmis CVSL Domino NORA TSPC

CMOS sion-gate gates Logic Logic Logic
CMOS Circuits Circuits Circuits

CVSL – Cascade Voltage Switch Logic

TSPC – True Single-Phase Clock

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MOS Transistor
— MOSFET – Metal Oxide Semiconductor Field Effect Transistor
— Fundamental block of MOS and CMOS digital integrated circuits
— 3 Layers
Basics of MOS o Metal Gate Electrode
— Since the 1970s, the gate has been formed from polycrystalline silicon
(polysilicon).
— Metal gates reemerged in 2007 to solve materials problems in advanced
manufacturing processes.
o Insulating Oxide Layer
o Substrate

— MOS Structure forms a capacitor

o Gate and substrate acts as two terminals (plates)
o Oxide layer acts as the dielectric.

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21 22

MOSFET - INTRODUCTION MOS transistor

— MOSFETs provide many advantages. — Add “source” and “drain” terminals to MOS capacitor
o They offer a very high input impedance and they are able to
consume very low levels of current.
o This is particularly important for integrated circuit technology where
power limitations are a major consideration. N+ N+ P+ P+
source drain source drain
o Relatively simple manufacturing process
P-substrate N-substrate
— Hence, it is possible to realize 106/107 transistors on an
integrated circuit (IC) economically. NMOS PMOS
— MOSFETs are widely used in applications such as switches and
amplifiers. They are also able to consume very low levels of
current and as a result they are widely used in microprocessors,
logic integrated circuits and the like.

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23 24

MOSFET: Device dimensions Circuit symbols forMOSFETs.

— Channel length (L): Distance between source-substrate junction
and drain-substrate junction near the oxide-substrate interface

— Channel Width (W): Width of the channel

— Oxide thickness (tox): Gate insulator thickness

Since the body is generally connected to a dc supply that is identical for

all devices of the same type (GND for NMOS, Vdd for PMOS), it is most
often not shown on the schematics

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25 26

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MOSFET Biasing Types of MOSFET

Type of Sign of — Enhancement Type (Enhancement Mode)
MOSFET
Substrate Capacitor Inversion Threshold o A MOS transistor which has no conducting channel region at zero
Type
Carriers Voltage gate bias
P - Type PMOS N-Channel Electrons +
— Depletion Type (Depletion Mode)
N - Type NMOS P-Channel Holes -
o A MOS transistor which has a conducting channel at zero gate bias

— In a n-channel MOSFET (NMOSFET), source is more negatively

biased in comparison with drain
Here, we will mainly consider Enhancement Type MOSFETs
— In a p-channel MOSFET (PMOSFET), drain is more negatively
biased in comparison with source

— Generally, the applied gate voltage and drain voltage are positive
in NMOSFET and negative in a PMOSFET

27 28

27 28

Two Terminal MOS Structure Energy Band Diagrams

EC
EF
q f Fn
EF = Ei Ei Ei
q f Fp
EF
Mass Action Law
2
• At Equilibrium np = ni (ni = 1.45x 1010 cm -3 at T = 300K) EV
• If the substrate is uniformly doped with NA, the equilibrium
electron and hole concentrations in the p-type substrate
ni2 Intrinsic N-type P-type
pp 0 ≅ N A np 0 ≅
NA ni2
• If the substrate is uniformly doped with ND, nn 0 ≅ N D pn 0 ≅
ND
29 30

29 30

Extrinsic Energy Bands

— The electron affinity, qχ, is the potential difference between the
For N-type: For P-type: conduction band level and the vacuum (free-space) level.

— The energy required for an electron to move from the Fermi level
p0 = N A = ni e(
Ei −EF )/kT into free space is called the work function, qΦ and is given by
n0 = N D = ni e(
EF −Ei )/kT

qΦ = q χ + (EC − EF )
ND ni
EF − Ei = kT ln EF − Ei = kT ln — The Fermi potential at the surface, called surface potential, Φs,
ni NA
is smaller in magnitude than the bulk Fermi potential, ΦF. (Why?)
ND ni
qφ Fn = kT ln qφ Fp = kT ln — The voltage which has to be applied between the gate and the
ni NA substrate, so that the bending of the energy bands near the
surface can be compensated i.e., the energy bands become flat
is called flat band voltage, VFB
φ Fn , φ Fp are the Fermi Potential of n and p type semiconductors.
qφ F = EF − Ei VFB = Φ M − Φ S

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31 32

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MOS Energy Band Diagram Energy band diagram of

Work function difference between Al and Si - depends on material used, a combined MOS structure
doping, etc.
Electric field ,ε

qVFB

33 34

33 34

MOS structure: Depletion, under

MOS structure: Accumulation
small gate bias.

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37 38

MOS structure: Strong Inversion MOS transistor operation

— Simple case: VD = VS = VB = 0 - Operates as MOS capacitor

— When VGS<VT0, depletion region forms - No carriers in channel to

connect S and D

Vg < V T0

Vs=0 Vd=0
depletion
source drain region
• When the condition is φ s = −φ F, strong inversion starts and the depletion
region has maximum depth
P-substrate
2ε si . 2φ F
xd =
qN A VB = 0
• At the start of Strong Inversion, MOSFET starts to turn on.
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MOS transistor operation Threshold voltage components

— When VGS > VT0, inversion layer forms — The value of the gate-to-source voltage VGS needed to cause
surface inversion (to create the conducting channel) is called the
threshold voltage V.
— Source and drain connected by conducting n-type layer (for
NMOS) — The 4 physical components affecting the threshold voltage of a
MOS structure
Vg > V T0 1. Work function difference between gate & channel (Flat-band
voltage)
Vs=0 Vd=0 2. Gate voltage to change surface potential
depletion 3. Gate voltage to offset depletion charge
source drain region 4. Gate voltage to offset fixed charges in gate oxide and silicon-oxide
interface
P-substrate

inversion
layer VB = 0

42 43

42 43

Threshold voltage (1) Threshold voltage (2)

— Work function difference VFB between gate — Now apply additional gate voltage to achieve
inversion: change surface potential by -2fF
and channel

VT 0 = VFB +  VT 0 = VFB - 2fF + 

This accounts for built-in voltage drop

44 45

44 45

Threshold voltage (3) Threshold voltage (4)

— Depletion region charge, due to fixed acceptor — Finally, correct for non-ideal fixed charges - Fixed
positive charged ions at boundary between oxide and
ions
substrate. Density = N OX (ions/cm 2)

QB 0 = - 2qN Ae Si - 2f F (charge/area) o Due to impurities, lattice imperfections at interface,

positive charge density Q ox = qN ox

— To offset this charge, need voltage – QB0/Cox o Correct with gate voltage = -Q ox/C ox

where, Cox=eox/tox

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Threshold voltage (for NMOS): Threshold voltage (5)

— What if substrate bias V SB is not zero?
QB 0 Qox
VT 0 = VFB - 2f F - - o Depletion width W changes
Cox Cox
o Need to account for different depletion region
charge

(VSB = 0): QB 0 = - 2qN Ae Si - 2f F

(VSB ¹ 0): QB = - 2qN Ae Si - 2fF + VSB

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48 49

Threshold voltage: general Threshold Voltage

QB Qox NMOS PMOS
VT = VFB - 2f F - -
Cox Cox
Substrate Fermi potential fF < 0 fF > 0
Q - QB 0
VT = VT 0 - B Depletion charge density QB < 0 QB > 0
Cox
Substrate bias coefficient g>0 g<0

Body effect
VT = VT 0 + γ ( −2ϕ F + VSB − 2ϕ F ) Source to bulk voltage VSB > 0 VSB < 0
coefficient + for NMOS
2qN Aε Si
γ= - for PMOS Threshold voltage
Cox VT0 > 0 VT0 < 0
(enhancement devices)

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50 51

Body effect
— Calculate the threshold voltage VT0 at VSB = 0, for a polysilicon
gate n-channel MOS transistor, with the following parameters:
substrate doping density NA = 1016 cm -3, polysilicon gate doping
density ND = 2 x 1020 cm -3, gate oxide thickness tox = 500 Å, and
oxide-interface fixed charge density Nox = 4 x 1010 cm -2, Fermi
potential = 0.55 V, ΦF(substrate) = -0.35V

— esi = 11.7e0, eox = 3.9e0, e0= 8.85x10-14 F/cm, q = 1.6x10-19 C

VT0

VSB (V)
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MOS transistor characteristics

— Cutoff: V GS < V t and IDS » 0

— Linear: V GS > V T, V DS < V GS-V T

Inversion layer connects drain and source. Current is almost

linear with V DS

— Saturation: V GS>V T, V DS³V GS-V T Channel is “pinched-off”.

Current saturates.

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55 56

Linear mode Saturation mode

— When VDS = VGS - VT:
— When VGS>VT, an inversion layer forms between drain and source
- Depth of channel depends on V between gate and channel - o No longer a voltage drop of VT from gate to substrate at drain
Drain end narrower due to larger drain voltage - Drain end depth o Channel is “pinched off”
reduces as VDS is increased
Vg > VT0
Vs=0 Vd > VGS-VT0
Vg > VT0
depletion
source drain
Vs=0 Vd < VGS-VT0 region
Channel depletion
source drain
(inversion region
layer) pinch-off point VB = 0
P-substrate
VB = 0
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57 60

Ideal MOS I-V Characteristics

Saturation I/V Equation x 10
-4

6
VGS= 2.5 V

— If VDS is further increased, no increase in current - Pinch-off point

5
moves closer to source - Channel between that point and drain is
depleted - High electric field in depleted region accelerates
Linear Saturation
4
electrons towards drain - To get saturation current, use linear VGS= 2.0 V
IDS

equation with VDS = VGS - VT 3

VDS = VGS - VT
I

2
W
(VGS - VTN )2
VGS= 1.5 V

I D = 12 µ nCox
L 1
VGS= 1.0 V

0
0 0.5 VDS 1 1.5 2 2.5

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Channel Length Modulation MOS I/V characterstics

— As VDS is increased, pinch-off point moves closer to source -
with
Effective channel length becomes shorter - Current increases VDS = VGS-VT channel-
due to shorter channel
VGS3 length

Drain current IDS

L' = L - DL Linear VGS2
modulation
1 1 1 DL
-> » (1 + )
L L - DL L L
VGS1 without
1 channel-length
= (1 + lVDS )
L Saturation modulation
I D ' = I D (1+ λVDS )
Drain voltage VDS
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63 64

Current-voltage equations of the Current-voltage equations of the

n-channel MOSFET p-channel MOSFET

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65 66

Example Problem
— Measured voltage and current data for a MOSFET are given
below. Determine the type of the device, and calculate the
parameters kn, VT0, and g. Assume fF = -0.3 V.

VGS (V) VDS (V) VSB (V) ID (µA)

3 3 0 97
4 4 0 235
5 5 0 433
3 3 3 59
4 4 3 173
5 5 3 347

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MOSFET As Switch MOSFET As a Switch

— We can view MOS transistors as electrically controlled switches — nMOS
o connected when gate is high
— Voltage at gate controls path from source to drain
o high output is degraded

g=0 g=1
— pMOS
o connected when gate is low
d d d
o low output is degraded
nMOS g OFF
ON
s s s

d d d

pMOS g OFF
ON
s s s

Slid
e 71
69

69 71

— nMOS examples (Vtn = 0.5V) — nMOS examples (Vtn = 0.5V)

o E.g. 1: Vg = 5V, Vi = 2V o E.g. 1: Vg = 5V, Vi = 2V
Vo = ? Vg = 5 > Vi + Vtn = 2.5 ⇒ Vo = 2V
o E.g. 2: Vg = 2V, Vi = 2V o E.g. 2: Vg = 2V, Vi = 2V
Vo = ? Vg = 2 < Vi + Vtn = 2.5 ⇒ Vo = 1.5V

— pMOS examples (Vtp = –0.5V) — pMOS examples (Vtp = –0.5V)

o E.g. 1: Vg = 2V, Vi = 5V o E.g. 1: Vg = 2V, Vi = 5V
Vo = ? Vg = 2 < Vi – |Vtp | = 4.5 ⇒ Vo = 5V
o E.g. 2: Vg = 2V, Vi = 2V o E.g. 2: Vg = 2V, Vi = 2V
Vo = ? Vg = 2 > Vi – |Vtp | = 1.5 ⇒ Vo = 2.5V

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73 74

The Depletion MOSFET The Depletion MOSFET (Cont..)

— The physical construction of a depletion MOSFET is identical to — Thus, for a depletion NMOS transistor, the channel conducts even
the enhancement MOSFET, with one exception: if VGS=0.

— The conduction channel is physically implanted (rather than — If the value of VGS is positive, the channel is further enhanced.
induced)! That is, more free electrons are attracted to the channel, and its
conductivity increases.

— If the value of VGS is negative, free electrons are repelled from the
channel! The conductivity of the channel is thus decreased -
channel depletion.
Implanted N-channel
— If the value of VGS becomes sufficiently negative, all of the free
electrons in the channel will be repelled - the channel is said to
be completely depleted, i.e., the depletion MOSFET is in cutoff!

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The Depletion MOSFET (Cont..) The Depletion MOSFET (Cont..)

— Thus, the negative value of VGS at which the channel is completely — An enhancement MOSFET and a depletion MOSFET are precisely
depleted is the threshold voltage VT for a depletion NMOS device. identical in nearly every way (e.g., same modes, same equations,
same terminal names).
— In other words, to have a conducting channel, the gate-to source
voltage VGS must be greater than the threshold voltage VT: (Just — 2 differences:
like the enhancement NMOS device!) o The threshold voltage for a depletion NMOS device is negative (i.e., VT
VGS > VT < 0). While the threshold voltage for a depletion PMOS device is
positive (i.e., VT > 0).
o The depletion MOSFET has a slightly different circuit symbol.

Depletion NMOS Depletion PMOS

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MOSFET SCALING – Technology Scaling - Small is

INTRODUCTION Beautiful
— MOS ICs have met the world’s growing needs for electronic
devices for computing, communication, entertainment, — Since the 1960’s the price of one bit of semiconductor memory
automotive, and other applications with steady improvements in has dropped 100 million times and the trend continues.
cost, speed, and power consumption.
— The cost of a logic gate has also undergone a similarly dramatic
— Such steady improvements in turn stimulate and enable new drop.
applications and fuel the growth of IC sales.
— This is because of “miniaturization”.
— If the MOSFET can continue this trend of continuous o By making the transistors and the interconnects smaller, more
improvement. circuits can be fabricated on each silicon wafer and therefore each
circuit becomes cheaper.
— The off-state current or the leakage current of the MOSFETs. o Speed and power consumption also reduced.

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79 80

Technology Scaling (Cont..)

— The “Moore’s Law” - Gordon Moore made an empirical — With scaling
observation in the 1960’s that the number of devices on a chip
doubles every 18 months. o Line width, MOSFET gate oxide thickness and the power supply
voltage reduces.
— Each time the minimum metal line width is reduced, a new o The reductions are chosen such that the transistor current density
technology generation or technology node is introduced. (Ion/W) increases with each new node.
o Eg: 0.18mm, 0.13mm, 90nm, 65nm, 45nm…generations. The
numbers refer to the minimum metal line width. — The smaller the transistors and shorter the interconnects lead to
smaller capacitances.
— At each new node, the various feature sizes of circuit layout, such o This causes the circuit delays to drop.
as the size of contact holes, are 70% of the previous node.
o Integrated circuit speed has increased almost 30% at each new
o i.e., the circuit size is reduced by 2. (70% of previous line width technology node
means ~50% reduction in area, i.e. 0.7 x 0.7= 0.49.)
o Since nearly twice as many circuits can be fabricated on each wafer
with each new technology node, the cost per circuit is reduced
significantly.

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Scaling
— The reducing capacitance and, especially, the power supply — Due to a phenomenon called “scaling”
voltage lowers the power consumption.
o Due to these reduction in C and Vdd, power consumption per chip has — Reduce physical dimensions such as channel length (L), width
increased only modestly per node in spite of the rise in switching (W) and gate oxide thickness (tox) are scaled
frequency, f and the doubling of transistors per chip at each
technology node.

— If there had been no scaling, doing the job of a single PC

microprocessor chip-- running 500M transistors at 2GHz using
1970 technology would require the electrical power output of a
medium-size power generation plant.

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Effects of Scaling Types of Scaling

— If fields are not controlled properly, — Traditionally Two types
o One dimension field nature in channel become multi-dimensional o Constant Voltage Scaling
o Channel charge is also controlled by drain/source voltage o Constant Field Scaling
o Long channel effect is lost
— Constant voltage scaling: voltages in the device are kept constant
— Long channel device behavior è Physical dimension is not à fields increase exponentially causing breakdown
important however, it is the electrical dimension
— Constant field/full scaling: fields in the device are kept constant
à reduction in applied voltage means takes more time to load
parasitics and thus is slower

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87 88

Parameters Affected in Scaling Parameters Affected in Scaling

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Parameters Affected in Scaling Generalized Scaling

— The supply voltages, while moving downwards, are not scaling as fast
as the technology
o Some of the intrinsic device voltages such as the silicon bandgap and the
built-in junction potential, are material parameters and cannot be scaled.
o The scaling potential of the transistor threshold voltage is limited. Making
the threshold too low makes it difficult to turn off the device completely.

— Therefore, a more general scaling model is needed, where

dimensions and voltages are scaled independently.
— Here, device dimensions are scaled by a factor S , while voltages are
reduced by a factor U.

— When the voltage is held constant, U = 1, and the scaling model

reduces to the fixed-voltage model.

— The general-scaling model offers a performance scenario identical to

the full- and the fixed scaling, while its power dissipation lies
between the two models (for S > U > 1).

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94 95

Short Channel Effects (SCE) Carrier velocity saturation

— Velocity saturation — Field along channel - As channel length is reduced, electric field
increases (if voltage is constant).
— Vth roll-off
— Electron drift velocity is proportional to electric field only for
— Channel Length Modulation (CLM) small field values - For large electric field, velocity saturates.
— Drain Induced Barrier Lowering (DIBL) — Current saturates before “saturation region” – Drain current is
reduced.
— Subthreshold Conduction
— Punch through

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99 102

Velocity Saturation Effects

— With VDD being fixed and as L becomes small, — For short channel devices and large enough VGS – VT
o This reduces IDSAT which now depends linearly on VG–VT rather than o VDSat < VGS – VT so the device enters saturation before VDS reaches VGS
– VT and operates more often in saturation
almost quadratically..
o IDSat has a linear dependence on VGS so current reduces for a given
control voltage
VDsat
vdsat = µ n Esat = µ n
L
W " V2 %
I Dsat =
µ nCox $(VGS − VT )VDSat − DSat '
L # 2 &
" VDSat %
= WCox vdsat $VGS − VT − '
# 2 &

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103 104

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VDS = 2.5V, W/L = 1.5

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105 106

Drain Induced Barrier Lowering

(DIBL)
— If the gate bias voltage is not sufficient to invert the surface, i.e., VGS — DIBL results in an increase in drain current at a given VG.
< VT, the carriers (electrons) in the channel face a potential barrier Therefore VT↓ as L↓.
that blocks the flow.
— Increasing the gate voltage reduces this potential barrier and, — Similarly, as VD↑, more QB is depleted by the drain bias, and
eventually, allows the flow of carriers under the influence of the hence ID↑ and VT↓.
channel electric field.

— The potential barrier is controlled by both VGS and VDS.

— In long channel devices, the gate is completely responsible for
depleting the semiconductor (QB).

— In very short channel devices, part of the depletion is accomplished

by the drain and source bias.

— If the drain voltage is increased, less gate voltage is required to

deplete QB, and the barrier for electron injection from source to drain
decreases. This is known as drain induced barrier lowering (DIBL).

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107 108

Punch Through Sub-threshold Current

— If the channel length becomes too short, the depletion region — Circuit speed improves with increasing Ion, therefore it would be
from the drain can reach the source side and reduces the barrier desirable to use a small Vt.
for electron injection. This is known as punch through.
— Vt must not be set too low, say 10mV, otherwise Ioff would be too
large.

— At Vgs < Vt, an N-channel MOSFET is in the off-state. However, an

undesirable leakage current can flow between the drain and the
source.

— The MOSFET current observed at Vgs<Vt is called the subthreshold

current.

— This is the main contributor to the MOSFET off-state current, Ioff. Ioff is
the Id measured at Vgs = 0 and Vds = Vdd.
— Drain current no longer controlled by gate
— In the absence of a conducting channel, the n+ (source) – p (bulk) –
— Transistors won’t “turn off” n+ (drain) terminals actually form a parasitic bipolar transistor.

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Sub-threshold Current MOSFET Capacitance

— The sub-threshold can be — 2 Types
approximated as VGS o Oxide-related capacitances
nkT /q
" − DS %
V

ID = ISe $1− e kT /q ' o Junction capacitances

# &

• It is important to keep Ioff very small in order to minimize the

static power that a circuit consumes even when it is in the
standby mode.
• For example, if Ioff is a modest 100nA per transistor, a cell-phone chip
containing one hundred million transistors would consume so much
standby current (10A) that the battery would be drained in minutes without
receiving or transmitting any calls.

116 118

116 118

Cross-sectional view and top view of Oxide-related/Overlap

a typical n-channel MOSFET. Capacitances
— Source and drain extend somewhat below the oxide by an
amount LD , called the lateral diffusion

— It gives rise to a parasitic capacitance between gate and source

(drain) that is called the overlap capacitance.

— The two overlap capacitances are called CGDO and CGSO.

CGSO = CoxWLD Cox = εox/tox

CGDO = CoxWLD

— These overlap capacitances are voltage-independent.

119 120

119 120

Channel Capacitance Transistor in Cut-off

— The most significant MOS parasitic circuit element is the gate-to- — When the transistor is off, no carriers in channel to form the other
channel capacitance CGC. side of the capacitor.
o Substrate acts as the other capacitor terminal
— CGC varies in both magnitude and in its division into three o The total capacitance CGC = W.L.Cox appears between gate and body
components CGCS, CGCD and CGCB (the gate-to-source, gate-to-
drain, and gate-to-body capacitances) depending upon the o Capacitance becomes series combination of gate oxide and depletion
capacitance
operation region and terminal voltages

121 122

121 122

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Transistor in Linear Region Transistor in Saturation Region

— Channel is formed and acts as the other terminal — Changing source voltage doesn’t change VGC uniformly
o E.g. VGC at pinch off point still V TH
o CGCB drops to zero (shielded by channel)
— Bottom line: CGCS ≈ 2/3·W·L·Cox
— Model by splitting oxide cap equally between source and drain,
CGCS = CGCD = WLCox/2. — Drain voltage no longer affects channel charge
o Set by source and V DSat
o Changing either voltage changes the channel charge
— If change in charge is 0, CGCD = 0

123 124

123 124

Oxide Capacitance Channel capacitance of MOS

transistor for different operation
regions
Operation
CGCB CGCS CGCD CGC CG
Region
Cutoff C oxWL 0 0 C oxWL C oxWL + 2C OXWL D

Resistive 0 C oxWL/2 C oxWL/2 C oxWL C oxWL + 2C OXWL D

Saturation 0 (2/3)C oxWL 0 (2/3)C oxWL (2/3)C oxWL + 2C OXWL D

125 127

125 127

Junction Capacitance Junction Capacitance

— This capacitive component is contributed by the reverse-biased
source-body and drain-body pn junctions.

— The depletion-region capacitance is nonlinear and decreases

when the reverse bias is raised.

— Bottom Junction
o which is formed by the source region (with doping ND ) and the substrate
with doping NA
o Area cap
o Cbottom = Cj·LS ·W, Cj the junction capacitance per unit area

128 129

128 129

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Capacitance Model Summary

— Side-wall junction — Gate-Channel Capacitance
o CGC ≈ Cox·W·L (|VGS| < |VT|)
o formed by the source region with doping ND and the p+ channel-stop o CGC = Cox·W·L (Linear)
implant with doping level NA+. — 50% G to S, 50% G to D
o The doping level of the stopper is usually larger than that of the o CGC = (2/3)·Cox·W·Leff (Saturation)
substrate, resulting in a larger capacitance per unit area. Its — 100% G to S
capacitance value equals
Csw = C'jsw xj (W+2Ls) — Gate Overlap Capacitance
o CGSO = CGDO = Cox·W.LD (Always)
where, capacitance per unit perimeter Cjsw = C'jswxj
o No side-wall capacitance is counted for the fourth side of the source — Total Junction/Diffusion Capacitance
region, as this represents the conductive channel. o Cdiff = Cbottom + Csw = Cj x AREA + Cjsw x PERIMETER
= Cj·LS·W + Cjsw·(2LS + W) (Always)
— No side-wall capacitance is counted for the fourth side of the — C s-diff = C s-bottom + C s-sw = C j x Source Bottom Area+ C jsw x (2LS
side
+ W) of the source
source region, as this represents the conductive channel
— C d-diff = C d-bottom + C d-sw = C j x Drain Bottom Area+ C jsw x (2LS + W) of the drain side

130 134

130 134

Capacitive Device Model Example

CGS = CGCS + CGSO — Compute the gate capacitances for an NMOS transistor. Assume
that drain and source areas are rectangular, and are 1 μm wide
CGD = CGCD + CGDO and overlap is 0.5 μm long. W/L = 1/0.25. Oxide Capacitance is 6
fF/μm 2.
CGB = CGCB
o a. VGS = 2.5 V, VDS = 2.5 V, 0.5 V
CSB = Csdiff o b. VGS = 0 V, VDS = 2.5 V, 0.5 V

CDB = Cddiff

CS = CGS + CSB

CD = CGD + CDB

136 137

136 137

MOSFET RC Model Transistor Sizing

— Channel Resistance
— Modeling MOSFET resistance and capacitance is very important for
transient characteristics of the device. o “ON” resistance of transistors
1 1
Rn = Rp =
!W $ !W $
µ nCox # & (VGS − VTn )
" L %n
(
µ pCox # & VSG − VTp
" L %p
)
RC Model Cox = ε ox / tox [F/cm 2 ], process constant

— Channel Resistance Analysis

o R ∝ 1/W (increasing W decreases R & increases Current)
— Time constant at drain, τD = CDRn o R varies with Gate Voltage
— Drain-Source (channel) Resistance, Rn o If Vtn ≈ |Vtp|, Rn µ p (W L ) p
=
o R n=V DS/ID Rp µ n (W L )n
o Linear region — If (W/L)n = (W/L)p , then Rn < Rp
— Rn = 1/[βn (VGS-Vtn)] o Since μ n > μ p
o Saturation region o To match resistance, Rn = Rp
— Rn = 2VDS/[βn (VGS-Vtn)2] — adjust (W/L)n = (W/L)p to balance for μn > μp

153 154

153 154

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Transistor Sizing (Cont…)

— Matching Channel Resistance
o there are performance advantage to setting R n = R p
o To set R n = R p
— define mobility ratio, r = μn /μp

(W L ) p
= r (W L )n
(W L ) p µn
=
(W L ) n
µp
o pMOS must be larger than nMOS for same resistance/current

— Negative Impact
o C Gp = rC Gn
o larger gate = higher capacitance

155

155

19