IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 37, NO.

10, OCTOBER 2002 1339

Op-Amps and Startup Circuits for CMOS Bandgap References

With Near 1-V Supply
Andrea Boni, Member, IEEE

Abstract—The design of bandgap-based voltage references

in digital CMOS raises several design difficulties, as the supply
voltage is lower than the silicon bandgap in electron volts, i.e.,
1.2 V. A current-mode architecture is used in order to address
the main issues posed by the low supply, but the implementation
of the operational amplifier and of dedicated startup circuits
deserves some attention. Even if nonstandard devices such as
depletion-mode MOS transistors may be helpful to manage the
supply scaling, they are seldom available and poorly character-
ized. Therefore, they must be avoided in a robust design featuring
a high portability. This paper proposes some circuit solutions
suitable for very low-supply-voltage operation and addresses the
main issues of achieving the correct bias point at the power on.
A few bandgap references were implemented in digital 0.35- and
0.18- m technologies featuring a nominal output voltage of about Fig. 1. Low-voltage current-mode CMOS bandgap reference. Either startup
500 mV and minimum supplies from 1.5 to 0.9 V. circuit A, right, or B , left, must be included for achieving the correct bias point
Index Terms—Bandgap-based voltage reference, CMOS at power on.
integrated circuits, low-voltage design, voltage reference.
II. CMOS BANDGAP REFERENCES
I. INTRODUCTION In a bandgap reference, an output voltage with a low sensi-
tivity to the temperature is obtained as the sum of a forward

R EFERENCE voltage generators with low sensitivity to

the temperature and supply are commonly required both
in analog and digital circuits such as DRAM or flash memories.
voltage drop on a p-n junction and a contribution proportional to
absolute temperature (PTAT). By setting the output voltage
approximately equal to the silicon bandgap measured in electron
Since the conventional implementation of the bandgap voltage volts, it is possible to nullify its temperature sensitivity [4], [5].
reference provides an output voltage almost equal to the silicon In CMOS technology, substrate vertical p-n-p bipolar junction
energy gap, measured in electron volts, it cannot be used in the transistors (BJTs) implement the p-n junctions [6]. Since the
latest deep-submicron technologies whose supply voltage is output voltage is about 1.2 V, this architecture cannot be used
already in the 1-V range [1]. A recently reported current-mode with the latest CMOS technologies, where the supply voltage
(CM) realization of the bandgap reference in CMOS technology ranges from 1.8 (0.18 m) to 1.2 V (0.13 m), and is expected
has the potential of circumventing the supply-voltage limitation to drop to 0.9 V with the next technology scaling [1]. Use of
[2]. However, the reported implementation requires a minimum nonstandard devices instead of p-n diodes might help to cope
supply voltage of about 2 V, makes use of nonstandard devices with the reduced supply voltage [7], [8], but at the cost of low
(depletion-mode MOSTs), and requires an external power reproducibility, poor portability of the design, and the need for
on-reset signal (POR) seldom available in analog and mixed- accurate models of nonstandard devices. On the contrary, by
signal circuits. A CM voltage reference with sub-1-V supply in means of resistive division, a reference voltage of about 0.7 V
BiCMOS technology was recently reported, but the low-voltage with sub-1-V supply has been demonstrated [9]. However, this
operational amplifier (op amp) cannot be implemented in digital technique is not suitable for high-precision reference working
CMOS [3]. In this paper, the design of bandgap references in a large temperature range, since the lowering of the output
with low supply voltage is discussed and some useful circuit voltage obtained through resistive division greatly increases the
techniques are proposed. Moreover, a few implementations curvature error. In the low-voltage CM bandgap reference of
with minimum supply voltages from 1.5 to 0.9 V in 0.35- Fig. 1, the voltages at and nodes are kept equal by the
and 0.18- m CMOS technologies are presented. op amp, and since , . Since the currents
in and are also equal, , and the voltage
drop on is . The current in is, therefore,
, where is
the voltage drop on . The first contribution is PTAT, while
Manuscript received December 18, 2001; revised June 26, 2002. This work the second decreases with the temperature: by choosing , ,
was supported by CNR, Progetto Finalizzato MADESS-II under Contract so that and mirroring by means of ,
0100083.PF48. an arbitrary with a very low temperature sensitivity can
The author is with the Dipartimento di Ingegneria dell’ Informazione, Uni-
versity of Parma, I43100 Parma, Italy (e-mail: andrea.boni@unipr.it). be obtained as the voltage drop on low-temperature coefficient
Publisher Item Identifier 10.1109/JSSC.2002.803055. resistor .
0018-9200/02$17.00 © 2002 IEEE
1340 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 37, NO. 10, OCTOBER 2002

III. BANDGAP REFERENCES FOR VERY LOW SUPPLY VOLTAGE

The implementation of the CM bandgap reference reported
in [2] exhibits some relevant limitations. The minimum supply
voltage is about 2 V, well above the supply voltage supported
by the latest CMOS generations. Moreover, the seldom-avail-
able depletion-mode MOST was used in the op amp, while a
design aiming at easy portability should rely on standard CMOS
devices only. Finally, a correct startup at power on was achieved
by means of an external POR signal, which may be unavailable
in analog and mixed-signal designs.
From inspection of the CM circuit in Fig. 1 the min-
imum theoretical supply voltage that can be supported is
, being the saturation voltage of
. Considering V and V, a
supply voltage as low as 0.75 V can be achieved in principle.
However, achieving a sufficient gain of the op amp and an
adequate stability margin is difficult at such a low supply
voltage.

A. Design of the Op Amp

The common-mode input voltage of the op amp in Fig. 1 is
V, independent of the supply voltage, being imposed
by the voltage drop across diode . Neglecting solutions in-
volving switching devices for an easier and less noisy imple-
mentation, the input stage of the op amp may be either a pMOS
or an nMOS differential pair. Three possible solutions are given
in Fig. 2. All the op amps include an R–C compensation network
for achieving a sufficient stability margin. In each configura-
tion, the bias current may be derived either from the bandgap
reference itself (dashed lines) or from the raw supply through
the pin. The former solution is usually preferred, providing
a lower sensitivity to the supply voltage, but it leads to a very
small voltage gain in the undesired bias point, i.e., when no cur-
rent flows in the bandgap core. Furthermore, the input transis-
tors should be designed with a large gate area and nonminimum
gate length in order to keep offset low. Indeed, the spread of the
reference voltages at wafer level is mainly contributed by the
op-amp offset voltage, while a minor contribution arises from Fig. 2. Low-voltage op amps for the CM bandgap. The bias current may be
the pMOS current mirrors and the substrate p-n-ps. derived either from the bandgap core (dashed lines) or from the raw supply
through the V pin.
In order to compare benefits and drawbacks of the reported
arrangements, let us consider a digital 0.35- m technology
with typical thresholds ( ) of 0.5-V nMOS and 0.6-V pMOS leading to a higher supply rejection. Nevertheless, due to the
transistors. Note that these values do not change significantly level shifting, the minimum tolerated supply is about 1.5 V and
in the latest digital CMOS technologies. In the pMOS solution, a higher offset voltage is expected.
Fig. 2(a), a supply voltage lower than 1.5 V pushes the tail-cur- The op amp in Fig. 2(c) is an evolution of the nMOS arrange-
rent generator in triode region and, consequently, causes ment aiming at the reduction of the minimum supply voltage
a decrease of the bias current and a degradation of the below 1 V. Indeed, the pMOS level shifters have been removed
common-mode rejection ratio (CMRR). At 1.2-V supply, the and the nMOS input devices are biased in weak inversion with a
input devices enter in weak inversion mode and the voltage gate voltage equal to , i.e., 0.65 V. The pMOS current mirror
of is a few tens of millivolts. Below 1.2-V supply, in the load of the input stage is replaced by a symmetric ac-
decreases abruptly and the op amp cannot provide enough loop tive load driven by a common-mode feedback control. Due to
gain and CMRR to keep the bandgap at the correct bias point. the very low supply voltage, common-mode feedback cannot
The nMOS differential pair with pMOS followers, Fig. 2(b), be implemented with a differential stage, but it can be achieved
allows the input common-mode voltage to be as low as 0 V, by splitting the tail-current generator into two identical tran-
thus simplifying the design of the startup circuit. Moreover, the sistors, and , whose gate voltages are controlled
bias current is almost independent of the supply voltage, by the outputs of the differential stage. The higher the output
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 37, NO. 10, OCTOBER 2002 1341

TABLE I
CIRCUIT PARAMETERS OF LOW-VOLTAGE OP AMPS IN FIG. 2

common-mode voltage, the higher the tail current. This feed-

back control fixes the voltage at the drain of and at
about , and being biased in weak inversion.
However, it should be remarked that any difference between the
desired common-mode voltage at the outputs of the differential
stage and the measured common-mode voltage, represented by
the voltage of , leads to a systematic offset voltage. This
is easily avoided if the drain current of is set to , i.e., equal
to the tail current of the differential stage. The minimum supply
voltage is determined by the load transistors and and
by the pMOS current mirrors in the bandgap core which enter in
Fig. 3. Proposed strategy for achieving the correct bias point at the power on.
triode region. Simulations show an open-loop gain higher than Transistors MX , MY , and MB must be driven by one of the three circuits at
60 dB at 27 C down to 0.75-V supply. Aspect ratios and bias the right. Circuit (I) requires a POR. Circuit (II) does not require any external
currents for the op amps in Fig. 2 are reported in Table I. signal and forces a constant current into the bandgap core. Circuit (III) does not
require any external signal, but is able to remove the injected current as soon as
the correct bias point is established.
B. Startup Issues and Countermeasures
The startup of the CM bandgap of Fig. 1 involves several is- current derived from the raw supply, without requiring any POR
sues since it exhibits an operating point with no current flowing signal. Here, the perturbing currents, and , should be as
in the bandgap core and . This point may be low as possible in order to minimize the perturbation on the
stable if the op amp does not provide enough gain, as a con- bandgap circuit at regime, but be effective in moving the bias
sequence of a bias current derived from the bandgap core or a point of the circuit away from the wrong bias point. To this aim,
limited input common-mode range. Moreover, startup may fail the op amp must provide enough gain at the wrong bias point
because of the op-amp offset voltage, pushing the bias point in and only the one in Fig. 2(b) proves to be adequate. The last
the wrong direction. The perturbation caused by the startup cir- solution, proposed in Fig. 3 at the bottom, avoids both the POR
cuit in the bandgap core must either be removed as the circuit signal and the perturbation on the bandgap reference. Here, a
settles at the correct bias point or have a minimal impact on the comparator compares the output reference voltage with a
behavior of the reference circuit. Known solutions for conven- rough reference developed from a diode by means of a resistive
tional bandgap circuits cannot be used here, since the output divider ( ), and the startup current is supplied as
reference voltage is even lower than a diode voltage drop. long as the output voltage is smaller than . It is important
Two alternative startup strategies are reported at either sides that the op amp provides enough gain for overriding the second
of the CM bandgap of Fig. 1. The solution at the right is based feedback loop provided by the startup comparator. Otherwise,
on a switch driven by a POR signal and temporarily closed at oscillatory behavior or settling at a wrong stable bias point may
power on, thus forcing the op-amp output at the low potential occur.
and causing some current to flow in the arms of the bandgap
core [2].
IV. EXPERIMENTAL RESULTS
The alternative strategy, shown on the left side of Fig. 1, is
expanded in Fig. 3. Three controlled-current generators inject Combining the op amps reported in Fig. 2 and the startup cir-
some current at nodes and of the bandgap core and also cuits in Fig. 3 with the basic CM bandgap core, three reference
provide some bias current to the op amp. Note that is not circuits were designed with (diode ratio) and 10 A
required if the op-amp bias is derived from the supply. must of bias current. The first one (BG-A) uses the pMOS op amp
be larger than in order to drive the circuit toward the correct [Fig. 2(a)] and the startup circuit with an external PON signal
bias point and to override any offset voltage of the op amp. Three [circuit (I) in Fig. 3], the second (BG-B) uses the nMOS op amp
possible ways of driving the pMOS devices are illustrated in with input followers [Fig. 2(b)] in conjunction with the simplest
the right side of Fig. 3. The first resorts to a POR signal. The startup [circuit (II) in Fig. 3]. Both bandgap references were im-
second is the least complex, since it makes use of a constant plemented in a digital 0.35- m technology and BG-B also in
1342 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 37, NO. 10, OCTOBER 2002

Fig. 6. From top to bottom, measured V over the 40 140 C 0 4

temperature range for the BG-A and BG-B (0.35 m implementation)
respectively.

Fig. 4. Chip photographs of the BG-A, BG-B (0.35 m technology), and

BG-B (0.18 m technology).

Fig. 7. Measured distribution of V of 0.35-m BG-B over 16 samples at

different supplies (1.8 and 2 V) and temperatures (0 C, 27 C, 85 C, 125 C).

Fig. 5. Measured V at different supply voltages and temperatures for

BG-A, BG-B (0.35 m implementation) and BG-B (0.18 m implementation).

0.18 m (see Fig. 4). was set by design at about 500 mV;
the measured at different supply voltages and over a large
temperature range ( 40 C 140 C) is reported in Figs. 5 and
6. The measurements demonstrate a minimum supply voltage
of about 1 and 1.5 V for the BG-A and BG-B implementations,
respectively. The measured supply sensitivity is 2 mV/V with Fig. 8. Simulated reference voltage V provided by the CM bandgap
a supply ranging from 2.5 to 1 V, and 6.5 mV/V with a supply using the op amp of Fig. 2(c) (diamonds), together with its supply sensitivity
(triangles) as functions of the supply voltage.
ranging from 2.7 to 1.5 V, for BG-A and BG-B, respectively.
Fig. 7 shows the distribution of the of BG-B (0.35- m im-
plementation) voltage over 16 samples and at different supplies The simulated output noise at 100 kHz, 27 C, is 230 nV/ Hz
and temperatures, highlighting a 4 value lower than 4%. Re- for BG-A (1.2 V), 205 nV/ Hz for BG-B (1.5 V, 0.35 m), and
garding the 0.18- m implementation, measurements over more 170 nV/ Hz for BC-C (0.9 V).
than 1000 samples show a standard deviation of about 3.5 mV at
27 C. Furthermore, a reference for sub-1-V supply (BG-C) was
ACKNOWLEDGMENT
designed in the 0.35- m technology, using the nMOS op amp
with fully differential active load [Fig. 2(c)] and the startup cir- The author would like to thank Prof. C. Morandi of the Uni-
cuit (III) in Fig. 3. The simulated reference voltages at 27 C are versity of Parma for fruitful discussions and the critical review
reported in Fig. 8, top graph, together with their correspondent of this paper. The support of A. Marmiroli, M. Vendrame,
supply sensitivities. Taking into account the tolerances affecting and S. Lucherini of ST Microelectronics for the technology
the devices and a temperature range extending down to 0 C, access and the characterization of the 0.18- m bandgap is also
BG-C exhibits a minimum supply as low as 0.85 V. acknowledged.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 37, NO. 10, OCTOBER 2002 1343

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