12 External Memory Interfacing

Syllabus
Memory address decoding, interfacing 8031/8051 with ROMEPROM and Data
ROM.
Contents
12.1 Interfacing and Timing Diagrams
for Memory Interfacing
Winter-15, Marks 7
12.2 Memory Address Decoding
12.3 Interfacing Examples
Winter-10,11, 13,14,
12.4 Accessing Extermal Data Memory in 8051C
Summer-11,13,14,15, -" Marks 7

12.5 Short Questions and Answers

(12 - 1)
Microprocessors and Microcontrollers 12-2 External Memory lnterfacing

12.1 Interfacing and Timing Diagrams for Memory Interfacing

GTU: Winter-15

We have seen that 8051 has internal data and code memory with limited memory
capacity. This memory capacity may not be sufficient for some applications. In such
situations, we have to connect external ROM/EPROM and RAM to 8051 microcontroller
to increase the memory capacity. We also know that ROM 1s used as a program memory
and RAM is used as a data memory. Let us see how 8051 accesses these memories.

12.1.1 External Program Memory

Fig. 12.1.1 shows a map of the 8051 program memory.
Program memory

FFFFH FFFFH
EA 0
60 kbytes ACCesS
External External
memory 64 kbytes
OR Extermal

1000H
OFFFH
4 kbytes EA =1
Internal Access
0000 0000
Internal
memory

Fig. 12.1.1 The 8051 program memory

In 8051, when the EA pin is connected to Vcc, program fetches to addresses 0000F1
through OFFFH are directed to the internal ROM and program fetches to addresses
1000H through FFFFH are directed to external ROM/EPROM. On the other hand when
EA pin is grounded, all addresses (0000H to FFFFH) fetched by programn are directed to

Po Do
D,
EA ROM/EPROM
8051
A
T
ALE A
CLK Addr.
P Ag
PSEN A46
OE
Fig. 12.1.2 Accessing external program
memory
TECHNICAL PUBLICATIONS An up thrust for knowledge
 Microprocessors and Microcontrollers 12 -3
Extermal Memory Interfacing
the external
ROM/EPROM. The PSEN signal is used to activate output enable signal of
the external
ROM/EPROM, as shown in the Fig. 12.1.2.
As shown in the Fig. 12.1.2, the port 0is
lower order 8-bit address in the initial used as a multiplexed address/bus. It gives
T-cycle and later it is used as a data bus. The
R-bit address is latched using external latch
and ALE signal generated by 8051. The
port 2 provides the higher order &-bit
for external program memory read cycle.
address. Fig. 12.1.3 shows the timing waveforms

ALE

PSEN

PORT 0 Ab -Ay INSTR

Ag -Ay

PORT 2
Ag -A15 Ay -A15
Fig. 12.1.3 Timing waveforms for external program memory rad cycle

The lower part of program memory stores the vector addresses for various interrupt
service routines. Fig. 12.1.4 shows the vector address map. Each interrupt is assigned
with afixed location in program memory. For example, external interrupt 0 is assigned
to location 0003H. The interrupt service locations are spaced at &-byte intervals such as

0033 H

002B H

0023 H
Serial Port
001B H
Timer 1 8 Bytes
Interrupt External Interrupt1
0013 H
Locations
000B H
Timer 0
0003 H
External Interrupt 0
0000 H
RESET

In the lower part of program memory

Pig. 12.1.4 InterruptVector locatlons
up thrust for knowledge
TECHNICAL PUBLICATIONS- An
MicroprOcesSors and Microcontrollers 12- 4 Extermal Memory Interfacing

for External Interrupt 1

0003H for Exterrnal Interrupt 0, 000BH for Timer 0, 0013H
routine must begin at
001BH for Timer 1, etc. If interrupt is going to be used, its service
its service location is
corresponding location. If the interrupt is not going to be used,
available as general purpose program memory.
Instructions to Access External ROM/Program Memory
The Table 12.1.1 explains the instructions to access external ROM/program memory.
Mnemonic Operation
MOVC A, @A Copy the contents of the external ROM
DPTR address formed by adding A and the DPTR,
to A.

MOVC A, @A +PC Copy the contents of the external ROM

address formed by adding A and the PC, to

Table 12.1.1

12.1.2 External Data Memory

Fig. 12.1.5 shows a map of the 8051 data memory.
Data memory

Internal data memory External data memory

SFRS) FFFFH
FFH
Accessible by
indirect Accessible by
Upper addressing
direct
128 addressing
only AND
64 kbytes
8011 Xtermaf
TFH menoryY
Accessible by
Lower direct & indirect
128
addressing

O000H

Fig. 12.1.5 A map of the 8051 data memory

The 8051 can address upto 64 kbytes of external data memory. The "MOVX"
instruction is used to access the external data memory. The intermal data memory space
for 8051 is divided into three blocks : Lower 128 bytes, Upper 128bytes and SFRs. The
upper addresses and SFRs occupy the same block of address space, 80H through FPr
TECHNICAL PUBLICATIONs An up thrust for knowledge
MicroproceSSors and Microcontrollers 12-5 Extemal Memory Interfacing

although they are physically separate entities. As shown in the Fig. 12.1.5, the upper
address space is accessible by indirect addressing only and SFRs are accessible by direct
addressing only. On the other hand, lower address space can be accessed either by
direct addressing or by indirect addressing.
Fig. 12.1.6 shows the circuit diagram for
connecting external data memory. The
multiplexed address/data bus provided by port 0 is demultiplexed by external latch and
ALE signal. Port 2 gives the higher order address bus. The RD and WR
signals from
8051 selects the memory read and memory write
operation, respectively.
Pa
D,
EA +Vcc RAM

8051ALE
CLK
ADDR

RD
P P PAGE
BITS

WR
WR

Fig. 12.1.6 Accessing external data memory

Fig. 12.1.7 (a) and (b) shows the timing waveforms for
external data memory read
and write cycles, respectively.

ALE

PSEN
RD

PORT 0 Ao -Ay DATA IN A, -Ay KINSTR IN

FROM RIOR DPL FROM PCL

PORT 2 P2.0-P2.7 OR A_-As FROM DPH Ag -Ays FROM PCH

Fig. 12.1.7 (a) Timing waveforms for external data memory read cycle
TECHNICAL PUBLICATIONS -An up thrust for knowledge
MicroprOceSsors end Microcontrollers
12 - 6
Extemal Memory Interfacing

ALE

PSEN

WR

PORT 0
Ao-Ay DATA OUT -Ay INSTR IN
FROM RIOR DPL FROM PCL

PORT 2 P2.0-P2.7 OR Ag-A45 FROM DPH Ag-A15 FROM PCH

Fig. 12.1.7 (b) Timing waveforms for external data memory write cycle
Instructions to Access External Data Memory
The Table 12.1.2 explains the instruction to access external data memory.

Mnemonlc Operation
MOVX A, Rp Copy thecontents of the external address in Rp to A
MOVX A, ODPTR Copy the contents of the external address in DPTR to A.
MOVX @Rp, A Copy data from Ato the external address in Rp.
MOVX QDPTRA Copy data from A to the external address in DPTR.
Table 12.1.2
12.1.3 mportant Points to Remember in
Accessing External Memory
" All external data moves with external ROM or external RAM involve the
A register.
While accessing external memory, Kp can address 256 bytes and DPTR can address
64 kbytes.
" MOVX
instruction is used to access external RAM or I/O
When PCis used to access external ROM, it is incremented by 1 (to pointto thenext
addresses.
instruction) before it is added to Ato form the physical address of external ROM.

TECHNICAL PUBLICATIONS
Microprocessors and Microcontrollers 12-7 Extermal Memory Interfacing
Review Questions

1. Explain interfacing and timing diagrams for external

program memory interfacing.
2. Explain interfacing and timing iagrams for
external data memory interfacing.
3. Dratw and explain interfacing of external program
ROM with 8051. GTU: Winter-15, Marks 7
12.2 Memory Address Decoding
We know that read/write memories consist of an
array of registers, in which each
register has unique address. The size of the memory is Nx M as
where N is the number of registers and M is the word length, in shown Fig. 12.2.1 (a)
in
number of bits.
For Example : If memory is having 12 address lines and 8 data
lines, then
Number of registers/memory locations = 2N =212 = 4096.
Word length = Mbit = 8-bit .
For Example : If memory has 8192 memory locations, then it has 13
address lines.
The Table 12.2.1 summarizes the memory capacity and
address lines required for
memory interfacing.

Memory Capacity Address Lines Required

1K= 1024 memory locations 10

2K= 2048 memorylocations 11

4 K-4096 memory locations 12

8K= 8192 menory locations 13

16 K= 16384 memnory locations 14

32 K = 32768 memory locations 15

64 K= 65536 memory locations 16

Table 12.2.1
AS Shown in the Fig. 12.2.1 (a) memory chip has 11 address lines A1oA one chip
select (CS) and two control lines. Read (RD) to enable output buffer and write (WR) to
P ne input buffer. The internal decoder is used to decode the address lines.
Fig, 12.2.1 (b) shows the logic diagram of a typical EPROM (Erasable Programmable
Read Only Memory) with 4096 (4 K) registers. It has 12 address ines Aj1-A one chip
select (CS), one read control signal. Since EPROM is aread only memory, it does not
Tequire the (WR) signal.
TECHNICAL PUBLICATIONs An up thrust for knowledge
Microprocessors and Microcontrollers 12- 8 External Memory lnterfacing
Input
data

Input bufter WR
EPROM
decoder
Internal decoder
Internal 4096 x 8

A10 AgT
RIW
Memory
2048 x 8
(Nx M)
Ao A

Output buffer Output buffer -CS

RD RD
Output Output
data data

(a) Logic diagram for RAM (b) Logic diagram for EPROM
Fig. 12.2.1

The memory interfacing requires to :

Select the chip.
Identify the register.
Enable the appropriate buffer.
Microprocessor/microcontroller system includes memnory devices and I/O devices. It
is important to note that microprocessor can communicate
(read/write) with only one
device at a time, since the data, address and control buses are
common for all the
devices. In order to communicate with memory or I/0 devices, it is
the address from the necessary to decode
microprocessor/microcontroller.
common address decoding techniques.
The following section describes

Address Decoding Techniques :

Absolute decoding/Full decoding
" Linear decoding/Partial decoding
Absolute decoding
In absolute decoding techrnique, all the higher
memory chip, and the memory chip is selected address lines are decoded to select tie
only for the specified logic levels o
these high-order address lines; no other logic
the memmory interface with absolute
levels can select the chip, Fig. 12.2.2 show
used in large memory systems. decoding. This is normally
addressing technique

TECHNICAL PUBLICATIONs An up thrust for

 Microprocessors and Microcontrolers 12 - 9
External Memory Interfacing

Ag

RD
-WR
-PSEN
D, Do Ag Ag Ay A OE D,-D Ag Ag A,-Ap OE WR
EPROM (1K) RAM (1 K)
Vcc

Ay3
A44
A15

K5
74LS138
A10

A2 A11
Fig. 12.2.2 Absolute decoding technique

Memory Map

Memory ICs A15 14 A13 12 A11 A10 Ag A Ay Ag As A Ag A Ag Address

Starting address 0 0 0 0 0 0 0 0 0 0 00001H
of EPROM

End address of 00 0 0 0 0 1 1 1 1 11 1 1 11 03FFH

EPROM
Starting address
of RAM
0 1 00 0 0 0 0 0 0 0 0 0 2000H

End address of 0 0 1 0 0 0 1 1 1 1 11 1 1 11 23FFH

RAM
Table 12.2.2

TECHNICAL PUBLICATIONS -An up thrust for knowledge

MicroprOcessors and Microcontrollers 12- 10 External Memory Interfacing

Linear decoding
In small systems, hardware for the decoding logic can be eliminated
by using
individual high-order address lines to select memory chips. This is referred to as linear
decoding. Fig. 12.2.3 shows the addressing of RAM with linear decoding technique. This
technique is also called partial decoding. It reduces the cost of decoding circuit, but it
has a drawback of multiple addresses (shadow addresses).

Ag-A15

RD
WR
PSEN

D,-Do Ag Ag AyAo OE D,-Do Ag Ag Az-A OE WR

EPROM (1 K) RAM (1 K)
CS CS

Ar5
Fig. 12.2.3 Linear decoding
Fig. 12.2.3 shows the addressing of RAM with linear decoding techrnique. A15 address
line, is directly connected to the chip select signal of EPROM and after inversion it is
connected to the chip select signal of the RAM. Therefore, when the status of A1s line 1s
'zero', EPROM gets selected and when the status of Ag line is 'one' RAM gets selected.
The status of the other address lines is not considered, since those address lines are
used for generation of chip select signals.
Memory Map :

Memory ICs A15 A14 A13 A12 A11 A10 Ag Ag Ay A6 Ag A Ag Ag A1 0

Starting address of EPROM 0 X X X X X 0 0 0000H
0 0 0
End address of EPROM X X X 03FFH
X X 1 1 1 11 1
1
Starting address of RAM 1 X XX X X 8000H
0 0 0 0 0
End address of RAM 1 X X X X X 1 83FFH
1 1 11 1 1 1 1

Table 12.2.3
TECHNICAL PUBLICATIONS - An up
 Microprocessors and Microcontrollers 12- 11
Extemal Memory Interfacing
Review Question
1 Write a short note on nemory address
decoding.
12.3 Interfacing Examples GTU : Winter-10, 11,13,14, Summer-11,13, 14,15|
Example 12.3.1 LDraw and explain 8051
connection to
orogram to read 1O0 bytes of data from Pl and save theexternal RAM (8K ×8). Write a
5100H location. data in external RAM starting at
GTU : Summer-15, Mark 1
Solution:

P2.0
P2.7 IO4r

PO.0
PO,7
RST AgrAys
8051
Dy-D,
PsEN
WR PSEN
RD WR
ALE RD
ALE
Reset

A13 OE D, Do Ay-Ag WR
A14 8K(RAM)
A15

Fig. 12.3.1
RAM Map
As Ais Ajg Ap Aj AoA A A,A, As AAs A A Ag Address
RAM
0 1 0 00 0 0 Start 4000H

1 0 1 1 End 5FFFH
1 1 1 1 1 1
:Initialize counter
MOV R0, # 100
MOVDPTR, # 5100H
MOV P1, # OFFH ;Configure P1 as an input port
BACK : MOV A, P1 ; Get data from P1
Send it to extermal RAM
MOVX @ DPTR, A
INCDPTR
DNZ R0, BACK
PUBLICATIONS -An up thrust for knowledge
 12- 12 External Memory Interfacing
Microprocessors and Microcontrollers

12.3.2 Discuss interfacing of external 32 K EPROM and 32 K RAM with the

Example
microcontroller. Drato diagram and explain.
lines (A A,). The
Solution: To address 32 K EPROM and RAM needs 15 address
RAM. When A1s is low
remaining address line As is used for selection of EPROM or
EPROM is selected and when Ass is high RAM is selected.

Xy P2.0
P2.7

PO.0 AyA15
PO.7
RST

8051 Do-D,

PSEN PSEN
WR WR
EA
RD
ALE ALE
Reset

OE D,-Do AuAo OE D-D A-An WR

32 K(EPROM) 32 K(RAM)
CS

A15

Fig. 12.3.2
Memory Map

Memory As Au Ags Ayg A1 A1o Ag Ag A, As As A As A, A, A, Address

0 8000H
(Start)
RAM
1 1 1 1 1 1 1 1 1 1 1 FFFFH
1 1 1
(End)
0 0 0 0 0 0000H
0 0
(Start)
EPROM
1 1 1 1 1 1 ZFFFH
1 1 1 1 1 1 1
(End)

Example 12.3.3 An 8051 based system requires

each and two chíps of EPROM of size 2
external memory of four 4 kbyte
kbytes. The EPROM starts at address 0
SRAM address map follows EPROM map,
Give the complete interface.
TECHNICAL PUBLICATIONS An up thrust for knowledge
MicroproceSsors and Microcontrollers 12- 13 Extermal Memory Interfacing

Solution AysAy5 Do-D

PSEN Reset
WRRD ALE
EPROM0 EPROM1

OE
DD5
A-A_4

2K(EPROM) 1EPROM

CS

A1

OE
D-Do
A1oAo
(EPROM)
2K EPROM0

WR 4RAM
RAM
3
Ay-Ay
(RAM) 2RAM
RAM
1|
CS 1RAM 2RAM 3RAM 4RAM
D-D,
4K

OE

P2.0
Xy P2.7 PO.7
PO.0 FSEN
WR ALE
GND
8O51
awuoauH
B
RST EA
Voc A13A12
R

Fig. 12.3.3

TECHNICAL PUBLICATIONS- An up thrust for knowledge

Microprocessors and Microcontrollers 12- 14 Extermal Memory Interfacing

A15 A4 A13 A A1 A10 Ag Ag Ay A_ As A Ag A, A Ag Address

.****

0 0 2000H
1 1 1 1 27FFH
EPROMO
1 1 1 1 1 1 1
....... ******

1 1 0 0 0 0 0 0 0 2800H
1 1 1 2FFFH
EPROM1
1 1 1 1 1 1 1 1

1 1 0 0 0 0 3000H
RAMO
1 1 1 1 11 1 1 1 1 1 3FFPH
1 00 0 0 0 4000H
RAM1
1 1 1 1 1 1 1 1 1 1 4FFFH
0 0 0 0 0 5000H
RAM2
1 1 1 1 1 1 1 1 1 1 1 SFFFH
0 1 1 0 0 6000H
RAM3
1 1 1 1 1 1 1 1 1 1 6FFFH

Example 12.3.4 Give the complete block schematic of an 8051 based system having following
specifications.
64 kB of program memory.
64 KB of data memory.
Make use of 16 Kx 8-bit memory chips and 74 LS 138 decoders.
Indicate cleariy, the addresses selected for the memory chips.
Solution: See Fig. 12.3.4 on next page.
Memory Map :
Memory A1s A4 A3 A12 A11 A10 Ag Ag A, Aç As A4 A3 Az Aj Ag Address

EPROM1 Start 0 0 0 0000H

EPROM1 End 1 1 1 1 1 1 1 1 1 1 1 1 1 3FFFH
...

EPROM2 Start 1 0 0 0 0 0 4000H

EPROM2 End 1 1 1 1 1 1 1 1 1 ZFFFH
1 1 1
EPROM3 Start 1 0 0 8000H
EPROM3 End 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 BFFFH
EPROM4 Start 0 0 CO00H
0 0 0 0
EPROM4 End 1 1 1 1 1 1 1 1 1 1 FFFFH
1 1 1
RAM1 Start 0 0
0000H
0
RAM1 End 0 1 1 1 1 1 1 1 3FFFH
1 1 1 11
RAM2 Start 0 1 0 0 0 0 4000H
0
RAM2 End 0 1 1 1 1 1 1 7FFFH
1 1 1 1 1 1 1

TECHNICAL PUBLICATIONs An up thrust for knowledae

Microprocessors and Microcontrollers 12- 15 Extermal Memory Interfacing
RAM3 Start 0
0 0 0 8000H
RAM3 End 1 0 1 1 1 1 1 1 1 1 1 1 1 1 BFFFH
RAM4 Start 1 1 0 0
RAM4 End 1 1 1 1 1
00 0 0 CO00H
1 1 1 1 1 FFFFH
1
Table 12.3.1

AA
DJD,
WADE

AA
DgD,
WAOE

DAA
AWROED,

A,
D;
D,
WROE

A
O,D,
AAOE

DD,
AO

A
D,D, EPROM
K
8
E

138
74
LS

AA
L

Fig 12.3.4
knowledge
TECHNICAL PUBLICATIONS - An up thrust for
Microprocessors end Microcontrollers 12 -16 Extermal Memory Interfacing

Review Questions

1. DraO and explain 8051 connection to external RAM (8K × 8). GTU : Winter-10, Marks 3
with the microcontroller. Draw
2. Discuss interfacing of external 32K EPROM and 32K RAM
diagram and explain important handshaking signals. GTU : Summer-11, Marks 7
and an
3. Explain connection between an 8031 and an external memory consisting of 16K EPROM
GTU : Winter-11, Marks 7
8K of static RAM with external memory timing diagram.
microcontroller at address 8000H
4. Interface three memory chips as per below details with 8051
GTU : Winter-13, Marks 7
onwards. Draw neat and clean dingram.
1. Chip-1, 42K x8 bit data ROM
2. Chip-2, 1K x 8 bit RWM
3. Chip-3, 1K x 8 bit RWM
5. Explain with necessary dingram, interfacing of 32K external ROM with 8051.
GTU : Summer-13, Marks 7
6. Explain interfacing of external 32K EPROM and 16K RAM with 8051. Draw circuit diagram.
GTU: Winter-13, Marks 7
7. Explain interfacing of external 16kK EPROM and 16K RAM with 8051. Draw circuit dingram.
GTU : Summer-14, Marks 7

8. Draw and describe interfacing of 8K x 8 data chip with 8051. GTU : Summer-15, Mark 1

12.4 Accessing External Data Menmory in 8051C

For accessing external memory 8051C uses XBYTE[LOC] command. Here, loc gives
the address in the range of 000OH - FFFFH. For using XBYTE command we have to
include absacc.h header file in the program.
Example 12.4.1 Write an 8051 C program to store ASCII codes for numbers 0to 3 nthe
extern RAM rom aadress 0000
Solution :
# include <reg51.h>
# include <absacc.h> /* file included for XBYTE */
void main (void)
XBYTE [O] = '0;/*Write ASCII of 0to location 0 */
XBYTE [1] = '1;/* Write ASCII of 1to location 1 */
XBYTE [2] = 2 ; /*Write ASCII of 2to location 2 */
XBYTE (3] = 3': /* Write ASCII of 3to location 3 */
}
Example 12.4.2 Write an 8051 Cprogram to read 5 bytes of data fromn external RAM romt
location 1000H and output the same on port P1.

TECHNICAL PUBLICATIONS - An up thrust for knowledge

 Microprocessors and Microcontrollers 12 - 17 External Memory Interfacing

Solution:
# include <reg51.h>
# include <absacc.h>
vold maln (void)
{ unsigned char i;
for (i = 1000; i < 1005; i ++)
P1 = XBYTE [0) ; / Read data byte from RAM and send it to P1 */

Review Question

1. Explain accessing of external data memory in 805IC.

12.5 Short Questions and Answers
Multiple Choice Questions
Q.1 While reading external menory, PSEN is activated every oscillator periods.
.... ..
6 bË 5
4 3 [Ans. : a]

Q.2 act as a read strobe to external program memory.

a ALE EA
......:

PSEN d RST [Ans. : c]

Q.3 When EA = 1, the address range for internal progran memory is through
0000H, OFFFH bi 0000H, FFFFH
........
1000H, OFFFH 1000H, FFFFH [Ans.: a)
Q4 When EA = 1, the address range for internal program memory is through

**.*****t
0000H, OFFFH b 0000H, FFFFH
1000H, 0OFFFH 1000H, FFFFH [Ans. : d]

Q.1 Write the memory capacity of microcontroller 8051.

Ans. : The memory capacity of microcontroller 8051 is 64 kbytes.
Q.2 List any two instructions to access external data memory. (Refer Table 12.1.2)

Q.3 List any two instructions to access external ROM / program memory.
(Refer Table 12.1.1)

TECHNICAL PUBLICATIONS- An up thrust for knowledge