CST202

COMPUTER ORGANIZATION
&
ARCHITECTURE

1
MODULE 1
Basic Structure of computers – functional units - basic operational concepts -bus
structures. Memory locations and addresses - memory operations, Instructions, and
instruction sequencing, addressing modes.

Basic processing unit – fundamental concepts – instruction cycle – execution of a complete

instruction - single bus and multiple bus organization
What is a computer?
a computer is a sophisticated electronic calculating machine that:
Accepts digitized input information processes the information according to a list of internally
stored instructions and produces the resulting output information.

Information handled by a
computer

Instructions Data
Instructions
Commands that govern the transfer of information.
Eg: MOV R0, R1

The instruction specifies arithmetic and logic operations to be performed.

Eg: ADD R0, R1

Program
List of instructions that perform a specific task stored in the memory, the processor fetches the
program instruction by instruction from the memory and performs the desired operation.

Eg:
Data
Numbers and encoded characters are used as operands by the instructions and stored as digital
information.

Each number or character is encoded as a string of binary digits called Bits.

ASCII is a 7-bit code for representing alphanumeric characters.

What are the functional units of a computer?

Real world Input unit
Computer
The computer accepts (reads the data)
coded information through the input unit.
Keyboard Memory
Audio input Input Input device: keyboard
…… Unit
Interfac
e When a key is pressed the corresponding
letter or digit is automatically translated to
Processor binary code and transmitted over cable to
either memory or processor.

Examples of input devices: Keyboard, joystick, trackballs, mouses, scanner, microphone etc.
Output unit

Output processed results to the outside world.

Accept processed results provided by the computer in
specific binary form, Convert the information in binary
form to a form understood by an output device.
Interface

E.g: screen, printer, plotter, speaker, etc.

Memory Unit Store programs and data in Binary format.

Primary storage
Fast Memory
Programs must be stored in memory while they are being executed.
Made up of a large number of semiconductor storage cells.
Data stored in memory is processed in the form of memory words.
For accessing memory words specify their address.
Time taken to access(memory read/write) a memory word is called memory access time.
Memory is organized so that the contents of one word containing n bits can be stored or retrieved in one basic
operation.

Word length: no. of bits in each word.

A typical computer has word lengths ranging from 16 - 64 bits.

A distinct address is associated with each word.

Addresses are numbers that identify successive memory locations.

A given word is accessed by giving its address

Memory operations
Read: retrieving information from memory.

Write: storing data to memory.

Random Access Memory (RAM)
RAM is used to store the programs and data being used by the CPU in real-time.

The data on the RAM can be read, written, and erased any number of times.

RAM is a hardware element where the data being currently used is stored.

It is a volatile memory.

Types of RAM:
Static RAM, or (SRAM) which stores a bit of data using the state of a six transistor memory cell.
Dynamic RAM, or (DRAM) which stores a bit data using a pair of transistor and capacitors which
constitute a DRAM memory cell.
Read Only Memory
ROM is a type of memory where the data has been prerecorded.
Data stored in ROM is retained even after the computer is turned off i.e, non-volatile.

Types of ROM:
Programmable ROM, where the data is written after the memory chip has been created.
It is non-volatile.
Erasable Programmable ROM, where the data on this non-volatile memory chip can be
erased by exposing it to high-intensity UV light.

Electrically Erasable Programmable ROM, where the data on this non-volatile memory chip
can be electrically erased using field electron emission.

Mask ROM, in which the data is written during the manufacturing of the memory chip.
 Memory hierarchy – cache, main memory, Secondary memory

Mai Cach
memory memor Processo
n e
y r

Bu
s

Organization of cache and main memory

Secondary storage
Store large amounts of data
Non-volatile storage device.
Slow access compared to main memory.
A secondary storage device is also known as an auxiliary storage device or external storage.

Magnetic Storage
Magnetic Tape
Magnetic Hard Disk
Floppy Disk
Optical Storage
Arithmetic and Logic Unit (ALU)
An arithmetic logic unit (ALU) is a digital circuit used to perform arithmetic and logic operations.
Arithmetic operations such as addition and subtraction.
Logic operations such as comparison of numbers.

Represents the fundamental building block of the central processing unit (CPU) of a computer.
Operations are done by ALU on the data stored in the registers of the processor.
A register is a high-speed storage element available as part of a CPU.
Each register can store one word of data.
In order to execute an instruction, operands need to be brought into the ALU from the memory.
Operands are stored in general-purpose registers available in the ALU.
Access times of general-purpose registers are faster than the cache.
Results of the operations are stored back in the memory or retained in the processor for immediate
use.
Control Unit

The operations of the input, memory, ALU, and output unit are coordinated by the control unit.
Control unit generates timing signals which determine “when” a particular operation takes place .
A large set of control lines carries the signals used for timing and synchronization
Basic Operational Concepts:
15

Processor R0
5
Typical Instructions LOCA 10
R1
ADD LOCA, R0
…

Rn
Typical Instructions

Load LOC, R1
Add R1,R0 Processor R0
5
LOC 10
R1
15
R2

Rn
Typical Instructions

Sub R1,R0
Processor R0
5
LOC
R1 15
10
R2

Rn
Basic Operational Concepts: Connection Between the Processor and
Memory
 Typical Operating Steps (Fetch Cycle)
Programs reside in the memory, entered through input devices .

PC (Program counter) has address of the first instruction or next instruction to be

executed
The contents of PC are transferred to MAR (Memory Address Register) and send over
system bus to the memory.

A Read signal is sent to the memory by control unit .

The instruction (addressed word) is fetched and loaded into MDR (Memory Data
Register) after duration of memory access time .

The contents of the MDR were transferred to IR (Instruction Register).

Now the instruction is ready to be decoded and executed.
 Typical Operating Steps (Execution Cycle)

Get operands for ALU from:

General-purpose register (R0, … Rn-1) or from Memory
(address to MAR, Read from mem, data to MDR, to ALU)

Perform the operation in ALU

Store the result back to:
General-purpose register (R0, … Rn-1) or to Memory
(address to MAR, result to MDR, Write to mem)

During the execution, PC is incremented to point to the next instruction.

In addition to transferring data between memory and processor, the computer accepts data from
input devices and sends data to output devices. Instructions to handle I/O transfers, I/O Address
Register, I/O Data Register, etc are provided.
Registers

Instruction register (IR): holds the instruction that is currently being executed.
Program counter (PC):
Contains the address of the next instruction to be fetched and executed.

During the execution of an instruction, the contents of the PC are updated with the address of
the next instruction to be executed.

Keeps track of the execution of a program .

Memory address register (MAR) : Holds the address of the location to be accessed.
Memory data register (MDR) : This contains the data to be written into or readout of the
addressed location.
General-purpose register (R0 – Rn-1) : Used to store data on which ALU performs its
operations .
Memory read
 MAR 8
Memory write
9
Assume IR holds
instruction Store R2,LocA …
MDR
And processor start
execution 100 Load LocB,R1

101 Load LocC,R2

PC 103
102 Add R1,R2
R0 103 Store R2,LocA
R1 50 …
IR Store R2,LocA
R2 68 (LocA)110
R3 (LocB)111 50
CONTRO
L UNIT
(LocC)112 18

ALU

Rn
 MAR 8
Memory write (LocA)110
9
R0
…
R1 50 MDR

100 Load LocB,R1

R2 68
101 Load LocC,R2
R3 PC 103
102 Add R1,R2

103 Store R2,LocA

…
IR

(LocA)110
Rn
(LocB)111 50
CONTRO
L UNIT
(LocC)112 18

ALU
 MAR 8
Memory write (LocA)110
9
R0
…
R1 50 MDR 68
100 Load LocB,R1
R2 68
101 Load LocC,R2
R3 PC 103
102 Add R1,R2

103 Store R2,LocA

…
IR

(LocA)110
Rn
(LocB)111 50
CONTROL
UNIT

(LocC)112 18

ALU
 MAR 8
Memory write (LocA)110
9
R0
…
R1 50 MDR 68
100 Load LocB,R1
R2 68
101 Load LocC,R2
R3 PC 103
102 Add R1,R2

103 Store R2,LocA

…
IR Store R2,LocA
(LocA)110
Rn
(LocB)111 50
CONTROL WRITE
UNIT CONTROL

(LocC)112 18

ALU
 MAR 8
Memory write (LocA)110
9
R0
…
R1 50 MDR 68
100 Load LocB,R1
R2 68
101 Load LocC,R2
R3 PC 104
102 Add R1,R2

103 Store R2,LocA

…
IR Store R2,LocA
(LocA)110 68
Rn
(LocB)111 50
CONTROL
UNIT

(LocC)112 18

ALU
Interrupt
Normal execution of programs may be interrupted if some device requires urgent servicing.
To deal with the situation immediately, the normal execution of the current program must be
interrupted.
Procedure of interrupt operation
The device raises an interrupt signal.
The processor provides the requested service by executing an appropriate interrupt service-routine
The state of the processor is first saved before servicing the interrupt .

Normally, the contents of the PC, the general registers, and some control information are stored
in memory .

When the interrupt-service routine is completed, the state of the processor is restored so that the
interrupted program may continue .
Classes of Interrupts
Program Generate Interrupt
Generated by some condition that occurs as a result of an instruction execution such as
arithmetic overflow, division by zero, attempt to execute an illegal machine instruction, or
reference outside a user’s allowed memory space.
Timer Interrupt
Generated by a timer within the processor. This allows the operating system to perform certain
functions on a regular basis .
I/O Interrupt
Generated by an I/O controller, to signal normal completion of an operation or to signal a variety
of error conditions .
Hardware failure
Generated by a failure such as power failure or memory parity error.
Bus Structures
A group of lines that serves as a connecting path for several devices is called a bus.

In addition to the lines that carry the data(data bus), the bus must have lines for address (address
bus)and control purposes (control bus).

The simplest way to interconnect functional units .

The devices connected to a bus vary widely in their speed of operation .
–Some devices are relatively slow, such as printers and keyboards.
–Some devices are considerably fast, such as optical disks .
–Memory and processor units operate are the fastest parts of a computer.

An efficient transfer mechanism thus is needed to cope with this problem .

–A common approach is to include buffer registers with the devices to hold the information
during transfers.
Eg : A processor is faster than a printer, so whenever a processor wants to print, sends data to
the buffer register associated with a printer. Once the buffer register gets loaded with data sent
by the processor can engage in some other work and once the printer becomes available it can
start printing of data available in the buffer register without intervention by the processor.

–Another approach is to use a two-bus structure and an additional transfer mechanism.

Memory Location, Addresses, and Operation
To retrieve information from memory, either for one word or one byte
(8-bit), addresses for each location are needed.
A k-bit address memory has 2k memory locations, namely 0 – 2k-1,
called memory space.

24-bit address memory: 224 = 16,777,216 =24 x 220 =16M (1M=220)

32-bit address memory: 232 = 22 x 230 = 4G (1G=230)
1K(kilo)=210
1T(tera)=240
It is impractical to assign distinct addresses to individual bit locations in the memory.

The most practical assignment is to have successive addresses refer to successive

byte locations in the memory – byte-addressable memory.

Byte locations have addresses 0, 1, 2, … If word length is 32 bits, the successive

words are located at addresses 0, 4, 8,…
Big-Endian and Little-Endian Assignments

Ordering of bytes within a larger object, eg how a word is stored in memory.

Big-Endian: lower byte addresses are used for the most significant bytes of the word .

Little-Endian: opposite ordering. lower byte addresses are used for the less significant
bytes of the word .
Differentiate between big-endian and little-endian byte ordering.
Consider a computer that has a byte-addressable memory organized
as 32-bit words. A program reads ASCII characters entered at a
keyboard and stores them in successive byte locations, starting at
location 1000. Show the contents of the memory word at locations
1000 and 1004 after the name Johns has been entered in case:
Big Endian Byte ordering is used
Little Endian Byte ordering is used
(ASCII equivalent of characters in John in hex will be 4A, 6F, 68,
6E, 73)
(You can indicate unused byte locations using XX).
1000 4A 6F 68 6E 1000 6E 68 6F 4A
1004 73 XX XX XX 1004 XX XX XX 73
XX XX XX XX XX XX XX XX
A memory has 32-bit address and byte-addressable, what is the size of the memory (in
bytes)?
32-bit address, byte addressable memory
No of bytes = 232 = 230 x 22
= 4G bytes (1G = 230)

A memory has 24-bit address and word-addressable with a word length of 32 bits,
what is the size of the memory (in bytes)?

No of words = 224 = 220 x 24

No of bytes = No of words x (bytes/word)
= 220 x 24 x 22 (1 word = 4 bytes)
= 64M bytes (1M = 220)
Given a byte-addressable memory with a capacity of 1024 MB. How many bits are
required to address each memory address?

Memory capacity = 1024 MB

= 210 x 22 0 = 230 Bytes
30 bits in each address

Given a byte-addressable memory with a capacity of 2GB. Find the range of address
values possible in this system.

Memory capacity = 2GB

= 21x 23 0 =
231 Bytes
Address Range : 0 to 231 -1
1. A memory has 16-bit address and byte addressable. Word length is 32 bits.
How many words can we store in such a memory?

No of bytes in memory = 216 bytes

1Word =32 bits (4 bytes)
No of words = 216 / 22 = 210 x 26 / 22
=16 K words (1K = 210)
 4-types of Operations Specified by Instructions.

Data transfers between the memory and the processor registers

Arithmetic and logic operations on data
Program sequencing and control
I/O transfers
Assembly Language Notations
Move LOC, R1 = R1←[LOC]
Add R1, R2, R3 = R3 ←[R1]+[R2]
Basic Instruction Types
Eg: C=A+B Zero Address Representation
3 address representation
Add A,B,C Push A
Push B
Add
2 address representation Pop C TOS
Mov A,R1
TOS-1
Add B,R1
Mov R1,C
Add🡨TOS=TOS+(TOS-1)
1 address representation
Mov A
Add B Accumulator register
is default here
Mov C
Evaluate (A+B) X(C+D) and Store the Result in memory location X

3 Address representation

Add A,B,R1 R1🡨A+B

Add C,D,R2 R2🡨C+D
[X]🡨R1 X R2
MUL R1,R2,X
Two-Address Representation
(A+B) x (C+D)

MOV A,R1 R1🡨[A]

ADD B,R1 R1🡨R1+[B]
MOV C,R2 R2🡨[C]
ADD D,R2 R2🡨R2+[D]
MUL R1,R2 R2🡨R1*R2
MOV X,R2 [X]🡨R2
One-Address Representation
(A+B) x (C+D)

LOAD A AC🡨[A]
ADD B AC🡨AC+[B]
STORE T [T]🡨AC
LOAD C AC🡨[C]
ADD D AC🡨AC+[D]
AC🡨AC *[T]
MUL T [X]🡨AC
STORE X
Zero Address Representation
(A+B) x (C+D)
 Instructions and Instruction Sequencing

At the end of each instruction execution,PC get incremented by 1 (means skip 4 bytes here because 1
memory word size is 4 bytes here ),and pointing to next memory word . Suppose PC hold address ‘I’ now ,
after the execution ith instruction PC will point “i+4”.
This program gives sum of n
numbers they are stored at
locations labelled as
NUM1,NUM2,NUM3,…NUMn.

Here it executes instructions one

after another sequentially and
finally store result in memory
location labelled as “sum”.

We can reduce the number of

instructions in the given program
if we introduce loop ,But it will
alter sequential execution and
cause branching ..
Program to add n numbers using loop .

Here we have a branching situation ,

If the branching condition is true
( here branching condition is R1>0) then it will
execute the loop body again ; in that case
control need to transfer in to memory location
labelled as “LOOP” ,this location is not
sequentially next to current instruction .So PC
current value should updated to make it
pointing to location “LOOP”.

If branch condition is false now , then it should

execute sequentially next instruction present
just after the loop body .ie “Move R0, SUM “
here. In this case, PC contains the correct
address, no further Updation is required over
PC .
{ because we know that , while executing an
instruction by processor PC automatically get
updated and pointing to sequentially next
instruction in the program .}
Condition Codes
The processor keeps track of information about the results of various operations for
use by subsequent conditional branch instructions. This is accomplished by recording
the required information in individual bits ,called condition code flags . These flags
are usually grouped together in a special processor register called the condition
code register or status register .
Individual condition code flags are set to 1 or cleared to 0 depending on the outcome
of the operation performed .
Condition code flags
N (negative) : Set to 1 if the result is negative ;otherwise cleared to 0.
Z (zero) : set to 1 if the result is 0;otherwise cleared to 0.
V (overflow) : set to 1 if arithmetic overflow occurs ;otherwise cleared to 0.
C (carry) :set to 1 if a carry out results from the operation ;otherwise cleared to 0.
Different instructions affect different flags
 Namitha Ramachandran

65
 Addressing Modes
The different ways in which the location of an operand is specified
in instruction is referred to as addressing modes.
 Register Mode

The operand is the contents of a processor register.

Clear R1 Move R1, R2

Absolute Mode/Direct Mode

The operand is in a memory location.
The address of the memory location is given explicitly in the instruction.

Clear A or Move LOC, R2

 Namitha Ramachandran
Register Addressing Diagram

Example
MOV R1, R2
R1=3

R2
 Namitha Ramachandran

Direct /Absolute Addressing

Example
MOV A, R1

A = 101

100
101 0 1 0 4
102
103
104
0104 R1
R1
Immediate mode

Operand is given explicitly in the instruction.

E.g. Move #200, R0

Can be used to represent constants.

A=B+6
MOV B,R1
ADD #6,R1
MOV R1,A
Example

MOV #5 ,R1

5 🡪 R1
Indirection and Pointers

Indirect Mode: The effective address of the operand is the content

of a register or memory location whose address appears in the
instruction.

Indirection is denoted by placing the name of the register or the

memory address given in the instruction in parenthesis.

The register or memory location that contains the address of an

operand is called a pointer.
Indirect Addressing Diagram Namitha Ramachandran

Example
MOV (A), R1

A = 101
100
101 1 0 4
102
103
104 1 1 0 A

R1
 Register Indirect AddressingNamitha Ramachandran
•Operand is in register or memory cell pointed to by
contents of register Ri
•EA = [Ri]
•Large address space (2n)
•One fewer memory access than indirect addressing
 Namitha Ramachandran

Register Indirect Addressing Diagram

Example
MOV(R2), R1
R1

R2 = 3

R3 = 5
 Before addition After Addition
Add(R1),R0
100

R0 10
60
102

R1 B (label of 108)
104

B 108 50(operand)
 100
Add(A),R0
Before addition After Addition
R0 10
60
102

A 104 B(label of 108)

B 108 50(operand)
 R0 0
Example N 5

NUM1 10

20

30
R2 NUM1
40

50

60
R1 5
70

SUM
 R0 10
Example N 5

NUM1 10

NUM1+4 20

NUM1+8 30
R2 NUM1+4
NUM1+12 40

NUM1+16 50
R1 4
NUM1+20 60

NUM1+24 70

SUM
 R0 30
Example N 5

NUM1 10

NUM1+4 20

NUM1+8 30
R2 NUM1+8
NUM1+12 40

R1 3 NUM1+16 50

NUM1+20 60

NUM1+24 70

SUM
 R0 60
Example N 5

NUM1 10

NUM1+4 20

NUM1+8 30
R2 NUM1+12
NUM1+12 40

NUM1+16 50
R1 2
NUM1+20 60

NUM1+24 70

SUM
 R0 100
Example N 5

NUM1 10

NUM1+4 20

NUM1+8 30
R2 NUM1+16
NUM1+12 40

NUM1+16 50
R1 1
NUM1+20 60

NUM1+24 70

SUM
 R0 150
Example N 5

NUM1 10

NUM1+4 20

NUM1+8 30
R2 NUM1+20
NUM1+12 40

NUM1+16 50
R1 0
NUM1+20 60

NUM1+24 70

SUM
LOOP EXIT
 R0 150
Example N 5

NUM1 10

NUM1+4 20

NUM1+8 30
R2 NUM1+20
NUM1+12 40

NUM1+16 50
R1 0
NUM1+20 60

NUM1+24 70

SUM 150
LOOP EXIT
Indexing and Arrays
Index mode: the effective address of the operand is generated by
adding a constant value to the contents of a register .

The register used may be either a special register provided for this
purpose, or, more commonly, it may be any one of a set of
general-purpose registers in the processor.

It is referred to as an index register

The index mode is useful in dealing with lists and arrays .

We denote the Index mode symbolically as X(Ri), where X denotes

the constant value contained in the instruction and Ri is the name of
the register involved.

The effective address of the operand is given by EA=X+(Ri).

The contents of the index register are not changed in the process of
generating the effective address .

Effective Address of the operand is generated by adding a constant

value to the contents of the register .
 Indexed / Displacement Addressing
Namitha Ramachandran

● Indexed Address
● EA = Index Register value + Relative Addr
Example
MOV 3(R1), R2
3

+
100
R1 = 100 101
102
103 1 1 0 A
104

R2
Example for Index Addressing
R0 LIST+32
LIST+16
LIST
SUM1 30
(2)
R1 10 0 30
(1)
(10)
SUM2 45
(20) R2 20 0 45
(30)
(2) SUM3 60
R3 30 0 60
(20)
(25) R4 2
1 0
(30)
 Variations of Indexed Addressing Mode
A second register may be used to contain the offset X, in which case we can write the
Index mode as (Ri,Rj) .

The effective address is the sum of the contents of registers Ri and Rj .

The second register is usually called the base register .

This mode implements a two-dimensional array .

Another version of the Index mode use two registers plus a constant, which can be
denoted as X(Ri,Rj) .

The effective address is the sum of the constant X and the contents of registers Ri and Rj
This mode implements a three-dimensional array .
Relative mode
Effective Address of the operand is generated by adding a constant
value to the contents of the Program Counter (PC).
•Variation of the Indexing Mode, where the index register is the PC
instead of a general purpose register.

•When the instruction is being executed, the PC holds the address of

the next instruction in the program.

•Useful for specifying target addresses in branch instructions .

•Addressed location is “relative” to the PC, this is called “Relative
Mode” .
 Relative Addressing (PC-Relative)
Namitha Ramachandran

● Relative Address
● EA = PCvalue + Relative Addr
0
1
PC= 2 2
Example
MOV 100(PC), R1 +
100
X = 100
101
102 1 1 0 A
103
104

R1
Autoincrement mode

Effective address of the operand is the contents of a register specified

in the instruction.
After accessing the operand, the contents of this register are
automatically incremented to point to the next consecutive memory
location.
(R1)+

E.g., if the word size is 4 bytes (32 bits):

Autoincrement increments the contents by 4.
Autodecrement mode
Effective address of the operand is the contents of a register
specified in the instruction.
Before accessing the operand, the contents of this register are
automatically decremented to point to the previous consecutive
memory location.
-(R1)
if the word size is 4 bytes (32 bits):
Autodecrement decrements the contents by 4.
Autoincrement and Autodecrement modes are useful for
implementing “Last-In-First-Out” data structures.
An Example of Autoincrement Addressing
1 WORD=4 BYTES
NUM1 (1000) 10

NUM2 (1004) 20

NUM3 (1008) 30

NUM4 (1012) 40

NUM5 (1016) 50

N (1020) 5

SUM (1024) 150

R0 150
0 R2 10
50

R1 5
0
Part 2
Basic processing unit – fundamental concepts – instruction cycle – execution of a
complete instruction - single bus and multiple bus organization
Fundamental Concepts
Basic Steps Involved in the Executing an Instruction

1)Fetch the contents of the memory location pointed to by the PC. The contents of this
location are loaded into the IR (fetch phase-fetch instruction). IR ← [[PC]]

2)Assuming that the memory is byte addressable and each instruction comprises 4
bytes , increment the contents of the PC by 4 . PC ← [PC] + 4 (fetch phase-fetch )

3)Decode the instruction and identify which operation to perform and on which
operands (Decode Phase).

4)Carry out the actions specified by the instruction in the IR (execution phase).
In the case where an instruction occupies more than one word, steps 1 and step 2
must be repeated as many times as necessary to fetch the complete instruction .

These two steps are usually referred to as the fetch phase ; step 3 constitutes the
execution phase .
Processor Organization (Single Bus Organization of
the datapath inside a processor )
Data and address lines of the external memory bus are connected to the internal processor bus via
the memory data register, MDR and the memory address register MAR respectively.

MDR has two inputs and two outputs, data may be loaded to MDR from either the memory bus or
from the internal processor bus.
The input of MAR is connected to the internal processor bus and its output is connected to the
external memory bus .
Control lines of the external memory bus are connected to the instruction decoder and control
logic block.This unit is responsible for issuing the signals that control the operation of all the
units inside the processor and for interacting with the memory bus .

Registers R0…Rn-1 provided for General purpose use by programmers Some dedicated
special-purpose registers such as index registers and stack pointers are also available for
programmers.

Three registers Y,Z and TEMP are used by processor for temporary storage during execution of
some instructions ,these registers are not available for programmers also never used for storing
data generated by one instruction for later use by another instruction .
The MUX selects either the output of register Y or a constant value 4 to be provided as
input A of the ALU .
The constant 4 is used to increment the content of PC by 4 in case memory word size
is 4 bytes .
If ALU need 2 inputs for operation,in that case MUX select content of register Y as A
input and content directly available now in internal data bus as B input of ALU .

As instruction execution progresses , data are transferred from one register to another,
often passing through the ALU to perform some arithmetic or logic operation.

The instruction decoder and control logic unit is responsible for implementing the
actions specified by the instruction loaded in the IR register .

The decoder generates the control signals needed to select the registers involved and
direct the transfer of data .
Instruction Execution
During instruction execution data are transferred from one register to
another , or to ALU( in case of arithmetic or logic operations).
Perform an arithmetic or a logic operation and store the result in a
processor register .
Fetch contents of a given memory location and load them into processor
register .
Store a word of data from a processor register into a given memory
location .

The registers ,the ALU and the interconnecting bus are collectively
referred to as the DATAPATH .
 For transferring contents of register R1 to
Register Transfers
register R4 perform the following:
Enable the output of register R1 by setting
R1outto 1 .
(this place the contents of R1 on the
processor bus )
Enable the input of register R4 by setting
R4in to 1 .
( this loads data from the processor bus
into register R4).
All operations and data transfer within the
processor take place within time period
known as processor clock .
Implementation for one bit of register Ri
A two-input multiplexer is used to select the data applied to the input
of an edge-triggered D -flip flop .

When a control input Rin is equal to 1 , the multiplexer selects the data
on the bus .This data will be loaded into the flip flop at the rising edge
of the clock .When Ri =0 , the multiplexer feeds back the value
currently stored in the flip flop .

The Q output of the flip flop is connected to the bus via a tri-state gate .
When Riout =0 the gate output is in the high impedance state
( electrically disconnected state ---open circuit state of the switch ).
When Riout=1 ,the gate drives the bus to 0 or 1, depending on the
value of Q.
Performing an Arithmetic or Logic Operation
The ALU is a combinational circuit that has no
internal storage.
It perform arithmetic and logic operations on the
two operands applied to it’s A and B inputs .

The result is temporarily stored in register Z.

What is the sequence of operations to add the

contents of register R1 to those of R2 and
store the result in R3?

1) R1out, Yin
2) R2out, SelectY, Add, Zin
3) Zout, R3in
Step 1: output of register R1 and input of register Y are enabled , causing the
contents of R1 to be transferred over the bus to Y .

Step 2: multiplexer’s select signal is set to select Y ,causing the multiplexer to gate
the contents of register Y to input A of the ALU .At the same time , the contents of
register R2 are gated onto the bus and hence to input B. ADD line of ALU is set to 1
,causing the output of the ALU to be the sum of the two numbers at inputs A and B
.the sum is loaded in to register Z ,because its input control signal is activated .

Step 3 : The contents of register Z are transferred to the destination register

R3. This last transfer cannot be carried out during step 2 because only one
register output can be connected to the bus during any clock cycle .
 Fetching a Word from Memory

To fetch a word of information from memory , the processor has to

specify the address of the memory location where this information
is stored and request a Read operation .

The information to be fetched represents an instruction in a

program or an operand specified by an instruction .

When the requested data are received from the memory they are
stored in register MDR , from where they can be transferred to
other registers in the processor.
 The response time of each memory access varies (cache miss, memory-mapped
I/O,…).
To accommodate this, the processor waits until it receives an indication that the
requested operation has been completed (Memory-Function-Completed, MFC).

Consider the instruction Move (R1),R2 , the action needed to execute

this instruction are :
🡪1)MAR ← [R1]
🡪2)Start a Read operation on the memory bus
🡪3)Wait for the MFC response from the memory
🡪4)Load MDR from the memory bus
🡪5)R2 ← [MDR]
In the above example these actions may be carried out as separate steps ,but some
can be combined into a single step .Each action can be completed in one clock
cycle, except 3 which require more clock cycles depending on the speed of the
addressed device.
🡪1)MAR ← [R1]
🡪2)Start a Read operation on the memory bus
🡪3)Wait for the MFC response from the memory
🡪4)Load MDR from the memory bus
🡪5)R2 ← [MDR]

The above actions can be rewrite as

1) R1out , MARin , Read
2) MDRinE , WMFC
3) MDRout , R2in
Timing of a Memory Read operation
Assume that the output of MAR is enabled all the time .Thus contents of MAR are
always available on the address lines of memory bus .

When a new address is loaded into MAR , it will appear on the memory bus at the
beginning of next clock cycle .

A Read control signal is activated at the same time MAR is loaded and this will
generate a read command MR on the bus .

MDRinE is waiting for a response from memory ,and data from memory are loaded
into MDR at the end of clock cycle in which MFC signal is received .

In the next clock cycle ,MDRout is activated to transfer the data to register R2 .
Storing a Word In Memory
Executing the instruction
Move R2,(R1) requires the sequence
1 R1out , MAR in
2 R2out , MDR in , Write
3 MDR outE ,WMFC
Execution of a Complete Instruction

Instruction Cycle :
->Fetch instruction
->Decode instruction ( Identify opcode and operands )
-> Execute
-> Write Back Result (in register /memory)

Example :Add (R3), R1

🡪Fetch the instruction
🡪Fetch the first operand (the contents of the memory location pointed to by R3)
🡪Perform the addition
🡪Store the result into R1
Execution of Branch Instructions

A branch instruction replaces the contents of PC with the branch target address,
which is usually obtained by adding an offset X given in the branch instruction.

The offset X is usually the difference between the branch target address and the
address immediately following the branch instruction.

Example : If the branch instruction is location is at 2000 and branch target

address is 2050 , the offset value must be 46 .
( This is because the PC is incremented during the fetch phase before knowing the
type of instruction being executed and pointing to the instruction following the
branch instruction )

Branch Instruction : X(PC) ….. 46(PC)

119
MDRi
nE,

Selecty,

120
 Multiple-Bus Organization
Using a single bus structure only one data item can be transferred over
the bus in a clock cycle . To reduce the number of step needed , most
commercial processors provide multiple internal paths that enable
several transfers to take place in parallel .

General purpose registers are combined into a single block called

register file ( implemented in the form of an array of memory cells )
Buses A and B are used to transfer the source operands to the A and B
inputs of the ALU ,and the result of ALU operation is transferred to the
destination over bus C .

ALU control signal for such operation

121
R=A or R=B
 Namitha Ramachandran

122
Introduction of the incrementer unit ,which is used to increment the PC by 4 .
Using the incrementer eliminates the need to add 4 to the PC using the main ALU .
The source for the constant 4 at the ALU used to increment other memory addresses in
LoadMultiple and StoreMultiple instructions.