Differential Amplifiers

David Johns

University of Toronto
david.johns@utoronto.ca
Differential Signals
Many circuits make use of differential signals
− ethernet, SATA, PCIe, memory interfaces, ADCs, DACs, ...
Advantage of differential signalling
− Rejection of common-mode noise
− EMI (electromagnetic interference) reduction to other circuits

RS
v10 = v1 + (IN /2)RS
v1
RS
v20 = v2 + (IN /2)RS
v2
IN
(interference noise)

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Differential Signals
If the 2 signals are matched, the interference noise is the same on
each wire so ...
v20 − v10 = v20 − v1
Taking the difference between the 2 wires cancels
”common-mode” noise
In general, define
v2 = VCM + vid /2
v1 = VCM − vid /2
Differential signal
vid = v2 − v1
− Difference of 2 signals
Common-mode signal
VCM = (v2 + v1 )/2
− Average of 2 signals

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Differential Amplifiers
Differential inputs used in opamps
vi+ vi+ vo−
vo
vi− vi− vo+
Opamp Fully Diff Opamp

Opamp input stage: transistor differential pair

vi+ vi−
Diff Pair
IB

Look at large-signal and small-signal for MOS diff pair

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Diff Pair - Large Signal
VDD

RD RD

vD1 vD2

ID1 ID2

M1 M2
VG1 VG2
IB

−VSS

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Diff Pair - Large Signal

M1 , M2 are identical
iD1 + iD2 = IB
If VG1 = VG2
− iD1 = iD2 = IB /2
If VG1 > VG2
− iD1 > iD2
If VG1 < VG2
− iD1 < iD2
Can use diff pair to ”steer” the current, IB

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Diff Pair - Large Signal - Common-Mode Input
VDD

RD RD

vD1 vD2
IB IB
2 2

M1 VS M2
VCM

IB

−VSS

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Diff Pair - Large Signal - Common-Mode Input
Define VCS be the min voltage required across IB for it to operate
correctly (i.e. be in the active region)
If VS − VSS ≥ VCS then
− VD1 = VD2 = VDD − ( I2B )RD
If M1 /M2 both active
2
− ID1 = IB /2 = 0.5µn Cox (W /L)Vov
p
− Vov = IB /(µn Cox (W /L))
Maximum VCM
− Occurs when gate is Vt above drain voltage
− VCM,max = Vt + VDD − ( I2B )RD
Minimum VCM
− Occurs when VS is low enough that IB does not have min voltage
across it
− Occurs when VS = −VSS + VCS
− VCM,min = −VSS + VCS + Vt + Vov
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Diff Pair - Large Signal - Diff Input
VDD

RD RD
vD1 vD2
M1 M2
Vid vGS1 vGS2
VS

IB

−VSS

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Diff Pair - Large Signal - Diff Input
if vid  0
− All IB flows through M1
if vid  0
− All IB flows through M2
At what vid does M2 ”just” turn off
− If iD2 ≈ 0, VGS2 = Vtn so VS = −Vtn since VG2 = 0
0 0 0
− VGS1 = Vtn + Vov where Vov is overdrive voltage when ID = IB
− Vov is the overdrive voltage when ID = IB /2
0
p
− Vov = 2IB /(µn Cox (W /L))
0
√
− Vov = 2Vov
− vid = VS + vGS1
0
√
− vid,max = −Vtn + Vtn + Vov = 2Vov
− So ID2 = 0 for vid > vid,max
− Similarily, ID1 = 0 for vid < −vid,max

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Diff Pair - Large Signal - Diff Input

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Diff Pair - Large Signal - Diff Input

Can show r  2
iD1 = IB
2 + ( VIBov )( v2id ) 1 − vVidov/2
r   2
vid /2
iD2 = IB
2 − ( VIBov )( v2id ) 1 − Vov

For vid ≈ 0, id is roughly linear equation

More non-linear as vid increases

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Diff Pair - Small-Signal

VDD

RD vod RD

VG1 = VCM + vid /2 VG2 = VCM − vid /2

M1 M2
IB

−VSS

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Small-Signal - Balanced

RD vod RD

vG1 vG2
+vid /2 −vid /2
vs = 0V
M1 M2
IB

IF circuit is balanced
Diff input applied
− vG1 goes up while vG2 goes down the same amount
− Results in vs = 0V
Can do our analysis with half-circuit

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Small-Signal - Balanced

RD

−vod /2

M1

+vid /2

Above is half circuit

−vod /2 = −gm1 (ro1 ||RD )(vid /2)
vod /vid = gm1 (ro1 ||RD )
Recall that M1 /M2 are matched
− gm1 = gm2 and ro1 = ro2

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Example - Balanced
VDD VDD

RD vod RD
1kΩ RL 1kΩ

2kΩ
VCM + vid /2 RS RS VCM − vid /2

Assume
100Ω 100Ω Vov = 0.2V
IB 1mA λ=0

−VSS

gm = 2ID /Vov = 2(IB /2)/Vov = 5mA/V

ro → ∞
For half circuit, split RL into 2 1kΩ

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Example - Balanced

RD
−vod /2
RL /2
vid /2

RS

Ro = (RL /2)||RD = 500 Ω

−1 −1
Gm = (1/gm )+RS = 300 A/V
(−vod /2)/(vid /2) = Gm Ro = −1.67 V/V
vod /vid = 1.67 V/V

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Small-Signal - UnBalanced
VDD VDD

RD1 vod RD2

1kΩ 2kΩ
vo1 vo2
VCM + vid /2 M1 M2 VCM − vid /2
1X 3X Assume
IB 1mA Vov = 0.2V
λ=0
−VSS

3X implies M2 is 3 times W /L compared to 1X M1

ID2 = 3ID1 and ID1 + ID2 = 1mA
− ID2 = 0.75mA, ID1 = 0.25mA
− gm2 = 7.5mA/V and gm1 = 2.5mA/V
− ro → ∞

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Small-Signal - UnBalanced

isc1 isc2

vid /2 M1 M2 −vid /2

1X 3X

Use superposition
0 0
− Find isc1 and isc2 due to vid /2 while −vid /2 = 0
00 00
− Find isc1 and isc2 due to −vid /2 while vid /2 = 0
0 00 0 00
− isc1 = isc1 + isc1 isc2 = isc2 + isc2
− These 2 currents go into the 2 load resistors so ...
− vod = isc2 RD2 − isc1 RD1

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Small-Signal - UnBalanced
0 −vid /2 0
isc1 = 1/gm1 +1/gm2 = −isc2
00 = −(−vid /2) 00
isc2 1/gm1 +1/gm2 = −isc1
−vid
isc1 = 1/gm1 +1/gm2 = 1.875e − 3(−vid )
vid
isc2 = 1/gm1 +1/gm2 = 1.875e − 3(vid )
In general, with an unbalanced diff pair
−vid
− isc1 = −isc2 = 1/gm1 +1/gm2

vod = isc2 (2e3) − isc1 (1e3) = 5.625vid

vod /vid = 5.625 V/V
Note that this is a very unusual case as the voltage swing at vo2 is
twice that at vo1 and this is generally undesirable.

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Diff Pair - Current Source Loads
VDD

VB2 M3 M4 VB2
vod

VCM + vid /2 VCM − vid /2

M1 M2

IB

−VSS

vod /vid = gm1 (ro1 ||ro3 )

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Diff Pair - Current Source Loads
VDD
VB4 M7 M8 VB4

VB3 M5 M6 VB3
vod Rop

Ron
VB2 M3 M4 VB2
VCM + vid /2 M1 M2 VCM − vid /2

IB

−VSS

vod /vid ≈ gm1 (Rop ||Ron )

Ron ≈ (gm3 ro3 )ro1 Rop ≈ (gm5 ro5 )ro7
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Diff Amp - Various Gains

vi1 vo1

vi2 vo2

Fully Diff Amplifier

vi1 = VCMi + vid /2 vo1 = VCMo − vod /2

vi2 = VCMi − vid /2 vo2 = VCMo + vid /2
vid = vi1 − vi2 vod = vo2 − vo1
vi1 +vi2 vo1 +vo2
VCMi = 2 VCMo = 2

We can define 4 gains through the amplifier

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Diff Amp - Various Gains
Differential Gain
vod
Ad ≡ vid
− This is what we are MOST interested in
Common-mode-to-differential gain
vod
ACM ≡ vcmi
− Common-mode ”signals” may convert to differential signal
This would result in ”noise” in the differential signal
Common-mode-to-common-mode gain
vcmo
− Acm−cm ≡ vcmi
− Generally not too critical but we want it less than 1 so we do not
amplify common-mode signals
Differential-to-common-mode gain
vcmo
− Ad−cm ≡ vid
− Generally not an issue to worry about so generally not looked at

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Diff Amp - Various Gains

Most important are Ad and ACM

Want Ad  ACM
− So common-mode signals are rejected relative to diff signals
Define common-mode rejection ratio (CMRR)
|Ad |
CMRR ≡ |ACM |
or in dB form
CMRRdB ≡ 20log( |A|ACM
d|
|)

Want a high CMRR value

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Common-mode to Diff Gain - ACM
Circuit for finding ACM ≡ vod /vcmi
VDD

RD RD
vod
vo1 vo2
VCM + vcmi VCM + vcmi

IB RSS

−VSS
Half circuits

RD RD
vod
vo1 vo2
vcmi vcmi

2RSS 2RSS

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Common-mode to Diff Gain - ACM
Let λ → ∞
Recall Ad = vod /vid = gm RD
vo1 vo2 −RD
vcmi = vcmi = (1/gm )+2RSS

If perfectly matched
− vod = vo2 − vo1 = 0 ⇒ ACM = 0
Resistors mismatched by ∆RD
− We can still used the half circuit here since the lower half of the
circuit is still perfectly matched (only RD are mismatched)
− RD1 = RD RD2 = RD + ∆RD
−(RD +∆RD )
− vvcmi
o1
= (1/g− RD
m )+2RSS
vo2
vcmi = (1/gm )+2RSS
vo2 −vo1 −∆RD
− ACM = vcmi = (1/gm )+2RSS
  
gm RD ∆RD
− ACM = − 1+2gm RSS RD
(1+2gm RSS )
− CMRRR = (∆RD /RD )
− To increase CMRR, increase gm or RSS or reduce ∆RD 27/45
Common-mode to Diff Gain - ACM
Transistors gm mismatched by ∆gm
We can not use half circuits as the circuit is no longer balanced
gm1 = gm + ∆gm /2 gm2 = gm − ∆gm /2

id1 id2
RD RD
vod
vo1 vo2
vcmi vcmi
M1 M2
vs

RSS

RSS vcmi
vs = RSS +1/(2gm ) vcmi id1 + id2 = vs /RSS = RSS +1/(2gm )

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Common-mode to Diff Gain - ACM
id1 = gm1 vgs1 id2 = gm2 vgs2
Since vgs1 = vgs2 , we have
id1 gm1
id2 = gm2

Combining the above equations, we have

gm1 vcmi gm2 vcmi
id1 = 1+2gm RSS id2 = 1+2gm RSS
−gm2 )RD vcmi
vod = vo2 − vo1 = −id2 RD − (−id1 RD ) = (gm11+2g m RSS
  
∆gm RD gm RD ∆gm
ACM = vod /vcmi = 1+2g m RSS
= 1+2gm RSS gm

(1+2gm RSS )
CMRRgm = (∆gm /gm )

To increase CMRR, increase gm or RSS or reduce ∆gm

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Common-mode to common-mode Gain - ACM−CM

From our original half circuit, we found

vo1 vo2 −RD
vcmi = vcmi = (1/gm )+2RSS

This is also our common-mode to common-mode gain so

−RD
ACM−CM = (1/gm )+2RSS

To reduce our common-mode to common-mode gain, we can

increase RSS or decrease gm or RD
− Increasing RSS is a better choice as it helps with the CMRR
− Decreasing gm or RD also decreases our diff gain

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Input Offset of Amp with Diff Input
The input offset is the dc voltage value, Vos , that when applied to
the input of an amplifier will result in the output voltage being zero.
Vos input offset for Vo = 0
Vo,off is the output offset for vid = 0
If in the linear range of the amp
− Vos = Vo,off /Ad where Ad is the gain of the amp
VDD

RD RD
Vo,off

IB

−VSS

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Input Offset of Diff Pair

VDD

RD RD
0V

Vos

IB

−VSS

Offset due to mismatch for RD , (W /L), Vtn

Without showing the derivation, the input offset is ...

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Input Offset of Diff Pair

For ∆Vtn
− Usually ∆Vtn is the dominant cause for offset
− Vos = ∆Vtn
− Typical values for ∆Vtn from 1 → 10 mV
For ∆RD   
Vov ∆RD
− Vos = 2 RD

For ∆(W /L)

  
Vov ∆(W /L)
− Vos = 2 (W /L)

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Amplifiers (First Stage)
Diff-Diff Amplifier (fully differential)
VDD

vi1 vo1 VB2 M3 M4 VB2

vod
Vo1 Vo2
vi2 vo2
Vi1 M1 M2 Vi2

IB

−VSS
Diff-Single Ended Amplifier
VDD

vi1 M3 M4

vo Vo
vi2
Vi1 M1 M2 Vi2

IB

−VSS 34/45
Diff-Single Ended Amplifier (First Stage)

To find gain of first stage - find Gm and Ro

For Gm
M4
M3 id1
isc
id1
id1
vid /2 M1 −vid /2

M2

id1 = gm1 (vid /2)

isc = 2id1 = gm1 vid

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Diff-Single Ended Amplifier (First Stage)
For Ro
M4
M3
id4 ix

id2
id2 vx
M1 M2

id2

Due to the current mirror

id4 = vx /ro4 + id2
id2 = vx /Rd2

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Diff-Single Ended Amplifier (First Stage)

Impedance Rd2 = 2ro2 is found by ...

− Impedance of diode connected M3 is approx 1/gm3
− Rs1 ≈ (1/gm1 ) + (1/gm3 )/(gm1 ro1 ) ≈ 1/gm1
− Rd2 ≈ (1 + gm2 Rs2 )ro2 ≈ (1 + ggm2
m1
)ro2 ≈ 2ro2
ix = id4 + id2 = vx /ro4 + vx /(2ro2 ) + vx /(2ro2 )
ix = vx /ro4 + vx /ro2
Ro = vx /ix = ro2 ||ro4
So the gain is
vo /vid = gm1 (ro2 ||ro4 ) where vid = vi1 − vi2

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2 Stage CMOS Opamp
VDD VDD

M8 M5 M7

Iref −vid /2 M1 M2 vid /2 vo

RC CC
vo1
−VSS
M3 M4 M6

−VSS −VSS
RC and CC are used for stability when feedback is used
− For low freq gain, we assume CC is an open circuit
A1 = vo1 /vid = −gm1 (ro2 ||ro4 ) A2 = vo /vo1 = −gm6 (ro6 ||r07 )
Overall gain: vo /vid = A1 A2
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2 Stage CMOS Opamp
Random dc offset
− Random offset will result in approx 1 − 10 mV of input offset
Systematic dc offset
− Even if all transistors are matched, systematic offset may occur
depending on bias currents
− For ZERO systematic offset

(W /L)6 (W /L)7
=2 (1)
(W /L)3 (W /L)5

Proof:
− Let Vid = 0
− ID3 = ID4 = ID5 /2 and since VGS3 = VGS4 , then VDS4 = VDS3 = VGS6
− VGS6 = VGS3 means that ID6 is a current mirror of the current ID3

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2 Stage CMOS Opamp

− ID6 = (W /L)6 /(W /L)3 × (ID5 /2)

− For no systematic offset, ID7 = ID6
− ID7 = (W /L)7 /(W /L)5 × ID5
− Combining the above, we have
− ID7 = ID6
− (W /L)7 /(W /L)5 × ID5 = (W /L)6 /(W /L)3 × (ID5 /2)
− Dividing both sides by ID5 we have
− 2(W /L)7 /(W /L)5 = (W /L)6 /(W /L)3
For good current matching
− the lengths of M5 /M7 /M8 should be the same
− the lengths of M3 /M4 /M6 should be the same

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Diff Amp Example
VDD
µn Cox = 240µA/V2
Vtn = 0.3V
VB M3
VDD µp Cox = 60µA/V2
vo λ0 = 100nm/V
W1 = 2µm
vi M1 M2
W2 = 1µm
W3 = 2µm
All L = 200nm
IB
VB chosen so ID3 = ID2
50µA

Find vo /vi and Rout

− For isc , make the approximation that all ro → ∞

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Diff Amp Example

First we do dc analysis
− ID1 = 2ID2 ID1 + ID2 = IB = 50µA
− Combining, we have
− ID2 = IB /3 = 16.67µA ID1 = 2ID2 = 33.33µA
− ID3 = ID2 = 16.67µA
p
− gm1 = 2µn Cox (W1 /L)ID1 = 400µA/V
− ro1 = L/(λ0 ID1 ) = 60kΩ
p
− gm2 = 2µn Cox (W2 /L)ID2 = 200µA/V
− ro2 = L/(λ0 ID2 ) = 120kΩ
− ro3 = L/(λ0 ID3 ) = 120kΩ

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Diff Amp Example
For isc , we have the following circuit

M3
isc
id1

vi M1 M2

id1

− isc = id1 = Gm vi
1
− Gm = (1/gm1 )+(1/gm2 ) = 133.3µA/V

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Diff Amp Example
For Rout , we have the following circuit

M3

Rop

Ron Rout

vi M1 M2

Rs1

− Rs1 = ((1/gm1 )||ro1 ) = 2.4kΩ

− Ron = ro2 + (1 + gm2 ro2 )Rs1 = 180kΩ
− Rop = ro3 = 120kΩ
− Rout = Ron ||Rop = 72kΩ
− vo /vi = Gm Rout = 9.6V/V

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Topics Covered

Differential signals
Diff amps
Diff pair
− Large signal
− Small signal (balanced and unbalanced)
Diff pair current source loads
Diff amps - 4 gains through amp
Input offset
2 stage CMOS opamp

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