UNIT-4

Stacks and Subroutines

Stacks:

A stack is a LIFO data structure which is employed in the RAM area where Programmers uses the stack to

store temporary data and addresses and the microprocessors use the stack to execute subroutines.

The 8085 has a 16-bit register known as the Stack Pointer. The function of the stack pointer is to hold the

starting address of the stack. This address can be decided by the programmer.

The stack operates on the Last In, First Out (LIFO) principle. The location of the most recent data on the

stack is known as the TOP of the stack. The stack pointer always points to the top of the stack. Contents

can be stored in the stack using the

PUSH instruction and can restore the contents by using the instruction POP
.
MNEMONIC DESCRIPTION

LXI SP, 16-bit Load the stack pointer register with a 16-bit address.

PUSH Rp Copies the contents of the specified register pair on the stack

POP Rp Copies the contents of the top two memory locations of the stack into the specified register pai

PUSH and POP Operation in 8085

PUSH Rp

This is a 1-byte instruction. This instruction copies the contents of the specified register pair on the stack

as described below:

 The stack pointer is decremented and the contents of the higher-order register are copied to
the location shown by the stack pointer register.
 The stack pointer is again decremented and the contents of the low-order register are copied
to that location.
POP Rp

This is a 1-byte instruction. This instruction copies the contents of the top two memory locations of the

stack into the specified register pair.

  First, the contents of the memory location indicated by the stack pointer register are copied
into the low-order register and then the stack pointer register is incremented by 1.
 The contents of the next memory location are copied into the high-order register and the
stack pointer register is again incremented by 1.

Example

LXI SP,2099H
LXI H, 42F2H
PUSH H
Delay Counter
POP H
 The instruction
LXI SP, 2099H will initialize the stack pointer with the address of 2099H.
 LXI H, 42F2H will initialize or load HL register pair with 42F2H data so H = 42
and L = F2
.

 After the execution of PUSH H instruction the stack pointer is decreased by one to 2098H and
the contents of the H register are copied to memory location 2098H
.
 The stack pointer is again decreased by one to 2097H and the contents of the L register are
copied to memory location 2097H
.

Contents
of Stack and Registers After PUSH Operation
 After the execution of POP H instruction, the contents of the top of the stack location shown
by the stack pointer are copied in the L register and the stack pointer is increased by one
to 2098H
.
  The contents of the top of the stack are copied in the H register and the stack pointer is
increased by one.
 The contents of the memory locations 2097H and 2098H
are not destroyed until some other data bytes are stored in these locations.

Contents of Stack and Registers After POP Operation

Subroutines:

A subroutine is a set of instructions that will be used repeatedly in different locations of the program.
Instead of repeating the same instructions several times, they can be combined into a subroutine that is
called from various locations. A subroutine in Assembly language can exist anywhere in the code.
However, It is a common practice to separate subroutines from the main program.

Subroutine Call and Program Transfer

The 8085 microprocessor has two instructions to implement subroutines. The CALL instruction is used to
redirect program execution to a subroutine. The RET instruction is used to return the execution to the
calling routine. They are described in the following table.

MNEMONIC DESCRIPTION

3-byte instruction.
CALL 16-bit address
Jumps unconditionally to the memory location specified.

1-byte instruction.
RET
Unconditionally returns from the subroutine.

When the CALL instruction has been executed the contents of the program counter is saved to the top of
the stack. This return address is retrieved from the stack when the RET instruction is executed.
I/O Peripherals Interface (Interfacing output display)

• Figure 2 shows one of the way to decode address lines to obtain output address 01 H

. • The line address A 7 -A 0 is connected to eight NAND gates function as decoder.

• The line A 0 is connected directly, A 7 -A 1 are connected through inverter gates.

• The G 2 gate is combined with gate G 1 and IO/W control signal to generate select signal I/O whenever
both signals are active low.

Interface Input keyboard:

• The assembly instruction for that circuit in fig. 4 is IN FFH.

• Note: FFH = 1111 binary • The line address is decoded using NAND gates.

• When address A 7 -A 0 is active high (FFH), the output of NAND gate will have an active low signal and
then combined with control signals IOR at G 2.
• Suppose the μp run the IN FFH instruction, data at DIP switches will be placed at data bus and copied
to accumulator.

Input Interface Figure 4: IN FFH

Seven segment display output interface. Figure 6

Seven segment display output interface

• Fig 6 shows two different type of 7 -segment display; common cathode and common anode.

• 7 -segment display consists of a few LEDs and are arranged physically as shown in figure 7 a.

• It has seven segment from A to G that normally connected to data bus D 0 to D 6 respectively.

• If decimal point is used, D 7 will be connected to DP; and left unconnected if it is unused.
Seven segment display output interface. Figure 7

Seven segment display output interface.

• Fig. 7 shows the example to interface seven segment display and address decoder with an address of
FDH.

• The common anode display is used therefore 0 logic is needed to activate the segment. • Suppose to
display number 4 at seven segment display, therefore the segment F, G, B and C have to be activated

. • Follows are the instructions to execute it: –

MVI A, 66 H

OUT FDH

Data lines: D7 D6 D5 D4 D3 D2 D1 D0

Segments: NC G F E D C B A

Bits: X 1 1 0 0 1 1 0 = 66 H
 Interrupts in 8085
Interrupts are the signals generated by the external devices to request the microprocessor to perform a
task. There are 5 interrupt signals, i.e. TRAP, RST 7.5, RST 6.5, RST 5.5, and INTR.
Interrupt Service Routine (ISR)
A small program or a routine that when executed, services the corresponding interrupting source is
called an ISR.

Interrupt are classified into following groups based on their parameter −

 Vector interrupt − In this type of interrupt, the interrupt address is known to the
processor. For example: RST7.5, RST6.5, RST5.5, TRAP.

INTERRUPT VECTOR ADDRESS

TRAP (RST 4.5)

24 H

RST 5.5 2C H

RST 6.5 34 H

RST 7.5 3C H

 Non-Vector interrupt − In this type of interrupt, the interrupt address is not known to the
processor so, the interrupt address needs to be sent externally by the device to perform
interrupts. For example: INTR.
 Maskable interrupt − In this type of interrupt, we can disable the interrupt by writing some
instructions into the program. For example: RST7.5, RST6.5, RST5.5.
 Non-Maskable interrupt − In this type of interrupt, we cannot disable the interrupt by
writing some instructions into the program. For example: TRAP.
 Software interrupt − In this type of interrupt, the programmer has to add the instructions
into the program to execute the interrupt. There are 8 software interrupts in 8085, i.e.
RST0, RST1, RST2, RST3, RST4, RST5, RST6, and RST7.
 Hardware interrupt − There are 5 interrupt pins in 8085 used as hardware interrupts, i.e.
TRAP, RST7.5, RST6.5, RST5.5, INTA.
TRAP
It is a non-maskable interrupt, having the highest priority among all interrupts. By default, it is enabled
until it gets acknowledged. In case of failure, it executes as ISR and sends the data to backup memory.
This interrupt transfers the control to the location 0024H.
RST7.5
It is a maskable interrupt, having the second highest priority among all interrupts. When this interrupt is
executed, the processor saves the content of the PC register into the stack and branches to 003CH
address.
RST 6.5
It is a maskable interrupt, having the third highest priority among all interrupts. When this interrupt is
executed, the processor saves the content of the PC register into the stack and branches to 0034H
address.
RST 5.5
It is a maskable interrupt. When this interrupt is executed, the processor saves the content of the PC
register into the stack and branches to 002CH address.
INTR
It is a maskable interrupt, having the lowest priority among all interrupts. It can be disabled by resetting
the microprocessor.
When INTR signal goes high, the following events can occur −
 The microprocessor checks the status of INTR signal during the execution of each
instruction.
 When the INTR signal is high, then the microprocessor completes its current instruction
and sends active low interrupt acknowledge signal.
 When instructions are received, then the microprocessor saves the address of the next
instruction on stack and executes the received instruction.
Note − INTA is not an interrupt, it is used by the microprocessor for sending acknowledgement. TRAP has
the highest priority, then RST7.5 and so on.
Priority of Interrupts –

When microprocessor receives multiple interrupt requests simultaneously, it will execute the
interrupt service request (ISR) according to the priority of the interrupts.
 Programmable Interrupt Controller (8259)

Features of 8259 PIC microprocessor –

1. Intel 8259 is designed for Intel 8085 and Intel 8086 microprocessor.
2. It can be programmed either in level triggered or in edge triggered interrupt level.
3. We can mask individual bits of interrupt request register.
4. We can increase interrupt handling capability upto 64 interrupt level by cascading further
8259 PIC.
5. Clock cycle is not required.

Block Diagram of 8259 PIC microprocessor –

The Block Diagram consists of 8 blocks which are – Data Bus Buffer, Read/Write Logic, Cascade Buffer
Comparator, Control Logic, Priority Resolver and 3 registers- ISR, IRR, IMR.
1. Data bus buffer –
This Block is used as a mediator between 8259 and 8085/8086 microprocessor by acting as
a buffer. It takes the control word from the 8085 (let say) microprocessor and transfer it to
the control logic of 8259 microprocessor. Also, after selection of Interrupt by 8259
microprocessors, it transfers the opcode of the selected Interrupt and address of the
Interrupt service sub routine to the other connected microprocessor. The data bus buffer
consists of 8 bits represented as D0-D7 in the block diagram. Thus, shows that a maximum
of 8 bits data can be transferred at a time.
2. Read/Write logic –
This block works only when the value of pin CS is low (as this pin is active low). This block is
responsible for the flow of data depending upon the inputs of RD and WR. These two pins
are active low pins used for read and write operations.
3. Control logic –
It is the center of the microprocessor and controls the functioning of every block. It has pin
INTR which is connected with other microprocessor for taking interrupt request and pin INT
 for giving the output. If 8259 is enabled, and the other microprocessor Interrupt flag is high
then this causes the value of the output INT pin high and in this way 8259 responds to the
request made by another microprocessor.
4. Interrupt request register (IRR) –
It stores all the interrupt level which are requesting for Interrupt services.
5. In-service register (ISR) –
It stores the interrupt level which are currently being executed.
6. Interrupt mask register (IMR) –
It stores the interrupt level which have to be masked by storing the masking bits of the
interrupt level.
7. Priority resolver –
It examines all the three registers and set the priority of interrupts and according to the
priority of the interrupts, interrupt with highest priority is set in ISR register. Also, it reset
the interrupt level which is already been serviced in IRR.
8. Cascade buffer –
To increase the Interrupt handling capability, we can further cascade more number of pins
by using cascade buffer. So, during increment of interrupt capability, CSA lines are used to
control multiple interrupt structure.
SP/EN (Slave program/Enable buffer) pin is when set to high, works in master mode else in slave mode.
In Non-Buffered mode, SP/EN pin is used to specify whether 8259 work as master or slave and in
Buffered mode, SP/EN pin is used as an output to enable data bus.
DMA -DMA controller (8257)
DMA stands for Direct Memory Access. It is designed by Intel to transfer data at the fastest rate. It allows
the device to transfer the data directly to/from memory without any interference of the CPU.
Using a DMA controller, the device requests the CPU to hold its data, address and control bus, so the
device is free to transfer data directly to/from the memory. The DMA data transfer is initiated only after
receiving HLDA signal from the CPU.

How DMA Operations are Performed?

Following is the sequence of operations performed by a DMA −

 Initially, when any device has to send data between the device and the memory, the
device has to send DMA request (DRQ) to DMA controller.
 The DMA controller sends Hold request (HRQ) to the CPU and waits for the CPU to assert
the HLDA.
 Then the microprocessor tri-states all the data bus, address bus, and control bus. The CPU
leaves the control over bus and acknowledges the HOLD request through HLDA signal.
 Now the CPU is in HOLD state and the DMA controller has to manage the operations over
buses between the CPU, memory, and I/O devices.

Features of 8257

Here is a list of some of the prominent features of 8257 −

 It has four channels which can be used over four I/O devices.
 Each channel has 16-bit address and 14-bit counter.
 Each channel can transfer data up to 64kb.
 Each channel can be programmed independently.
 Each channel can perform read transfer, write transfer and verify transfer operations.
 It generates MARK signal to the peripheral device that 128 bytes have been transferred.
 It requires a single-phase clock.
 Its frequency ranges from 250Hz to 3MHz.
  It operates in 2 modes, i.e., Master mode and Slave mode.

INTERNAL ARCHITECTURE OF 8257:

The functional Block Diagram of DMA controller(8257) is shown in Figure 3.8.2 and the description are
as follows: It consists of five functional blocks:

a) Data bus buffer

b) Control logic

c) Read/write logic

d) Priority Resolver

e) DMA channels

Figure 3.8.2 Functional Block Diagram of 8257

Data Bus Buffer:

8- bit Tristate, bidirectional buffer interfaces the internal bus of 8257 with the
external system bus under the control of various control signals.

Read/Write Logic:

In the slave mode, the read/write logic accepts the I/O Read or I/O Write signals,
decodes the Ao-A3 lines and either writes the contents of the data bus to the addressed
internal register or reads the selected register depending upon whether IOW or IOR signal is
activated. In master mode, the read/write logic generates the IOR and IOW signals to control
the dataflow to or from the selected peripheral.

Control Logic:

The control logic controls the sequences of operations and generates the required control
signals like AEN, ADSTB, MEMR, MEMW, TC and MARK along with the address lines A4-A7, in
master mode.

Priority Resolver:

The priority resolver resolves the priority of the four DMA channels depending upon
whether normal priority or rotating priority is programmed.

Register Organization of 8257:

The 8257 performs DMA operation over four independent DMA channels with the following
Registers.

1. DMA Address Register

Each DMA channel has one DMA address register. The function of this register is to store the
address of the starting memory location, which will be accessed by the DMA channel. The
device that wants to transfer data over a DMA channel, will access the block of the memory
with the starting address stored in the DMA Address

Register.
2. Terminal Count Registers
Each of the four DMA channels of 8257 has one terminal count register (TC). This 16-bit
registers used for ascertaining that the data transfer through a DMA channel ceases or stops
 after the required number of DMA cycles.
After each DMA cycle, the terminal count register content will be decremented by
one and finally it becomes zero after the required number of DMA cycles are over. The bits
14 and 15 of this register indicate the type of the DMA operation (transfer).

3. Mode Set Register

The mode set register is used for programming the 8257 as per the requirements of the
system. The function of the mode set register is to enable the DMA channels individually and also
to set the various modes of operation as shown in Figure 3.8.3.

Figure 3.8.3 Mode Set Register

4. Status register
The lower order 4-bits of this register contain the terminal count status for the four individual
channels. If any of these bits is set, it indicates that the specific channel has reached the terminal
count condition. The update flag is not affected by the read operation. This flag can only be
cleared by resetting 8257. The update flag is set every time, the channel 2 registers are loaded
with contents of the channel 3 registers. It is cleared by the completion of the first DMA cycle of
the new block. This register can only read.