Design of two Stage operational Amplifier

Mohd Salman Gaurav Kumar

Faculty No.: 20ELB362, Enrollment No.: GL9658 Faculty No.: 20ELB430, Enrollment No.: GL9674
Department of Electronics Engineering Department of Electronics Engineering
ZHCET, Aligarh Muslim Univerity ZHCET, Aligarh Muslim Univerity
Aligarh, India Aligarh, India
gl9658@myamu.ac.in gl9674@myamu.ac.in
Name of Supervisor: Dr. Mohd Wajid

Abstract—Modern System on Chip (SOC) technology is pose additional hurdles. The primary objective of this
characterized by the seamless integration of digital and analog work is to design a two-stage Op-Amp with a
components, enabling the realization of complex
Common-Source amplifier configuration, leveraging
functionalities. Key analog components such as digital-to-
analog converters (DACs), analog-to-digital converters (ADCs), the benefits of 90nm technology. The Common-Source
filters, bias voltage generators, and switched-capacitor circuits amplifier is chosen for its demonstrated capability to
play a pivotal role in achieving the desired system provide high voltage gain and versatility in design
functionality. The design focus revolves around optimizing applications. The design process involves harnessing
various parameters such as power consumption, performance, the capabilities of the Cadence full custom design suite,
area utilization, and noise characteristics. One critical with careful consideration given to challenges such as
component in high-performance analog systems is the two-
stage operational amplifier (OPAMP). The OPAMP serves as short-channel effects, gain reduction, and the need for
the core element, influencing key performance parameters sophisticated gain-boosting techniques. The results and
essential for the overall system efficacy. The target discussion highlight the successful implementation of
performance parameters for an OPAMP encompass power the two-stage Op-Amp, showcasing improved gain
consumption, gain, phase margin, common-mode rejection characteristics when compared to a single-stage Op-
ratio (CMRR), offset voltage, signal-to-quantization noise ratio Amp. The integration of 90nm technology allows for
(SQNR), slew rate, gain-bandwidth product (GBW), and more.
miniaturization and compatibility with modern SOC
systems. Challenges such as parasitic coupling, the
absence of large-sized capacitors, and package
Keywords – Op-Amp,
parasitics are addressed in the design process to ensure
the robust performance of the Op-Amp in real-world
applications. In conclusion, the successful design of the
I. INTRODUCTION two-stage Op-Amp with the Common-Source amplifier
using 90nm technology underscores the potential for
In the realm of analog and mixed-signal systems, enhancing gain in analog circuits. The utilization of the
Operational Amplifiers (Op-Amps) stand as Cadence full custom design suite proves instrumental in
indispensable components, serving diverse functions overcoming the intricate challenges associated with
from basic dc bias applications to high-speed advanced process nodes. This work contributes to the
amplification and filtering. However, as technology ongoing advancements in analog circuit design,
advances and transistor lengths shrink to mere tens of particularly in the context of modern SOC applications.
nanometres, the design of analog circuits, particularly
Op-Amps, encounters formidable challenges. Unlike
their digital counterparts, analog circuits often
necessitate significant redesign to meet evolving
constraints. This work addresses these challenges by
focusing on the design of a two-stage Op-Amp that
incorporates a Common-Source (CS) amplifier
configuration, chosen for its ability to enhance gain.
The design is executed using 90nm technology and the
Cadence full custom design suite, a powerful Figure 1 : Block diagram of two stage Opamp
combination for meeting the demands of modern
System on Chip (SOC) applications.
The challenges in Op-Amp design are multifaceted,
with issues such as reduced open-loop gain in MOS II. BASIC OP-AMP THEORY
technology, stemming from factors like small
transconductance and short-channel effects in
submicron processes. To counteract these challenges, The Op Amp (Operational Amplifier) is a high gain, dc
gain-boosting schemes are employed, often requiring coupled amplifier designed to be used with negative
intricate circuit structures and higher power supply feedback to precisely define a closed loop transfer
voltages. While the use of multiple-stage amplifiers can function. The gain produced by the op amp is higher
elevate gain, their construction and design complexity than the gain produced by normal amplifiers. Thus, it
is a high gain amplifier. The basic symbol of Op-Amp amplifier of Figure 3 is used to improve the gain
is shown in Figure 2. The op amp symbol has two performance parameter of op-amp. CL is used as load
input terminals, one is positive terminal and other is capacitor for overall circuit
negative terminal, voltage supplies to op amp as
+VDD, –VSS and one output terminal.
A.

Figure 2: Symbol of Op-amp

Figure 4 : Two stage operational Amplifier

IV. CIRCUIT WORKING PRINCIPLE

Figure 3 : Block diagram of op-amp

Two MOSFETs M1 and M2 are in saturation region

and are assigned to receive differential inputs. The M3
and M4 also operate in saturation region and work as a
The op-amps can be designed by using either two stage current mirror. The bias voltage is applied to the gate
topology or folded cascade topology by modifying the of M5 MOSFET, which provides the tail current. A
stage 1. stage-2 or at any portion of the basic op-amp basic op-amp may become unstable at higher
topology. The selection of the topology is based on the frequency. This issue can be resolved by applying
required nonfunctional parameters and features of op- different compensation techniques with the aid of
amp. capacitors. and sometimes both resistors and capacitors
between different stages of the op-amp . There are
many compensation topologies, such as miller
III. DESIGN OF OP-AMP capacitor compensation, self-compensating and so on

The design of two stage op-amp can be done by using Differential Input Stage:
the following steps. Step-1: Selection of the transistor
logic style or logic family. This stage consists of four MOSFETs M1, M2, M3
Step-2: Basic structure for the op-amp from the and M4. The gates of MOSFETs M1 and M2 are
selected Logic family. inverting and non-inverting terminals respectively.
Step-3: Selection of transistor in 90nm technology. According to the gain of the first stage (differential
Step-4: Physical verification stage) the differential input signal will be amplified.
The input is a differential one for the current source, The gain of the stage depends on the transconductance
Transistors M5 and M7 are biasing transistors that of M2 times the total output resistance measured at the
ensure the circuit to operate always in saturation drain of M2. Because of three distinct advantages the
region. The Vout (max) and the gain can be increased current mirror (CM) load has been applied here. First
by adding extra parallel transistors to M6 transistors. of all, output resistance of CM load is high. Secondly,
The design of single stage op-amp and cs amplifier is the process of differential input to single-ended output
used to improve the gain performance parameter of op- conversion can be performed by using CM topology
amp. The M1, M2, M3 and M4 transistors provides the and finally, it also helps to improve CMRR. The CM
differential input pair circuitry and the capacitor Cc is load consists of M3 and M4
used as first stage load capacitor. The parallel
combination of M6, M7 …Mn transistors of cs Second Stage (Output):

2
The actual goal of this stage is not only to improve
additional gain but also output voltage swing of the
amplifier. The second stage, a common-source (CS)
configuration, which consists of transistor M6 and M7,
receives the output from the drain node of M2. The
output of the first stage is amplified by M6 and M7.
Again, similar to the first stage an active transistor M7
behaves like a load for M6 transistor. The gain of this
stage can be calculated as the Gm (transconductance)
of M6 multiplied by the output resistances of M6 and
M7 MOSFETs.

IV. PARAMETERS

Dc voltage 1.8V
Idc 25uA
Small signal voltage .05mV
M1 W=15um, L=1um Figure 6: Test Bech of op amp
M2 W=15um, L=1um
M3 W=10um, L=1um VI. RESULT
M4 W=10um, L=1um
M5 W=23um, L=140nm Transient analysis in analog circuits is a crucial aspect
M6 W=17.5um, L=250um of circuit design and analysis. It involves studying the
M7 W=10.5um, L=1um circuit's behavior over time, particularly during the
M8 W=10.5um, L=1um transition from one steady state to another

V.CADENCE CIRCUIT

Figure 7: Transient analysis

DC analysis is an essential step in the design and

analysis of electronic circuits, especially analog
circuits. DC analysis focuses on the steady-state or
quiescent (non-changing) behavior of a circuit when
all time-varying signals have stabilized. Here are
Figure 5: schematic several reasons why DC analysis is crucial in
electronic circuit design
1. Biasing of Active Component
2. Operating Point Determination

3
 essential, such as in communication systems and
audio processing

Figure 8 : DC analysis

AC analysis provides insights into how a circuit

responds to different frequencies within the AC signal.
The response can vary depending on the circuit Figure 10 : Gain and Phase Analysis
elements and their characteristics. Understanding the
frequency response is essential for designing circuits
that perform well across a range of frequencies VII. LAYOUT

In integrated circuit (IC) design, layout refers to the

meticulous arrangement of transistors,
interconnections, and other components on a
semiconductor wafer, translating the logical design of
a circuit into a physical configuration. The placement
of transistors is a critical consideration, influencing the
flow of signals through the circuit and ultimately
determining its performance. Interconnection routing
involves establishing paths between transistors,
utilizing metal or polysilicon lines to connect various
elements of the circuit. Adherence to specific physical
design rules is paramount, encompassing minimum
feature sizes, spacing requirements, and other
Figure 9: AC Response guidelines essential for manufacturability and yield.
Cell design, where functional blocks are repeated,
Gain and phase analysis is a fundamental aspect of necessitates careful boundary definition and
understanding the behavior of electronic circuits, arrangement to optimize space and mitigate signal
particularly in the context of alternating current (AC) interference. Power distribution planning ensures all
signals. Gain refers to the amplification or attenuation components receive requisite power, while
of the amplitude of an AC signal as it passes through a considerations for signal integrity address issues like
circuit. It is a measure of how much the output voltage crosstalk and electromagnetic interference. Layout
or current is increased or reduced relative to the input. design is intricately tied to the specific manufacturing
Gain analysis is crucial in the design of amplifiers process, requiring optimization for steps such as
In this design we obtain 65dB gain which is use for lithography and etching in a manner aligned with
high power application. design for manufacturability (DFM) principles. Clock
Phase analysis, on the other hand, focuses on the distribution, symmetry, alignment, and careful
timing relationship between the input and output extraction processes further contribute to achieving a
signals in a circuit. AC signals can introduce phase layout that meets functional requirements, adheres to
shifts, altering the alignment of peaks and troughs. design constraints, and is ready for fabrication into a
Phase analysis is critical in applications where fully functional integrated circuit. This complex and
maintaining the temporal coherence of signals is interdisciplinary process is typically facilitated by
computer-aided design (CAD) tools and necessitates

4
collaboration among design engineers, layout desired performance characteristics. Key parameters
designers, and manufacturing teams to ensure the such as gain, slew rate, and gain-bandwidth have been
creation of a successful final product fine-tuned through a judicious trade-off of various
circuit parameters, including tail current, transistor
aspect ratios (W/L), transconductance (gm), and
compensation capacitor values. Prior to parameter
tuning, the aspect ratios of the MOSFETs were
calculated meticulously using relevant formulas. In the
conclusive analysis, the circuit demonstrates an
impressive gain of 65 dB with a bandwidth extending
up to 10khz. While other performance parameters also
meet satisfactory levels, it is acknowledged that,
depending on specific application requirements, users
may need to carefully balance and trade-off circuit
parameters to further tailor the design to their unique
needs. This indicates a flexible and adaptable design
approach that allows for customization based on
specific application constraints and preferences.

IX. ACKNOWLEDGEMENT

This report marks the completion of the assignment

Figure 11:Layout carried out during the Digital IC Design course within
the Electronics Engineering Department at Aligarh
Muslim University.
We extend our gratitude to the Ministry of Electronics
and Information Technology, Government of India for
providing the Cadence Virtuoso Tool under the Chip to
Startup (C2S) program for the project titled
“Development of Silicon Proven I.P. Cores
Transceiver IC and System prototype for mm wave
Radar sensing in Healthcare and Security
Applications”.

X. REFERENCES

[1] H. C. Chow and J. Y. Wang, “High CMRR

instrumentation amplifier for biomedical applications,”
Proc. 9th International Symposium on Signal Processing and
Its Applications (ISSPA), Feb. 2007.
[2] R. J. Baker, “CMOS Circuit Design, Layout, and
Simulation,” 2nd ed., Wiley-IEEE Press, 2004.
[3] Sunil M.P and Hari Krishna Murthy, “Design and
Implementation of 90dB-4mW Two Stage CMOS
Operational Amplifier Using 180nm” 3rd International
Conference on Electronics and Communication Systems
(ICECS-2016) 25-26th, February 2016, Coimbatore, Tamil
Figure 12: layout Created by gds file Nadu, India

VIII. CONCLUSION

The simulations conducted in Cadence using a 90nm

CMOS process have yielded a highly optimized analog
circuit with carefully controlled parameters to achieve

5
6