Unit -2

ARM 7 BASED MICROCONTROLLER

 LPC 2148 Microcontroller
➢Based on a 32/16 bit ARM7TDMI-S CPU with real-time emulation .
➢High speed flash memory ranging from 32 kB to 512 kB.
➢A 128-bit wide memory interface and a unique accelerator
architecture enable 32-bit code execution at the maximum clock rate.
➢ For critical code size applications, the alternative 16-bit Thumb mode
reduces code by more than 30 % with minimal performance penalty.
➢Due to their tiny size and low power consumption, LPC2141/2/4/6/8
are ideal for applications where miniaturization is a key requirement,
such as access control and point-of-sale.
 LPC 2148…

➢A blend of serial communications interfaces ranging from a USB 2.0

Full Speed device, multiple UARTs, SPI, SSP to I Cs,
2

➢On-chip SRAM of 8 kB up to 40 kB,

➢Various 32-bit timers, single or dual 10-bit ADC(s), 10-bit DAC, PWM
channels and 45 fast GPIO lines with up to nine edge or level
sensitive
➢External interrupt pins make these microcontrollers particularly
suitable for industrial control and medical systems.
 Features of LPC2148
Low Profile Quad Flat Package
➢16/32-bit ARM7TDMI-S microcontroller in a tiny LQFP64 package.
➢32 to 512 kB of on-chip flash program memory. 128 bit wide interface/accelerator
enables high speed 60 MHz operation.
➢ In-System/In-Application Programming (ISP/IAP) via on-chip boot-loader
software.
➢Single flash sector or full chip erase in 400 ms and programming of 256 bytes in 1
ms.
➢ EmbeddedICE RT and Embedded Trace interfaces offer real-time debugging with
the on-chip Real Monitor software and high speed tracing of instruction
execution.
➢ USB 2.0 Full Speed compliant Device Controller with 2 kB of endpoint RAM.
 Features of LPC2148
➢ Single 10-bit D/A converter provides variable analog output.
➢ Two 32-bit timers/external event counters (with four capture and four compare channels each), PWM unit
(six outputs) and watchdog.
➢ Low power real-time clock with independent power and dedicated 32 kHz clock input.
➢ Multiple serial interfaces including two UARTs (16C550), two Fast I2C-bus (400 kbit/s), SPI and SSP with
buffering and variable data length capabilities.
➢ Vectored interrupt controller with configurable priorities and vector addresses.
➢ Up to 45 of 5 V tolerant fast general purpose I/O pins in a tiny LQFP64 package.
➢ Up to nine edge or level sensitive external interrupt pins available.
 Features of LPC2148
➢ 60 MHz maximum CPU clock available from programmable on-chip PLL with settling
time of 100 μs.
➢ On-chip integrated oscillator operates with an external crystal in range from 1 MHz to
➢ 30 MHz and with an external oscillator up to 50 MHz.
➢ Power saving modes include Idle and Power-down.
➢ Individual enable/disable of peripheral functions as well as peripheral clock scaling for
additional power optimization.
➢ Processor wake-up from Power-down mode via external interrupt, USB, Brown-Out
Detect (BOD) or Real-Time Clock (RTC).
➢ Single power supply chip with Power-On Reset (POR) and BOD circuits:
➢ CPU operating voltage range of 3.0 V to 3.6 V (3.3 V ± 10 %) with 5 V tolerant I/O
pads.
ARM7 TDMI-S

NXP LPC2148
LPC2148 development board
 Bus Structure
In LPC2148 three types of buses are used to
connect the core with other peripherals on chip.

1. Local Bus to connect the on chip memory

controllers and fast GPIO’s
2. AMBA Advance High Performance Bus (AHB)
for interrupt controller
• AHB (Advanced High Performance BUS)
-High performance
-Support pipelined
- Each AHB peripheral is allocated a 16 KB
address space within the AHB address space.
3. the ARM Peripheral Bus for connection to on-
chip peripheral functions.
 System Control Block
The System Control Block includes several system features and control registers for a
number of functions that are not related to specific peripheral devices.
These include:
➢Crystal Oscillator: On-chip integrated oscillator operates with external crystal in range
of 1 MHz to 25 MHz.
➢ External Interrupt Inputs
➢ Memory Mapping Control
➢ PLL
➢ Power Control
➢ Reset
➢ VPB Divider
PLL – Phase Locked Loop
➢ There two registers are protected in order to prevent accidental alteration of PLL
parameters or deactivation of the PLL.

The PLL is enabled by software only. The program must configure and activate the PLL,
wait for the PLL to Lock, then connect to the PLL as a clock source.
PLL Registers
 PLLCON
• The PLLCON register contains the bits that enable and connect the PLL.
• Enabling the PLL allows it to attempt to lock to the current settings of the
multiplier and divider values.
• Connecting the PLL causes the processor and all chip functions to run from
the PLL output clock.
• Changes to the PLLCON register do not take effect until a correct PLL feed
sequence has been given
• The PLL must be set up, enabled, and Lock established before it may be
used as a clock source.
• When switching from the oscillator clock to the PLL output or vice versa,
internal circuitry synchronizes the operation in order to ensure that glitches
are not generated.
 PLLCFG
• The PLLCFG register contains the PLL multiplier and divider values.
• Changes to the PLLCFG register do not take effect until a correct PLL
feed sequence has been given.
 PLLSTAT
• The read-only
PLLSTAT register
provides the actual
PLL parameters that
are in effect at the
time it is read, as
well as the PLL
status.
 PLLFEED
• A correct feed sequence must be written to the PLLFEED register in order
for changes to the PLLCON and PLLCFG registers to take effect.
• The feed sequence is:
– 1. Write the value 0xAA to PLLFEED.
– 2. Write the value 0x55 to PLLFEED.
• The two writes must be in the correct sequence, and must be consecutive
APB bus cycles.
• The latter requirement implies that interrupts must be disabled for the
duration of the PLL feed operation.
• If either of the feed values is incorrect, or one of the previously mentioned
conditions is not met, any changes to the PLLCON or PLLCFG register will
not become effective.
 VPB Divider(VLSI Peripheral Bus Divider)
• The VPB Divider determines the relationship between the
processor clock (CCLK) and the clock used by peripheral
devices (PCLK).
• The VPB Divider serves two purposes.
– The first is to provides peripherals with desired PCLK via APB bus so
that they can operate at the speed chosen for the ARM processor.
The
– second purpose of the VPB Divider is to allow power savings when an
application does not require any peripherals to run at the full
processor rate.
Now , PLL output clock is given by the
formula: => Frequency from the crystal
FOSC
CCLK = M x FOSC or oscillator(XTAL)/external clock
CCLK = FCCO / (2 x P)
=> Frequency Of The PLL Current
FCCO
CCO output clock is given by: Controlled Oscillator(CCO)
FCCO = CCLK x 2 x P or => PLL output frequency (CPU
CCLK
FCCO = FOSC x M x 2 x P Clock)
• The PLL inputs and settings must meet the following: => PLL Multiplier value from the
M MSEL bits in the PLLCFG
• FOSC is in the range of 10 MHz to 25 MHz.
register
• CCLK is in the range of 10 MHz to Fmax (the
=> PLL Divider value from the PSEL
maximum allowed frequency for the microcontroller P
– determined by the system microcontroller is bits in the PLLCFG register
embedded in).
=> Peripheral Clock which is
• FCCO is in the range of 156 MHz to 320 MHz.
PCLK
derived from CCLK
The Order of setting up PLLs is strictly as follows :

1. Setup PLL
2. Apply Feed Sequence
3. Wait for PLL to lock and then Connect PLL
4. Apply Feed Sequence
Baud rate using UART0
Memory Map
• To access any peripheral
we need its address.
The entire address
space can be divided in
to several sections.
 Memory Access Module
The MAM block in the LPC2148 maximizes the
performance of the ARM processor when it is running
code in Flash memory,
Two general methods for achieving code execution
performance.
Using RAM for code execution.
Using Cache memory.
 Pin Connect Block

• The purpose of the Pin Connect Block is to configure the

microcontroller pins to the desired functions. The pin connect
block allows selected pins of the microcontroller to have more
than one function. Configuration registers control the
multiplexers to allow connection between the pin and the on
chip peripherals.
The Pin Control Module contains registers as
shown below:
PINSEL
PINSEL
Bootloader
A small piece of software executed after every reset. This software is used to
load the new user program in to the flash memory using any communication
channel like UART, USB, Ethernet or CAN.

For LPC2000 Series the Bootloader can be activated by maintaining low level on
P0.14 while reset.
Bootloader

ISP
Philips microcontroller have a great feature called ISP
(In System Programming).
It enables the user to flash the microcontroller with an ease. In
LPC2148 the ISP mode can be activated by maintaining low level on
P0.14 while reset.
TIMERS

• Two 32-bit-timer Blocks.

– Each Timer block can be used as a
‘Timer’ (like for e.g. triggering an
interrupt every ‘t’ microseconds)
– or as a ‘Counter’ and can be also
used to demodulate PWM signals
given as input.

• A Timer Has A
– Timer Counter(TC) and
– Prescale Register(PR) associated
with it.
Timers
When Timer is Reset and Enabled TC is set to 0
and incremented by 1 every ‘PR+1’ clock cycles.
When it reaches its maximum value it gets reset to
0 and hence restarts counting.

Prescale Register is used to define the resolution

of the timer.

If PR=0 then TC is incremented every 1 clock

cycle of the peripheral clock.

If PR=1 then TC is incremented every 2 clock

cycles of peripheral clock and so on. By setting
an appropriate value in PR we can make timer
increment or count : every peripheral clock cycle
or 1 microsecond or 1 millisecond or 1 second
and so on.

Each Timer has four 32-bit Match Registers and

four 32-bit Capture Registers.
TCR – Timer Control Register
The Timer Control Register (TCR) is used to control the operation of the Timer/Counter
Count Control Register (CTCR)

• The Count Control Register

(CTCR) is used to select
between Timer and Counter
mode

• In Counter mode to select the

pin and edge(s) for counting.
Timer Counter (TC)
• The 32-bit Timer Counter is
incremented when the Prescale
Counter reaches its terminal count.

• Unless it is reset before reaching its

upper limit, the TC will count up
through the value 0xFFFF FFFF and
then wrap back to the value 0x0000
0000.

• This event does not cause an interrupt,

but a Match register can be used to
detect an overflow if needed.
 Prescale Register
(PR, TIMER0: T0PR - and TIMER1: T1PR )

• The 32-bit Prescale

Register specifies the
maximum value for the
Prescale Counter.
Prescale Counter Register
(PC, TIMER0: T0PC and TIMER1: T1PC )

• The 32-bit Prescale Counter controls division of

PCLK by some constant value before it is
applied to the Timer Counter.

• This allows control of the relationship of the

resolution of the timer versus the maximum
time before the timer overflows.

• The Prescale Counter is incremented on every

PCLK. When it reaches the value stored in the
Prescale Register, the Timer Counter is
incremented and the Prescale Counter is reset
on the next PCLK.

• This causes the TC to increment on every PCLK

when PR = 0, every 2 PCLKs when PR = 1, etc.
Match Registers (MR0 - MR3)
• The Match register values are
continuously compared to the Timer
Counter value.

• When the two values are equal, actions

can be triggered automatically.

• The action possibilities are to generate an

interrupt, reset the Timer Counter, or
stop the timer.

• Actions are controlled by the settings in

the MCR register
 Match Control Register
(MCR, TIMER0: T0MCR and TIMER1: T1MCR )

• The Match Control Register is

used to control what operations
are performed when one of the
Match Registers matches the
Timer Counter.

• (Refer data sheet)

Capture Registers (CR0 - CR3)
• Each Capture register is associated
with a device pin and may be loaded
with the Timer Counter value when
a specified event occurs on that pin.

• The settings in the Capture Control

Register determine whether the
capture function is enabled, and
whether a capture event happens
on the rising edge of the associated
pin, the falling edge, or on both
edges
Capture Control Register
(CCR, TIMER0: T0CCR and TIMER1: T1CCR )

• The Capture Control Register is

used to control whether one of
the four Capture Registers is
loaded with the value in the
Timer Counter when the capture
event occurs, and whether an
interrupt is generated by the
capture event.

• Refer data sheet

 Interrupt Register
(IR, TIMER0: T0IR - and TIMER1: T1IR)

• The Interrupt Register consists of four

bits for the match interrupts and four
bits for the capture interrupts.
• If an interrupt is generated then the
corresponding bit in the IR will be high.
Otherwise, the bit will be low.
• Writing a logic one to the
corresponding IR bit will reset the
interrupt. Writing a zero has no effect.
Interfacing with LED, LCD, GLCD, KEYPAD
 LED blinking using Timer
#include <lpc214x.h>
#define PRESCALE 60000 //60000 PCLK clock cycles to increment TC by 1
void delayMS(unsigned int milliseconds);
void initTimer0(void);
int main(void)
{
initClocks(); //Initialize CPU and Peripheral Clocks @ 60Mhz
initTimer0(); //Initialize Timer0
IO0DIR = 0xFFFFFFFF; //Configure all pins on Port 0 as Output
while(1)
{
IO0SET = 0xFFFFFFFF; //Turn on LEDs
delayMS(500); //0.5 Second(s) Delay
IO0CLR = 0xFFFFFFFF; //Turn them off
delayMS(500);
}
}
void initTimer0(void)
{
/*Assuming that PLL0 has been setup with CCLK = 60Mhz and
PCLK also = 60Mhz.*/
T0CTCR = 0x0;
T0PR = PRESCALE-1; //(Value in Decimal!) - Increment T0TC at
// every 60000 clock cycles
//Count begins from zero hence subtracting 1
//60000 clock cycles @60Mhz = 1 mS
T0TCR = 0x02; //Reset Timer
}
void delayMS (unsigned int milliseconds)
{
T0TCR = 0x02; //Reset Timer
T0TCR = 0x01; //Enable timer
while(T0TC < milliseconds); //wait until timer counter
reaches the desired delay
T0TCR = 0x00; //Disable timer
}
 KEYPAD INTERFACING

• A keypad is a set of buttons arranged in a block or "pad" which

usually bear digits, symbols and usually a complete set of
alphabetical letters. If it mostly contains numbers then it can
also be called a numeric keypad. Here we are using 4 X 4
matrix keypad.
Interfacing Keypad
Figure shows how to interface the
4 X 4 matrix keypad to two ports in
microcontroller.
The rows are connected to an
output port and
the columns are connected to an
input port.
To detect a pressed key, the microcontroller
grounds all rows by providing 0 to the output latch,
and then it reads the columns. If the data read
from the columns is D3-D0=1111, no key has been
pressed and the process continues until a key press
is detected. However, if one of the column bits has
a zero, this means that a key press has occurred.
For example, if D3-D0=1101, this means that a key
in the D1 column has been pressed.

After a key press is detected, the microcontroller

will go through the process of identifying the key.
Starting with the top row, the microcontroller
grounds it by providing a low to row D0 only; then
it reads the columns.

If the data read is all 1s, no key in that row is

activated and the process is moved to the next
row. It grounds the next row, reads the columns,
and checks for any zero. This process continues
until the row is identified. After identification of
the row in which the key has been pressed, the
next task is to find out which column the pressed
key belongs to.
 Questions
1. Enlist the features of LPC2148.
2. Draw and Explain Memory Map of LPC2148.
3. Write embedded C program to blink LED connected to
LPC2148.
4. Interface 16 x 2 LCD display to LPC2148 in 4-bit mode. Write
embedded C program.
5. Write a short note on System Control block of LPC2148.
6. Draw and explain the block diagram of LPC 2148.
7. Write and explain the code for 4x4 keyboard matrix interfacing with
LPC 2148.
8. State different on chip peripherals of LPC2148 and describe their
significance.
9. State the Features of Timers of LPC2148.
10. Explain various registers of GPIO.
11. Explain the PLL block from System Control Function of LPC2148.
12. Explain the PLL programming of LPC2148.
13. Explain PLL registers use for PLL programming in LPC2148.
14. Explain Timer control Register (TCR) and Timer Counter (TC) register.
15. Draw and Explain interfacing diagram for GLCD with LCP2148
16.Explain the architecture of LPC2148 with a neat block
diagram.
17.State the features of LPC2148 micro controller in following
context
i) Flash memory and Static RAM
ii) Slow GPIO and Fast GPIO
iii) Timers and its modes
18. Explain the bus structure used in LPC2148.
19. Explain the significance of PLL0 and PLL1 in LPC2148.
20.Explain in brief the registers of PLL block.
21.Explain procedure to derive the settings of PLL.
21.Explain the relationship between Fosc, CCLK, Fcco w.r.t. PLL0.
Show the PLL frequency .Calculations to achieve CCLK =
60Mhz. assume suitable data.
22. Explain the significance of VPB/APB divider in LPC2148.
23.Explain with neat diagram relation between CCLK and PCLK
with the help of VPB/APB divider. Find the configuration of
VPB divider to achieve PCLK = 30 Mhz for Fosc = 12Mhz.
24.Draw and Explain the System Memory Map of LPC2148.
25. What is the need of Pin Connect Block in LPC2148? Explain
the role of PINSELx registers.
26. Explain the GPIO Ports available and registers to control the
same.
27.Differentiate the writing to IOSET/IOCLR vs. IOPIN.
28.Enlist the features and applications of Timer in LPC2148.
29. Explain the working of Timer w.r.t. generation of delay. (Refer
Block diagram of timer to write description)
30.Explain in brief the registers TCR, TC, CTCR, PC, and PR.
31.Explain the steps to generate the delay of 500ms using timer
when PCLK = 15Mhz.
32.What is need of prescaler? Explain the working of timer
prescaler in LPC2148?
33. Draw interfacing diagram to interface LED bank in common
anode / common cathode mode to port pins P0.18 - P0.21 of
LPC 2148. State algorithm and the SFRs involved with their
34.Draw interfacing of LEDs to P0.16 - P0.23 of LPC 2148 and
Pulled up Switches to P1.16 - P1.17 of LPC 2148. Explain the
algorithm to chase the LEDs right to left and vice-versa
whenever respective switch is pressed.
35.Draw the interfacing diagram between LPC2148 and LCD16x2
display. State algorithm, SFRs