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Cache Worksheet

The document discusses various cache policies, including write-through and write-back, and presents a 2-way set associative cache structure. It poses questions regarding cache size, memory size, and specific memory addresses, as well as calculating Average Memory Access Time (AMAT) and cycles for memory transfers. Additionally, it provides parameters for instruction and data caches, and explores the details of a 3-way set associative cache system.

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2 views

Cache Worksheet

The document discusses various cache policies, including write-through and write-back, and presents a 2-way set associative cache structure. It poses questions regarding cache size, memory size, and specific memory addresses, as well as calculating Average Memory Access Time (AMAT) and cycles for memory transfers. Additionally, it provides parameters for instruction and data caches, and explores the details of a 3-way set associative cache system.

Uploaded by

alieyadobeidat
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Cache Worksheet

1) In case of a cache write miss, the missed item is written to memory


only. This refers to what policy?

2) In case of a cache hit, the data is written to both the cache and
memory. This refers to what policy?

3) The following represents a 2-way set associative cache

Byte offset Byte offset


Inx Tag V 11 10 01 00 Tag V 11 10 01 00
000 1011 1 01 02 03 04 0001 1 81 82 83 84

001 1101 1 11 12 13 14 0011 1 91 92 93 94

010 0101 0 21 22 23 24 1011 1 A1 A2 A3 A4

011 1011 1 31 32 33 34 0101 0 B1 B2 B3 B4

100 1011 1 41 42 43 44 1101 1 C1 C2 C3 C4

101 0101 1 51 52 53 54 0111 0 E1 E2 E3 E4

110 0001 0 61 62 63 64 0011 0 F1 F2 F3 F4

111 1101 1 71 72 73 74 1111 1 05 06 07 08

1. What is the cache size in bytes?


2. What is the memory size in bytes?
3. The content of location 0x169 is ______________.
4. Show the changes made to the cache if the address 0x1ED is
referenced by a read operation. Assume M[0x1EC] = 0xA0B1C2D3.

4) Consider the following cache parameters:


 1st level Instruction cache: Hit time = 1 cycle, Hit ratio = 0.9
 1st level Data cache: Hit time = 1 cycle, Hit ratio = 0.85
 2nd level Unified cache:
o Hit time: 20 cycles (time to transfer a block from the 2nd
level cache to the 1st level cache)
o Global Hit ratio: 0.98
 Memory:
o Time to transfer a block from memory to the 2nd level cache
= 200 cycles
a) What is the AMAT (Average Memory Access Time) of a data
word?
b) What is the average CPI if 15% of the instructions are
memory reference instructions and the base CPI is 2.0?
5) Consider a computer system with the following parameters: a 32-bit
address, 3-way set associative cache with a total size of 3 MB, and a
block size of 128 bytes. Show the tag, block index, and word offset of
the address 0x32CC204C.

6) How many cycles are required to copy a 128-byte block from memory to cache in
each of the following memory systems if the memory delay is 8 cycles?
1. The memory-cache bus is 32 bits wide.
2. The memory-cache bus is 256 bits wide.
3. The memory-cache bus uses eight 32-bit banks.

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