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4 views9 pages

Sheet_5

Uploaded by

ahmed.bahaa55555
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Badr University in Assiut

2nd Year Students Academic Year 2024/2025


1st Semester Course: Computer Architecture
Sheet No. 5 Cache Memory

Questions:

1. Consider a machine has the following specifications: 1 MB main memory, 16 KB


cache, and each cache line contains 8 bytes. Show the memory address format in the
following cases:
a. Direct mapping
b. Associative mapping
c. 4-way set associative mapping

2. A set-associative cache consists of 64 lines, divided into four-line sets. Main


memory contains 4K blocks of 128 words each. Show the format of main memory
address.

3. A two-way set-associative 8 KB cache has lines of 16 bytes. The 64 MB main


memory is byte addressable. Show the main memory address format.

4. For the hexadecimal main memory address BBBBBB, show the following
information in hexadecimal format:
a. Tag, Line, and Word values for a direct-mapped cache, using the following
memory address format: Tag = 8 bits, Line = 14 bits, and Word =2 bits.
b. Tag and Word values for an associative cache, using the following memory
address format: Tag = 22 bits and Word =2 bits.
c. Tag, Set, and Word values for a two-way set-associative cache, using the
following memory address format: Tag = 9 bits, set = 13 bits, and
Word = 2 bits.

5. Consider a machine with a byte addressable main memory of 216 bytes and block
size of 8 bytes. Assume that a direct mapped cache consisting of 32 lines is used with
this machine.
a. How is the 16-bit memory address divided into tag, line number, and byte
number?
b. Into what line would bytes with each of the following addresses be stored?
0001 0001 0001 1011
1010 1010 1010 1010

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Badr University in Assiut
å School of Artificial Intelligence & Data Management

c. Suppose the byte with address 0001 1010 0001 1010 is stored in the cache.
What are the addresses of the other bytes stored along with it?
d. How many total bytes of memory can be stored in the cache?

6. Consider a memory system that uses a 32-bit address to address at the byte level,
plus a cache that uses a 64-byte line size.
a. Assume a direct mapped cache with a tag field of 20 bits. Show the memory
address format and determine the following parameters: number of
addressable units, number of blocks in main memory, and number of lines
in cache.
b. Assume an associative cache. Show the memory address format and
determine the following parameters: number of addressable units, number
of blocks in main memory, number of lines in cache, size of tag.
c. Assume a four-way set-associative cache with a tag field of 9 bits. Show the
address format and determine the following parameters: number of
addressable units, number of blocks in main memory, number of lines in set,
number of sets in cache, and number of lines in cache.

7. True or False [Write T for True and F for False]

a. True In the internal memory, data transfer is governed by data bus width.
b. False Using the associative access method in memory systems, access time
depends on current data location and previous location.
c. False Access time is the required time for the memory to be ready before
the next access.
d. False Based on the characteristics of memory, greater capacity requires
larger cost per bit.
e. True As one goes from top to down in the memory hierarchy, memory
capacity increases.
f. False Based on the memory hierarchy, cache provides the fastest way
to access data.
g. True Tag in the memory address is used to identify which block of main
memory is in each cache line.
h. False Using direct mapping technique, each block of main memory can be
mapped into one or more possible cache lines.
i. False Associative mapping can be considered the simplest technique and
doesn’t require expensive search.
j. True LFU algorithm means replacing the block in the set that has
experienced the fewest references.

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