0% found this document useful (0 votes)

10 views69 pages

PN7150

The PN7150 is a high-performance NFC controller with integrated firmware that supports all NFC Forum modes, designed for contactless communication at 13.56 MHz. It features a compact design, ultra-low power consumption, and is suitable for various applications including Android and Linux environments. The document provides detailed specifications, features, and ordering information for the PN7150 NFC controller.

Uploaded by

omar vargas

We take content rights seriously. If you suspect this is your content, claim it here.

Available Formats

Download as PDF, TXT or read online on Scribd

0% found this document useful (0 votes)

10 views69 pages

PN7150

Uploaded by

omar vargas

We take content rights seriously. If you suspect this is your content, claim it here.

Available Formats

Download as PDF, TXT or read online on Scribd

You are on page 1/ 69

PN7150

High performance NFC controller with integrated firmware, supporting all

NFC Forum modes
Rev. 4.2 — 2 February 2024 Product data sheet

1 Introduction
This document describes the functionality and electrical specification of the NFC Controller PN7150.
Additional documents describing the product functionality further are available for design-in support. Refer to the
references listed in this document to get access to the full documentation provided by NXP.
NXP Semiconductors
PN7150
High performance NFC controller with integrated firmware, supporting all NFC Forum modes

2 General description
Plug´n play and high-performance full NFC solution PN7150 is a full NFC controller solution with integrated
firmware and NCI interface designed for contactless communication at 13.56 MHz. It is compatible with NFC
forum requirements.
PN7150 is designed based on learnings from previous NXP NFC device generation. It is the ideal solution for
rapidly integrating NFC technology in any application, especially those running O/S environment like Linux and
Android, reducing Bill of Material (BOM) size and cost, thanks to:
• Full NFC forum compliancy (see [1]) with small form factor antenna
• Embedded NFC firmware providing all NFC protocols as pre-integrated feature
2
• Direct connection to the main host or microcontroller, by I C-bus physical and NCI protocol
• Ultra-low power consumption in polling loop mode
• Highly efficient integrated power management unit (PMU) allowing direct supply from a battery
PN7150 embeds a new generation RF contactless front-end supporting various transmission modes according
to NFCIP-1 and NFCIP-2, ISO/IEC 14443, ISO/IEC 15693, MIFARE Classic IC-based card and FeliCa card
specifications. It embeds an Arm Cortex-M0 microcontroller core loaded with the integrated firmware supporting
the NCI 1.0 host communication. It also allows to provide a higher output power by supplying the transmitter
output stage from 3.0 V to 4.75 V.
The contactless front-end design brings a major performance step-up with on one hand a higher sensitivity and
on the other hand the capability to work in active load modulation communication enabling the support of small
antenna form factor.
Figure 1 lists the supported transmission modes. For contactless card functionality, the PN7150 can act
autonomously if previously configured by the host in such a manner.
PN7150 integrated firmware provides an easy integration and validation cycle as all the NFC real-time
constraints, protocols and device discovery (polling loop) are being taken care internally. In few NCI commands,
host SW can configure the PN7150 to notify for card or peer detection and start communicating with them.

NFC FORUM READER CARD

NFC-IP MODES (PCD - VCD) (PICC)

READER FOR NFC FORUM ISO/IEC 14443 A T4T - ISO/IEC 14443 A

Tag Types 1 TO 5

ISO/IEC 14443 B T4T - ISO/IEC 14443 B

P2P ACTIVE
106 TO 424 kbps
INITIATOR AND TARGET ISO/IEC 15693 NFC FORUM T3T

MIFARE Classic 1K/4K

P2P PASSIVE
106 TO 424 kbps
INITIATOR AND TARGET MIFARE DESFire

Sony FeliCa(1)

aaa-023871

According to ISO/IEC 18092 (Ecma 340) standard.

Figure 1. PN7150 transmission modes

Product data sheet Rev. 4.2 — 2 February 2024

2 / 69
NXP Semiconductors
PN7150
High performance NFC controller with integrated firmware, supporting all NFC Forum modes

3 Features and benefits

• Includes NXP ISO/IEC14443-A and Innovatron ISO/IEC14443-B intellectual property licensing rights
• Arm Cortex-M0 microcontroller core
• Highly integrated demodulator and decoder
• Buffered output drivers to connect an antenna with minimum number of external components
• Integrated RF level detector
• Integrated Polling Loop for automatic device discovery
• RF protocols supported
– NFCIP-1, NFCIP-2 protocol (see [8] and [11])
– ISO/IEC 14443A, ISO/IEC 14443B PICC, NFC Forum T4T modes via host interface (see [3])
– NFC Forum T3T via host interface
– ISO/IEC 14443A, ISO/IEC 14443B PCD designed according to NFC Forum digital protocol T4T platform
and ISO-DEP (see [1])
– FeliCa PCD mode
– MIFARE Classic PCD encryption mechanism (MIFARE Classic 1K/4K)
– NFC Forum tag 1 to 5 (MIFARE Ultralight, Jewel, Open FeliCa tag, MIFARE DESFire) (see [1])
– ISO/IEC 15693/ICODE VCD mode (see [9])
• Supported host interfaces
– NCI protocol interface according to NFC Forum standardization (see [2])
2
– I C-bus High-speed mode (see [4])
• Integrated power management unit
– Direct connection to a battery (2.3 V to 5.5 V voltage supply range)
– Support different Hard Power-Down/Standby states activated by firmware
– Autonomous mode when host is shut down
2
• Automatic wake-up via RF field, internal timer and I C-bus interface
• Integrated non-volatile memory to store data and executable code for customization

Product data sheet Rev. 4.2 — 2 February 2024

3 / 69
NXP Semiconductors
PN7150
High performance NFC controller with integrated firmware, supporting all NFC Forum modes

4 Applications
• All devices requiring NFC functionality especially those running in an Android or Linux environment
• TVs, set-top boxes, blu-ray decoders, audio devices
• Home automation, gateways, wireless routers
• Home appliances
• Wearables, remote controls, healthcare, fitness
• Printers, IP phones, gaming consoles, accessories

Product data sheet Rev. 4.2 — 2 February 2024

4 / 69
NXP Semiconductors
PN7150
High performance NFC controller with integrated firmware, supporting all NFC Forum modes

5 Quick reference data

Table 1. Quick reference data
Symbol Parameter Conditions Min Typ Max Unit
[1]
VBAT battery supply voltage Card Emulation and Passive 2.3 - 5.5 V
[2]
Target; VSS = 0 V
[1]
Reader, Active Initiator and 2.7 - 5.5 V
[2]
Active Target; VSS = 0 V
VDD supply voltage internal supply voltage 1.65 1.8 1.95 V
VDD(PAD) VDD(PAD) supply voltage supply voltage for host
interface
[1]
• 1.8 V host supply;VSS = 0 V 1.65 1.8 1.95 V
[1]
• 3 V host supply; VSS = 0 V 3.0 - 3.6 V
[3]
IBAT battery supply current in Hard Power Down state;VBAT = 3.6 V; T - 10 14 μA
= 25 °C
in Standby state;VBAT = 3.6 V; T = 25 °C - 20 - μA
in Monitor state;VBAT = 2.75 V; T = 25 °C - - 14 μA
[4]
in low-power polling loop;VBAT = 3.6 V; T = - 150 - μA
25 °C;loop time = 500 ms
[2]
PCD mode at typical 3 V - - 190 mA
IO(VDDPAD) output current on pin total current which can be - - 15 mA
VDD(PAD) pulled on VDD(PAD) referenced
outputs
[2]
Ith(Ilim) current limit threshold current limiter on VDD(TX) pin;VDD(TX) = 3.3 - 180 - mA
current V

Ptot total power dissipation Reader; IVDD(TX) = 100 mA;VBAT = 5.5 V - - 420 mW
Tamb ambient temperature JEDEC PCB-0.5 -30 - +85 °C

[1] VSS represents VSS(PAD) and VSS(TX).

[2] The antenna should be tuned not to exceed this current limit (the detuning effect when coupling with another device must be taken into account).
[3] External clock on NFC_CLK_XTAL1 must be LOW.
[4] See [10] for computing the power consumption as it depends on several parameters.

Product data sheet Rev. 4.2 — 2 February 2024

5 / 69
NXP Semiconductors
PN7150
High performance NFC controller with integrated firmware, supporting all NFC Forum modes

6 Versions

6.1 Version C11006

PN7150B0HN/C11006 contains a firmware update compared to the previous version.
The firmware version is 10.01.AE and contains the following new features and fixes:
• Anti tearing mechanism: An Anti tearing mechanism has been added. For details, please refer to the User
Manual UM10936.
• A fix has been added that addresses a collision resolution problem for ISO 15693 tags in case there are
multiple tags in the field.
This Firmware version does not support the standby mode. The standby is not supported, also during
the polling sequence.

6.2 Version C11004

PN7150B0HN/C11004 has been withdrawn.

6.3 Version C11002

PN7150B0HN/C11002 and PN7150B0UK/C11002 is the initial released version.
The firmware version is 10.01.A0

Product data sheet Rev. 4.2 — 2 February 2024

6 / 69
NXP Semiconductors
PN7150
High performance NFC controller with integrated firmware, supporting all NFC Forum modes

7 Ordering information
Table 2. Ordering information
Type number Package
Name Description Version
[1]
PN7150B0HN/C110xx HVQFN40 plastic thermal enhanced very thin quad flat SOT618-1
package; no leads; 40 terminals; body; 6 mm × 6
mm × 0.85 mm
[1]
PN7150B0UK/C110xx WLCSP42 wafer level chip-scale package; 42 bumps; 2.88 mm SOT1459-1
× 2.80 mm × 0.54 mm (Backside coating included)
Do not use for new designs. Planned for
discontinuation.

[1] xx = firmware code variant

The product version C11006 does not support the standby mode. The standby is not supported, also
during the polling sequence.

Product data sheet Rev. 4.2 — 2 February 2024

7 / 69
NXP Semiconductors
PN7150
High performance NFC controller with integrated firmware, supporting all NFC Forum modes

8 Marking HVQFN40
Terminal 1 index area

Terminal 1 index area

A:7 A:7
B1 : 6

B2 : 6
B1 : 6
C:7

C:7

0 5

aaa-007965 aaa-038147

Figure 2. PN7150 package marking HVQFN40 (top view) Figure 3. PN7150 package marking HVQFN40 (top view)
4 lines 3 lines

Table 3. Marking codes

Type number Marking code
Line A 7 characters used: basic type number:PN7150x where x is
the FW variant
FW Variants:
Version C11001 (not released): x = 1
Version C11002 : x = 1
Version C11006: x = 6
Line B1 6 characters used: diffusion batch sequence
number
Line B2 (optional) 6 characters used: assembly ID number
Line C 7 characters used: manufacturing code
including:
• diffusion center code:
– Z: SSMC
– S: Powerchip (PTCT)
• assembly center code:
– S: ATKH
• RoHS compliancy indicator:
– D: Dark Green; fully compliant RoHS
and no halogen and antimony
• manufacturing year and week, 3 digits:
– Y: year
– WW: week code
• product life cycle status code:
– X: means not qualified product
– nothing means released product

Product data sheet Rev. 4.2 — 2 February 2024

8 / 69
NXP Semiconductors
PN7150
High performance NFC controller with integrated firmware, supporting all NFC Forum modes

9 Marking WLCSP42

aaa-028702

Figure 4. PN7150 package marking WLCSP42 (top view)

Table 4. WLCSP package marking (top view)

Line number Marking code
Line 1 Product identification
• Product name: 7150x; where x is the variant.
FW Variant:
Version C11002 : x = 2
Line 2 Diffusion batch sequence number
• Diffusion fabrication code: NNNNN
• Wafer ID: DD
Line 3 Manufacturing code including:
• Diffusion center code:
– Z: SSMC
– s: Global Foundry
– S: Power chip (PTCT)
• Assembly center code:
– Q: ASE-CL
• RoHS compliancy indicator:
– D: Dark Green; fully compliant RoHS and no halogen
and antimony
• Manufacturing year and week; 4 digits:
– YY: year
– WW: week code
• Mask layout version
• Product life cycle status code:
– X: not qualified product
– Nothing means released product
Line 4 NXP logo

Product data sheet Rev. 4.2 — 2 February 2024

9 / 69
NXP Semiconductors
PN7150
High performance NFC controller with integrated firmware, supporting all NFC Forum modes

10 Block diagram

CLESS CLESS UART HOST INTERFACE

INTERFACE UNIT
I2C-bus
RF DETECT SENSOR RX CODEC
SIGNAL
PROCESSING
DEMOD ADC TX CODEC

DRIVER TxCtrl
ARM DATA
CORTEX M0 MEMORY
PLL BG

SRAM
VMID

EEPROM

AHB to APB
MEMORY
CONTROL
CODE
POWER MISCELLANEOUS CLOCK MANAGEMENT UNIT MEMORY
MANAGEMENT UNIT
OSCILLATOR OSCILLATOR ROM
TIMERS
BATTERY 380 kHz 40 MHz
MONITOR
CRC FRACN QUARTZ
EEPROM
4.5 V 1.8 V COPROCESSOR PLL OSCILLATOR
TX-LDO DSLDO
RANDOM
NUMBER
GENERATOR

aaa-016737

Figure 5. PN7150 block diagram

Product data sheet Rev. 4.2 — 2 February 2024

10 / 69
NXP Semiconductors
PN7150
High performance NFC controller with integrated firmware, supporting all NFC Forum modes

11 Pinning information

11.1 Pinning HVQFN40

37 NFC_CLK_XTAL2
36 NFC_CLK_XTAL1
40 CLK_REQ
terminal 1

35 n.c.
34 n.c.
33 n.c.
32 n.c.
31 n.c.
39 i.c.
38 i.c.
index area

I2CADR0 1 30 VDDD
i.c. 2 29 VDD
I2CADR1 3 28 VDDA
VSS(PAD) 4 27 VSS
I2CSDA 5 26 VBAT
PN7150
VDD(PAD) 6 25 i.c.
I2CSCL 7 24 i.c.
IRQ 8 23 i.c.
VSS 9 VSS 22 VDD(TX_IN)
VEN 10 21 TX1
VBAT2 12
VBAT1 13
VDD(TX) 14
RXN 15
RXP 16
VDD(MID) 17
TX2 18
VSS(TX) 19
n.c. 20
i.c. 11

Transparent top view aaa-016738

Figure 6. Pinning

Table 5. Pin description

[1]
Symbol Pin Type Refer Description
2
I2CADR0 1 I VDD(PAD) I C-bus address 0
i.c. 2 - - internally connected; must be connected to GND
2
I2CADR1 3 I VDD(PAD) I C-bus address 1
VSS(PAD) 4 G n/a pad ground
2
I2CSDA 5 I/O VDD(PAD) I C-bus data line
VDD(PAD) 6 P n/a pad supply voltage
2
I2CSCL 7 I VDD(PAD) I C-bus clock line
IRQ 8 O VDD(PAD) interrupt request output
VSS 9 G n/a ground
VEN 10 I VBAT reset pin. Set the device in Hard Power Down
i.c. 11 - - internally connected; leave open
VBAT2 12 P n/a battery supply voltage; must be connected to VBAT
VBAT1 13 P n/a TXLDO input supply voltage
VDD(TX) 14 P n/a transmitter supply voltage
RXN 15 I VDD negative receiver input
PN7150 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Product data sheet Rev. 4.2 — 2 February 2024

11 / 69
NXP Semiconductors
PN7150
High performance NFC controller with integrated firmware, supporting all NFC Forum modes

Table 5. Pin description...continued

[1]
Symbol Pin Type Refer Description
RXP 16 I VDD positive receiver input
VDD(MID) 17 P n/a receiver reference input supply voltage
TX2 18 O VDD(TX) antenna driver output
VSS(TX) 19 G n/a contactless transmitter ground
n.c. 20 - - not connected
TX1 21 O VDD(TX) antenna driver output
VDD(TX_IN) 22 P n/a transmitter input supply voltage; must be connected to VDD(TX)
i.c. 23 - - internally connected; leave open
i.c. 24 - - internally connected; leave open
i.c. 25 - - internally connected; leave open
VBAT 26 P n/a battery supply voltage
VSS 27 G n/a ground
VDDA 28 P n/a analog supply voltage; must be connected to VDD
VDD 29 P n/a supply voltage
VDDD 30 P n/a digital supply voltage; must be connected to VDD
n.c. 31 - - not connected
n.c. 32 - - not connected
n.c. 33 - - not connected
n.c. 34 - - not connected
n.c. 35 - - not connected
NFC_CLK_XTAL1 36 I VDD oscillator input/PLL input
NFC_CLK_XTAL2 37 O VDD oscillator output
i.c. 38 - - internally connected; leave open
i.c. 39 - - internally connected; leave open
CLK_REQ 40 O VDD(PAD) clock request pin

[1] P = power supply

G = ground
I = input
O = output
I/O = input/output

Product data sheet Rev. 4.2 — 2 February 2024

12 / 69
NXP Semiconductors
PN7150
High performance NFC controller with integrated firmware, supporting all NFC Forum modes

11.2 Pinning WLCSP42

ball A1 1 2 3 4 5 6 7
index area
aaa-007576

Figure 7. WLCSP42 pinning (bottom view)

Table 6. WLCSP package marking (top view)

[1]
Symbol Pin Type Refer Description
VBAT2 A1 P n/a battery supply voltage; to be connected to VBAT
i.c. A2 - - internally connected; leave open
VBAT1 A3 P n/a TXLDO input supply voltage
RXN A4 I VDD negative receiver input
VDD(MID) A5 P n/a receiver reference input supply voltage
TX2 A6 O VDD(TX) antenna driver output
TX1 A7 O VDD(TX) antenna driver output
VSS B1 G n/a ground
VSS B2 G n/a ground
VDD(TX) B3 P n/a transmitter supply voltage
RXP B4 I VDD positive receiver input
VSS B5 G n/a ground
VSS(TX) B6 G n/a contactless transmitter ground
VDD(TX_IN) B7 P n/a transmitter input supply voltage; must be connected to VDD(TX)
IRQ C1 O VDD(PAD) interrupt request output
VDD(PAD) C2 P n/a pad supply voltage
VEN C3 I VBAT reset pin. Set the device in Hard Power Down
VSS C4 G n/a power ball. Shall be connected to ground for dissipation
VSS C5 G n/a power ball. Shall be connected to ground for dissipation
i.c. C6 - - internally connected; leave open
i.c. C7 - - internally connected; leave open
2
I2CSCL D1 I VDD(PAD) I C-bus clock line
2
I2CSDA D2 I/O VDD(PAD) I C-bus data line

Product data sheet Rev. 4.2 — 2 February 2024

13 / 69
NXP Semiconductors
PN7150
High performance NFC controller with integrated firmware, supporting all NFC Forum modes

Table 6. WLCSP package marking (top view)...continued

[1]
Symbol Pin Type Refer Description
CLK_REQ D3 O VDD(PAD) clock request pin
i.c. D4 - - internally connected; leave open
i.c. D5 - - internally connected; leave open
VDDD D6 P n/a digital supply voltage; must be connected to VDD
VBAT D7 P n/a battery supply voltage
VSS(PAD) E1 G n/a pad ground
2
I2CADR1 E2 I VDD(PAD) I C-bus address 1
i.c. E3 - - internally connected; leave open
NFC_CLK_XTAL1 E4 I VDD oscillator input/PLL input
i.c. E5 - - internally connected; leave open
i.c. E6 - - internally connected; leave open
VDD E7 P n/a LDO output supply voltage
2
I2CADR0 F1 I VDD(PAD) I C-bus address 0
i.c. F2 - - internally connected; must be connected to GND
NFC_CLK_XTAL2 F3 O VDD oscillator output
i.c. F4 - - internally connected; leave open
i.c. F5 - - internally connected; must be connected to GND
i.c. F6 - - internally connected; leave open
i.c. F7 - - internally connected; leave open

[1] P = power supply

G = ground
I = input
O = output
I/O = input/output

Product data sheet Rev. 4.2 — 2 February 2024

14 / 69
NXP Semiconductors
PN7150
High performance NFC controller with integrated firmware, supporting all NFC Forum modes

12 Functional description
2
PN7150 can be connected on a host controller through I C-bus. The logical interface towards the host
baseband is NCI-compliant [2] with additional command set for NXP-specific product features. This IC is fully
user controllable by the firmware interface described in [5].
Moreover, PN7150 provides flexible and integrated power management unit in order to preserve energy
supporting Power Off mode.
In the following chapters you will find also more details about PN7150 with references to very useful application
note such as:
• PN7150 User Manual ([5]):
User Manual describes the software interfaces (API) based on the NFC forum NCI standard. It does give full
description of all the NXP NCI extensions coming in addition to NCI standard ([2]).
• PN7150 Hardware Design Guide ([6]):
Hardware Design Guide provides an overview on the different hardware design options offered by the IC and
provides guidelines on how to select the most appropriate ones for a given implementation. In particular, this
document highlights the different chip power states and how to operate them in order to minimize the average
NFC-related power consumption so to enhance the battery lifetime.
• PN7150 Antenna and Tuning Design Guide ([7]):
Antenna and Tuning Design Guide provides some guidelines regarding the way to design an NFC antenna for
the PN7150 chip.
It also explains how to determine the tuning/matching network to place between this antenna and the PN7150.
Standalone antenna performances evaluation and final RF system validation (PN7150 + tuning/matching
network + NFC antenna within its final environment) are also covered by this document.
• PN7150 Low-Power Mode Configuration ([10]):
Low-Power Mode Configuration documentation provides guidance on how PN7150 can be configured in order
to reduce current consumption by using Low-power polling mode.

BATTERY/PMU

host interface
HOST control
NFCC
CONTROLLER

ANTENNA
MATCHING

aaa-016739

Figure 8. PN7150 connection

Product data sheet Rev. 4.2 — 2 February 2024

15 / 69
NXP Semiconductors
PN7150
High performance NFC controller with integrated firmware, supporting all NFC Forum modes

Note: To avoid data corruption inside the EEPROM memory, make sure to follow these rules:
• Prevent re-applying RF settings configuration when not required (different possibilities of implementation exist
depending on the integration environment, please contact NXP support for more details).
• Insure RF settings configuration is not interrupted (no interruption between related
CORE_SET_CONFIG_CMD and CORE_SET_CONFIG_RSP).
• Split the RF settings configuration into several CORE_SET_CONFIG_CMD to limit the time for the FW
to treat this command. Only one transferred RF parameter via the CORE_SET_CONFIG_CMD takes
approximately 2.7ms. 5.4ms in the specific case where the RF parameter resides in two separated Flash
memory blocks, which increase the probability for an interruption between CORE_SET_CONFIG_CMD and
CORE_SET_CONFIG_RSP.
• It must be ensured that the RF settings configuration will not be interrupted due to a power off or hardware
reset. Once the memory is corrupted, the IC cannot recover from this stage and cannot be used anymore.

12.1 System modes

12.1.1 System power modes

PN7150 is designed to enable the different power modes from the system.
Two power modes are specified: Full power mode and Power Off mode.

Table 7. System power mode description

System power mode Description
Full power mode the main supply (VBAT) as well as the host interface supply (VDD(PAD)) is
available, all use cases can be executed
Power Off mode the system is kept Hard Power Down (HPD)

Full power mode

[VBAT = On && VDD(PAD) = On

VEN = On]
[VBAT = Off || VEN = Off]

Power Off mode

[VEN = Off] aaa-015871

Figure 9. System power mode diagram

Product data sheet Rev. 4.2 — 2 February 2024

16 / 69
NXP Semiconductors
PN7150
High performance NFC controller with integrated firmware, supporting all NFC Forum modes

Table 8 summarizes the system power mode of the PN7150 depending on the status of the external supplies
available in the system:

Table 8. System power modes configuration

VBAT VEN Power mode
Off X Power Off mode
On Off Power Off mode
On On Full power mode

Depending on power modes, some application states are limited:

Table 9. System power mode descriptions

System power mode Allowed communication modes
Power Off mode no communication mode available
Full power mode Reader/Writer, Card Emulation, P2P modes

Product data sheet Rev. 4.2 — 2 February 2024

17 / 69
NXP Semiconductors
PN7150
High performance NFC controller with integrated firmware, supporting all NFC Forum modes

12.1.2 PN7150 power states

Next to system power modes defined by the status of the power supplies, the power states include the logical
status of the system thus extend the power modes.
4 power states are specified: Monitor, Hard Power Down (HPD), Standby, Active.

Table 10. PN7150 power states

Power state name Description
Monitor The PN7150 is supplied by VBAT which voltage is below its programmable
critical level, VEN voltage > 1.1 V and the Monitor state is enabled. The
system power mode is Power Off mode.
Hard Power Down The PN7150 is supplied by VBAT which voltage is above its programmable
critical level when Monitor state is enabled and PN7150 is kept in Hard
Power Down (VEN voltage is kept low by host or SW programming) to have
the minimum power consumption. The system power mode is in Power Off.
Standby The PN7150 is supplied by VBAT which voltage is above its programmable
critical level when the Monitor state is enabled, VEN voltage is high (by host
or SW programming) and minimum part of PN7150 is kept supplied to
enable
configured wake-up sources which allow to switch to Active state; RF
field,Host interface. The system power mode is Full power mode.
Active The PN7150 is supplied by VBAT which voltage is above its programmable
critical level when Monitor state is enabled, VEN voltage is high (by host or
SW programming) and the PN7150 internal blocks are supplied. 3 functional
modes are defined: Idle, Target and Initiator. The system power mode is Full
power mode.

At application level, the PN7150 will continuously switch between different states to optimize the current
consumption (polling loop mode). Refer to Table 1 for targeted current consumption in here described states.
The PN7150 is designed to allow the host controller to have full control over its functional states, thus of
the power consumption of the PN7150 based NFC solution and possibility to restrict parts of the PN7150
functionality.

12.1.2.1 Monitor state

In Monitor state, the PN7150 will exit it only if the battery voltage recovers over the critical level. Battery voltage
monitor thresholds show hysteresis behavior as defined in Table 27.

12.1.2.2 Hard Power Down (HPD) state

The Hard Power Down state is entered when VDD(PAD) and VBAT are high by setting VEN voltage < 0.4 V. As
these signals are under host control, the PN7150 has no influence on entering or exiting this state.

Product data sheet Rev. 4.2 — 2 February 2024

18 / 69
NXP Semiconductors
PN7150
High performance NFC controller with integrated firmware, supporting all NFC Forum modes

12.1.2.3 Standby state

Active state is PN7150’s default state after boot sequence in order to allow a quick configuration of PN7150. It is
recommended to change the default state to Standby state after first boot in order to save power. PN7150 can
switch to Standby state autonomously (if configured by host).
In this state, PN7150 most blocks including CPU are no more supplied. Number of wake-up sources exist to put
PN7150 into Active state:
2
• I C-bus interface wake-up event
• Antenna RF level detector
• Internal timer event when using polling loop (380 kHz Low-power oscillator is enabled)
If wake-up event occurs, PN7150 will switch to Active state. Any further operation depends on software
configuration and/or wake-up source.

12.1.2.4 Active state

Within the Active state, the system is acting as an NFC device. The device can be in 3 different functional
modes: Idle, Poller and Target.

Table 11. Functional modes in active state

Functional modes Description
Idle the PN7150 is active and allows host interface communication. The RF
interface is not activated.
Listener the PN7150 is active and is configured for listening to external device.
Poller the PN7150 is active and is configured in Poller mode. It polls external
device

Poller mode
In this mode, PN7150 is acting as Reader/Writer or NFC Initiator,
searching for or communicating with passive tags or NFC target. Once
RF communication has ended, PN7150 will switch to active battery
mode (that is, switch off RF transmitter) to save energy. Poller mode
shall be used with 2.7 V < VBAT < 5.5 V and VEN voltage > 1.1 V.
Poller mode shall not be used with VBAT < 2.7 V. VDD(PAD) is within its
operational range (see Table 1).

Listener mode
In this mode, PN7150 is acting as a card or as an NFC Target. Listener
mode shall be used with 2.3 V < VBAT < 5.5 V and VEN voltage > 1.1 V.

Product data sheet Rev. 4.2 — 2 February 2024

19 / 69
NXP Semiconductors
PN7150
High performance NFC controller with integrated firmware, supporting all NFC Forum modes

12.1.2.5 Polling loop

The polling loop will sequentially set PN7150 in different power states (Active or Standby). All RF technologies
supported by PN7150 can be independently enabled within this polling loop.
There are 2 main phases in the polling loop:
• Listening phase. The PN7150 can be in Standby power state or Listener mode
• Polling phase. The PN7150 is in Poller mode

Listening phase

Emulation

Pause

Type A

Type B

Type F
@424
Type F
@212
ISO15693
Polling phase

aaa-016741

Figure 10. Polling loop: all phases enabled

Listening phase uses Standby power state (when no RF field) and PN7150 goes to Listener mode when RF
field is detected. When in Polling phase, PN7150 goes to Poller mode.

Product data sheet Rev. 4.2 — 2 February 2024

20 / 69
NXP Semiconductors
PN7150
High performance NFC controller with integrated firmware, supporting all NFC Forum modes

To further decrease the power consumption when running the polling loop, PN7150 features a low-power
RF polling. When PN7150 is in Polling phase instead of sending regularly RF command, PN7150 senses
with a short RF field duration if there is any NFC Target or card/tag present. If yes, then it goes back to
standard polling loop. With 500 ms (configurable duration, see [5]) listening phase duration, the average power
consumption is around 150 μA.

Listening phase

Emulation

Pause

Polling phase

aaa-016743

Figure 11. Polling loop: low-power RF polling

The detailed description of polling loop configuration options is given in [5].

12.2 Microcontroller
PN7150 is controlled via an embedded ARM Cortex-M0 microcontroller core.
PN7150 features integrated in firmware are referenced in [5].

12.3 Host interface

2
PN7150 provides the support of an I C-bus Slave Interface, up to 3.4 MBaud.
2
The host interface is waken-up on I C-bus address.
To enable and ensure data flow control between PN7150 and host controller, additionally a dedicated interrupt
line IRQ is provided which Active state is programmable. See [5] for more information.

Product data sheet Rev. 4.2 — 2 February 2024

21 / 69
NXP Semiconductors
PN7150
High performance NFC controller with integrated firmware, supporting all NFC Forum modes

2
12.3.1 I C-bus interface
2 2
The I C-bus interface implements a slave I C-bus interface with integrated shift register, shift timing generation
and slave address recognition.
2
I C-bus Standard mode (100 kHz SCL), Fast mode (400 kHz SCL) and High-speed mode (3.4 MHz SCL) are
supported.
2
The mains hardware characteristics of the I C-bus module are:
2
• Support slave I C-bus
• Standard, Fast and High-speed modes supported
• Wake-up of PN7150 on its address only
• Serial clock synchronization can be used by PN7150 as a handshake mechanism to suspend and resume
serial transfer (clock stretching)
2 2
The I C-bus interface module meets the I C-bus specification [4] except General call, 10-bit addressing and
Fast mode Plus (Fm+).

2
12.3.1.1 I C-bus configuration
2 2 2
The I C-bus interface shares four pins with I C-bus interface also supported by PN7150. When I C-bus is
configured in EEPROM settings, functionality of interface pins changes to one described in Table 10.
2
Table 12. Functionality for I C-bus interface
Pin name Functionality
2
I2CADR0 I C-bus address 0
2
I2CADR1 I C-bus address 1
2
I2CSCL
[1] I C-bus clock line
2
I2CSDA
[1] I C-bus data line

[1] I2CSCL and I2CSDA are not fail-safe and VDD(pad) shall always be available when using the SCL and SDA
lines connected to these pins.
2
PN7150 supports 7-bit addressing mode. Selection of the I C-bus address is done by 2-pin configurations on
top of a fixed binary header: 0, 1, 0, 1, 0, I2CADR1, I2CADR0, R/W.
2
Table 13. I C-bus interface addressing
2 2
I2CADR1 I2CADR0 I C-bus address I C-bus address
(R/W = 0, write) (R/W = 1, read)
0 0 0x50 0x51
0 1 0x52 0x53
1 0 0x54 0x55
1 1 0x56 0x57

Product data sheet Rev. 4.2 — 2 February 2024

22 / 69
NXP Semiconductors
PN7150
High performance NFC controller with integrated firmware, supporting all NFC Forum modes

12.4 PN7150 clock concept

There are 4 different clock sources in PN7150:
• 27.12 MHz clock coming either/or from:
– Internal oscillator for 27.12 MHz crystal connection
– Integrated PLL unit which includes a 1 GHz VCO, taking is reference clock on pin NFC_CLK_XTAL1
• 13.56 MHz RF clock recovered from RF field
• Low-power oscillator 40 MHz
• Low-power oscillator 380 kHz

12.4.1 27.12 MHz quartz oscillator

When enabled, the 27.12 MHz quartz oscillator applied to PN7150 is the time reference for the RF front end
when PN7150 is behaving in Reader mode or NFCIP-1 initiator.
Therefore stability of the clock frequency is an important factor for reliable operation. It is recommended to
adopt the circuit shown in Figure 12.

PN7150

NFC_CLK_XTAL1 NFC_CLK_XTAL2

crystal
c c
27.12 MHz

aaa-016745

Figure 12. 27.12 MHz crystal oscillator connection

Table 14 describes the levels of accuracy and stability required on the crystal.

Table 14. Crystal requirements

Symbol Parameter Conditions Min Typ Max Unit
fxtal crystal frequency ISO/IEC and FCC - 27.12 - MHz
compliancy
[1]
Δfxtal crystal frequency accuracy full operating range -100 - +100 ppm
[1]
all VBAT range;T = 20 °C -50 - +50 ppm
[1]
all temperature range;VBAT = -50 - +50 ppm
3.6 V
ESR equivalent series resistance - 50 100 Ω
CL load capacitance - 10 - pF
Pxtal crystal power dissipation - - 100 μW

[1] This requirement is according to FCC regulations requirements. To meet only ISO/IEC 14443 and ISO/IEC 18092, then ± 14 kHz apply.

Product data sheet Rev. 4.2 — 2 February 2024

23 / 69
NXP Semiconductors
PN7150
High performance NFC controller with integrated firmware, supporting all NFC Forum modes

12.4.2 Integrated PLL to make use of external clock

When enabled, the PLL is designed to generate a low noise 27.12 MHz for an input clock 13 MHz, 19.2 MHz,
24 MHz, 26 MHz, 38.4 MHz and 52 MHz.
The 27.12 MHz of the PLL is used as the time reference for the RF front end when PN7150 is behaving in
Reader mode or ISO/IEC 18092 Initiator as well as in Target when configured in Active Communication mode.
The input clock on NFC_CLK_XTAL1 shall comply with the following phase noise requirements for the following
input frequency: 13 MHz, 19.2 MHz, 24 MHz, 26 MHz, 38.4 MHz and 52 MHz:

dBc/Hz

-20dBc/Hz

Input reference
noise floor
-140 dBc/Hz

Input reference noise corner Hz

50 kHz aaa-007232

Figure 13. Input reference phase noise characteristics

This phase noise is equivalent to an RMS jitter of 6.23 ps from 10 Hz to 1 MHz. For configuration of input
frequency, refer to [9]. Thee six pre-programmed and validated frequencies for the PLL are: 13 MHz, 19.2 MHz,
24 MHz, 26 MHz, 38.4 MHz and 52 MHz.

Table 15. PLL input requirements

Coupling: single-ended, AC coupling;
Symbol Parameter Conditions Min Typ Max Unit
fclk clock frequency ISO/IEC and FCC - 13 - MHz
compliance - 19.2 - MHz
- 24 - MHz
- 26 - MHz
- 38.4 - MHz
- 52 - MHz
[1]
fi(ref)acc reference input full operating range;frequencies -25 - +25 ppm
frequency accuracy typical values:13 MHz, 26 MHz and
52 MHz
[1]
full operating range;frequencies -50 - +50 ppm
typical values:19.2 MHz, 24 MHz
and
38.4 MHz
φn phase noise input noise floor at 50 kHz -140 - - dB/
Hz
Sinusoidal shape
Vi(p-p) peak-to-peak input 0.2 - 1.8 V
voltage

Product data sheet Rev. 4.2 — 2 February 2024

24 / 69
NXP Semiconductors
PN7150
High performance NFC controller with integrated firmware, supporting all NFC Forum modes

Table 15. PLL input requirements...continued

Coupling: single-ended, AC coupling;
Symbol Parameter Conditions Min Typ Max Unit
Vi(clk) clock input voltage 0 - 1.8 V
Square shape
Vi(clk) clock input voltage 0 - 1.8 ± 10 % V

[1] This requirement is according to FCC regulations requirements. To meet only ISO/IEC 14443 and ISO/IEC 18092, then ± 400 ppm limits apply.

For detailed description of clock request mechanisms, refer to [5] and [6].

12.4.3 Low-power 40 MHz ± 2.5 % oscillator

Low-power OSC generates a 40 MHz internal clock. This frequency is divided by two to make the system clock.

12.4.4 Low-power 380 kHz oscillator

A Low Frequency Oscillator (LFO) is implemented to drive a counter (WUC) waking-up PN7150 from Standby
state. This allows implementation of low-power reader polling loop at application level. Moreover, this 380 kHz is
used as the reference clock for write access to EEPROM memory.

12.5 Power concept

12.5.1 PMU functional description

The Power Management Unit of PN7150 generates internal supplies required by PN7150 out of VBAT input
supply voltage:
• VDD: internal supply voltage
• VDD(TX): output supply voltage for the RF transmitter
Figure 14 shows the main blocks available in the PMU.

VBAT VDD VBAT1 and VBAT2

DSLDO

BANDGAP VDD(TX)
TXLDO

NFCC

aaa-016748

Figure 14. PMU functional diagram

Product data sheet Rev. 4.2 — 2 February 2024

25 / 69
NXP Semiconductors
PN7150
High performance NFC controller with integrated firmware, supporting all NFC Forum modes

12.5.2 DSLDO: dual supply LDO

The input pin of the DSLDO is VBAT.
The Low drop-out regulator provides VDD required in PN7150.

12.5.3 TXLDO
Transmitter voltage can be generated by internal LDO (VDD(TX)) or come from an external supply source
VDD(TX).
The regulator has been designed to work in two configurations:

12.5.3.1 Configuration 1: supply connection in case the battery is used to generate RF field
The Low drop Out Regulator has been designed to generate a 3.0 V, 3.3 V or 3.6 V supply voltage to a
transmitter with a current load up to 180 mA.
The output is called VDD(TX). The input supply voltage of this regulator is a battery voltage connected to VBAT1
pin.

VBAT1
BATTERY

VBAT2

NFCC
VDD(TX)

VDD(TX_IN)

aaa-017002

Figure 15. VBAT1 = VBAT2 (between 2.3 V and 5.5 V)

VDD(TX) value shall be chosen according to the minimum targeted VBAT value for which reader mode shall work.
• If VBAT is above 3.0 V plus the regulator voltage dropout, then VDD(TX) = 3.0 V shall be chosen:

• If VBAT is above 3.3 V plus the regulator voltage dropout, then VDD(TX) = 3.3 V shall be chosen:

• If VBAT is above 3.6 V plus the regulator voltage dropout, then VDD(TX) = 3.6 V shall be chosen:

Product data sheet Rev. 4.2 — 2 February 2024

26 / 69
NXP Semiconductors
PN7150
High performance NFC controller with integrated firmware, supporting all NFC Forum modes

5.0 V

VB
AT

3.6 V
Drop = 1 Ω * load
3.3 V

3.0 V

2.8 V
4.5 V 3.6 V 3.3 V 3.0 V 2.8 V

aaa-014174

Figure 16. VDD(TX) offset behavior

Figure 16 shows VDD(TX) offset disabled behavior for both cases of VDD(TX) programmed for 3.0 V, 3.3 V or
3.6 V.
In Standby state, whenever VDD(TX) is configured for 3.0 V, 3.3 V or 3.6 V, VDD(TX) is regulated at 2.5 V.

VBAT

2.5 V

2.5 V
aaa-009463

Figure 17. VDD(TX) behavior when PN7150 is in Standby state

Figure 17 shows the case where the PN7150 is in standby state.

Product data sheet Rev. 4.2 — 2 February 2024

27 / 69
NXP Semiconductors
PN7150
High performance NFC controller with integrated firmware, supporting all NFC Forum modes

12.5.3.2 Configuration 2: supply connection in case a 5 V supply is used to generate RF field

with the use of TXLDO
TXLDO has also the possibility to generate 4.75 V or 4.5 V supply in case the supply of this regulator is an
external 5 V supply.

VBAT1
EXTERNAL 5 V

VBAT2
BATTERY
NFCC
VDD(TX)

VDD(TX_IN)

aaa-017003

Figure 18. VBAT1 = 5 V, VBAT2 between 2.3 V and 5.5 V

5.5 V VBAT1

4.75 V
VDD(TX)
4.5 V

Drop = 1 * load

aaa-017004

Figure 19. VDD(TX) behavior when PN7150 is supply using external supply on VBAT1

Figure 19 shows the behavior of VDD(TX) depending on VBAT1 value.

12.5.3.3 TXLDO limiter

The TXLDO includes a current limiter to avoid too high current within TX1, TX2 when in reader or initiator
modes.
The current limiter block compares an image of the TXLDO output current to a reference. Once the reference is
reached, the output current gets limited which is equivalent to a typical output current of 220 mA whatever VBAT
or VBAT1 value in the range of 2.3 V to 5.5 V.

Product data sheet Rev. 4.2 — 2 February 2024

28 / 69
NXP Semiconductors
PN7150
High performance NFC controller with integrated firmware, supporting all NFC Forum modes

12.5.4 Battery voltage monitor

The PN7150 features low-power VBAT voltage monitor which protects mobile device battery from being
discharged below critical levels. When VBAT voltage goes below VBATcritical threshold, then the PN7150 goes in
Monitor state. Refer to Figure 20 for the principle schematic of the battery monitor.
The battery voltage monitor is enabled via an EEPROM setting.
At the first start-up, VBAT voltage monitor functionality is OFF and then enabled if properly configured in
EEPROM. The PN7150 monitors battery voltage continuously.

VBAT

enable
VBAT
EEPROM REGISTERS
MONITOR
threshold
selection

SYSTEM
low power MANAGEMENT
POWER
VDD
MANAGEMENT
VDDD

power off
POWER SWITCHES

DVDD_CPU DIGITAL
(memories, cpu,
etc,...)

aaa-013868

Figure 20. Battery voltage monitor principle

The value of the critical level can be configured to 2.3 V or 2.75 V by an EEPROM setting. This value has a
typical hysteresis around 150 mV.

Product data sheet Rev. 4.2 — 2 February 2024

29 / 69
NXP Semiconductors
PN7150
High performance NFC controller with integrated firmware, supporting all NFC Forum modes

12.6 Reset concept

12.6.1 Resetting PN7150

To enter reset, there are 2 ways:
• Pulling VEN voltage low (Hard Power Down state)
• if VBAT monitor is enabled: lowering VBAT below the monitor threshold (Monitor state, if VEN voltage is kept
above 1.1 V)
Reset means resetting the embedded FW execution and the registers values to their default values. Part of
these default values is defined from EEPROM data loaded values, others are hardware defined. See [5] to know
which ones are accessible to tune PN7150 to the application environment.
To get out of reset:
• Pulling VEN voltage high with VBAT above VBAT monitor threshold if enabled
Figure 21 shows the reset via VEN pin.

VBAT

VDD(PAD)

host
VEN tw(VEN) tboot communication
possible
aaa-015878

Figure 21. Resetting PN7150 via VEN pin

See Section 16.2.2 for the timings values.

Product data sheet Rev. 4.2 — 2 February 2024

30 / 69
NXP Semiconductors
PN7150
High performance NFC controller with integrated firmware, supporting all NFC Forum modes

12.6.2 Power-up sequences

PN7150 has two power supplies. PN7150 allows these supplies to be set up independently, therefore different
power-up sequences have to be considered.

12.6.2.1 VBAT is set up before VDD(PAD)

This is at least the case when VBAT pin is directly connected to the battery and when PN7150 VBAT is always
supplied as soon the system is supplied.
As VEN pin is referred to VBAT pin, VEN voltage shall go high after VBAT has been set.

VBAT

VDD(PAD)

tt(VDD(PAD)-VEN) tboot

host
VEN communication
possible
aaa-015879

Figure 22. VBAT is set up before VDD(PAD)

See Section 16.2.3 for the timings values.

12.6.2.2 VDD(PAD) and VBAT are set up in the same time

It is at least the case when VBAT pin is connected to a PMU/regulator which also supply VDD(PAD).

VBAT

tt(VBAT-VEN)

VDD(PAD)

tboot

host
VEN communication
possible
aaa-015881

Figure 23. VDD(PAD) and VBAT are set up at the same time

See Section 16.2.3 for the timings values.

Product data sheet Rev. 4.2 — 2 February 2024

31 / 69
NXP Semiconductors
PN7150
High performance NFC controller with integrated firmware, supporting all NFC Forum modes

12.6.2.3 PN7150 has been enabled before VDD(PAD) is set up or before VDD(PAD) has been cut off
This can be the case when VBAT pin is directly connected to the battery and when VDD(PAD) is generated from a
PMU. When the battery voltage is too low, then the PMU might no more be able to generate VDD(PAD). When the
device gets charged again, then VDD(PAD) is set up again.
As the pins to select the interface are biased from VDD(PAD), when VDD(PAD) disappears the pins might not be
correctly biased internally and the information might be lost. Therefore it is required to make the IC boot after
VDD(PAD) is set up again.

VBAT

VDD(PAD)

tt(VDD(PAD)-VEN) tboot

host
VEN tW(VEN) communication
possible
aaa-015884

Figure 24. VDD(PAD) is set up or cut-off after PN7150 has been enabled

See Section 16.2.3 for the timings values.

12.6.3 Power-down sequence

tVBAT(L)

VBAT

t > 0 ms t > 0 ms
(nice to have)
VEN

VDD(PAD)

aaa-015886

Figure 25. Power-down sequence

12.7 Contactless interface unit

PN7150 supports various communication modes at different transfer speeds and modulation schemes. The
following sections describe selected communication modes.
Remark: all indicated modulation index and modes in this chapter are system parameters. This means that
beside the IC settings a suitable antenna tuning is required to achieve the optimum performance.

Product data sheet Rev. 4.2 — 2 February 2024

32 / 69
NXP Semiconductors
PN7150
High performance NFC controller with integrated firmware, supporting all NFC Forum modes

12.7.1 Reader/Writer communication modes

Generally 5 Reader/Writer communication modes are supported:
• PCD Reader/Writer for ISO/IEC 14443 type A and for MIFARE Classic
• PCD Reader/Writer for Jewel/Topaz
• PCD Reader/Writer for FeliCa
• PCD Reader/Writer for ISO/IEC 14443B
• VCD Reader/Writer for ISO/IEC 15693/ICODE

Product data sheet Rev. 4.2 — 2 February 2024

33 / 69
NXP Semiconductors
PN7150
High performance NFC controller with integrated firmware, supporting all NFC Forum modes

12.7.1.1 Communication mode for ISO/IEC 14443 type A, MIFARE Classic and Jewel/Topaz
PCD
The ISO/IEC 14443A and MIFARE Classic PCD communication mode is the general reader to card
communication scheme according to the ISO/IEC 14443A specification. This modulation scheme is as well used
for communications with Jewel/Topaz cards.
Figure 26 describes the communication on a physical level, the communication table describes the physical
parameters (the numbers take the antenna effect on modulation depth for higher data rates).

PCD to PICC
100 % ASK at 106 kbit/s
> 25 % ASK at 212, 424 or 848 kbit/s
Modified Miller coded
NFCC PICC (Card)

PICC to PCD,
subcarrier load modulation
ISO/IEC 14443A - Manchester coded at 106 kbit/s
MIFARE Classic BPSK coded at 212, 424 or 848 kbit/s ISO/IEC 14443A -
PCD mode MIFARE Classic

aaa-016749

Figure 26. Read/write mode for ISO/IEC 14443 type A and read/write mode for MIFARE Classic

Table 16. Communication overview for ISO/IEC 14443 type A and read/write mode for MIFARE Classic
Communication ISO/IEC 14443A/ ISO/IEC 14443A higher transfer speeds
direction MIFARE Classic/
Jewel/ Topaz
Transfer speed 106 kbit/s 212 kbit/s 424 kbit/s 848 kbit/s
Bit length (128/13.56) μs (64/13.56) μs (32/13.56) μs (16/13.56) μs
PN7150 → PICC
(data sent by PN7150 to a modulation on 100 % ASK > 25 % ASK > 25 % ASK > 25 % ASK
card) PN7150 side
bit coding Modified Miller Modified Miller Modified Miller Modified Miller
PICC → PN7150
(data received by PN7150 modulation on subcarrier load subcarrier load subcarrier load subcarrier load
from a card) PICC side modulation modulation modulation modulation
subcarrier 13.56 MHz/16 13.56 MHz/16 13.56 MHz/16 13.56 MHz/16
frequency
bit coding Manchester BPSK BPSK BPSK

The contactless coprocessor and the on-chip CPU of PN7150 handle the complete ISO/IEC 14443A and
MIFARE Classic RF-protocol, nevertheless a dedicated external host has to handle the application layer
communication.

Product data sheet Rev. 4.2 — 2 February 2024

34 / 69
NXP Semiconductors
PN7150
High performance NFC controller with integrated firmware, supporting all NFC Forum modes

12.7.1.2 FeliCa PCD communication mode

The FeliCa communication mode is the general Reader/Writer to card communication scheme according to the
FeliCa specification. Figure 27 describes the communication on a physical level, the communication overview
describes the physical parameters.

PCD to PICC,
8 - 12 % ASK at 212 or 424 kbits/s
Manchester coded
NFCC PICC (Card)

PICC to PCD,
load modulation
ISO/IEC 18092 - FeliCa Manchester coded at 212 or 424 kbits/s FeliCa card
PCD mode

aaa-016750

Figure 27. FeliCa Reader/Writer communication mode diagram

Table 17. Overview for FeliCa Reader/Writercommunication mode

Communication direction FeliCa FeliCa higher transfer speeds
Transfer speed 212 kbit/s 424 kbit/s
Bit length (64/13.56) μs (32/13.56) μs
PN7150 → PICC
(data sent by PN7150 to a card) modulation on 8 % - 12 % ASK 8 % - 12 % ASK
PN7150 side
bit coding Manchester Manchester
PICC → PN7150
(data received by PN7150 from a card) modulation on PICC load modulation load modulation
side
subcarrier frequency no subcarrier no subcarrier
bit coding Manchester Manchester

The contactless coprocessor of PN7150 and the on-chip CPU handle the FeliCa protocol. Nevertheless a
dedicated external host has to handle the application layer communication.

Product data sheet Rev. 4.2 — 2 February 2024

35 / 69
NXP Semiconductors
PN7150
High performance NFC controller with integrated firmware, supporting all NFC Forum modes

12.7.1.3 ISO/IEC 14443B PCD communication mode

The ISO/IEC 14443B PCD communication mode is the general reader to card communication scheme
according to the ISO/IEC 14443B specification. Figure 28 describes the communication on a physical level, the
communication table describes the physical parameters.

PCD to PICC,
8 - 14 % ASK at 106, 212, 424 or 848 kbit/s
NRZ coded
NFCC PICC (Card)

PICC to PCD,
subcarrier load modulation
ISO/IEC 14443 Type B BPSK coded at 106, 212, 424 or 848 kbit/s ISO/IEC 14443 Type B
PCD mode

aaa-016751

Figure 28. ISO/IEC 14443B Reader/Writer communication mode diagram

Table 18. Overview for ISO/IEC 14443B Reader/Writer communication mode

Communication ISO/IEC 14443B ISO/IEC 14443B higher transfer speeds
direction Transfer speed 106 kbit/s 212 kbit/s 424 kbit/s 848 kbit/s
Bit length (128/13.56) μs (64/13.56) μs (32/13.56) μs (16/13.56) μs
PN7150 → PICC
(data sent by PN7150 to a modulation on 8 % - 14 % ASK 8 % - 14 % ASK 8 % - 14 % ASK 8 % - 14 % ASK
card) PN7150 side
bit coding NRZ NRZ NRZ NRZ
PICC → PN7150
(data received by PN7150 modulation on subcarrier load subcarrier load subcarrier load subcarrier load
from a card) PICC side modulation modulation modulation modulation
subcarrier 13.56 MHz/16 13.56 MHz/16 13.56 MHz/16 13.56 MHz/16
frequency
bit coding BPSK BPSK BPSK BPSK

The contactless coprocessor and the on-chip CPU of PN7150 handles the complete ISO/IEC 14443B RF-
protocol, nevertheless a dedicated external host has to handle the application layer communication.

Product data sheet Rev. 4.2 — 2 February 2024

36 / 69
NXP Semiconductors
PN7150
High performance NFC controller with integrated firmware, supporting all NFC Forum modes

12.7.1.4 R/W mode for NFC forum Type 5 Tag

The R/W mode for NFC forum Type 5 Tag (T5T) is the general reader to card communication scheme according
to the ISO/IEC 15693 specification. PN7150 communicates with VICC (Type 5 Tag) using only the 26.48 kbit/s
with single subcarrier data rate of the VICC.

VCD to VICC,
100 % ASK at 26.48 kbit/s
pulse position coded
NFCC Card
(VICC/TAG)
VICC to VCD,
subcarrier load modulation
ISO/IEC 15693 Manchester coded at 26.48 kbit/s ISO/IEC 15693
VCD mode

aaa-016752

Figure 29. R/W mode for NFC forum T5T communication diagram

Figure 29 and Table 19 show the communication schemes used.

Table 19. Communication overview for NFC forum T5T R/W mode
Communication direction
PN7150 → VICC
(data sent by PN7150 to a tag) transfer speed 26.48 kbit/s
bit length (512/13.56) μs
modulation on PN7150 side 100 % ASK
bit coding pulse position modulation 1 out of 4 mode
VICC → PN7150
(data received by PN7150 from a tag) transfer speed 26.48 kbit/s
bit length (512/13.56) μs
modulation on VICC side subcarrier load modulation
subcarrier frequency single subcarrier
bit coding Manchester

Product data sheet Rev. 4.2 — 2 February 2024

37 / 69
NXP Semiconductors
PN7150
High performance NFC controller with integrated firmware, supporting all NFC Forum modes

12.7.2 ISO/IEC 18092, Ecma 340 NFCIP-1 communication modes

An NFCIP-1 communication takes place between 2 devices:
• NFC Initiator: generates RF field at 13.56 MHz and starts the NFCIP-1 communication.
• NFC Target: responds to NFC Initiator command either in a load modulation scheme in Passive
communication mode or using a self-generated and self-modulated RF field for Active communication mode.
The NFCIP-1 communication differentiates between Active and Passive communication modes.
• Active communication mode means both the NFC Initiator and the NFC Target are using their own RF field to
transmit data
• Passive communication mode means that the NFC Target answers to an NFC Initiator command in a load
modulation scheme. The NFC Initiator is active in terms of generating the RF field.
PN7150 supports the Active Target, Active Initiator, Passive Target and Passive Initiator communication modes
at the transfer speeds 106 kbit/s, 212 kbit/s and 424 kbit/s as defined in the NFCIP-1 standard.

BATTERY BATTERY

NFCC NFCC

HOST HOST

NFC Initiator: Passive or Active Communication modes NFC Target: Passive or Active Communication modes
aaa-016755

Figure 30. FNFCIP-1 communication mode

A dedicated external host handles the application layer communication.

Product data sheet Rev. 4.2 — 2 February 2024

38 / 69
NXP Semiconductors
PN7150
High performance NFC controller with integrated firmware, supporting all NFC Forum modes

12.7.2.1 ACTIVE communication mode

Active communication mode means both the NFC Initiator and the NFC Target are using their own RF field to
transmit data.

host NFCC host

NFC Initiator
1. NFC Initiator starts the communication at selected transfer speed NFC Target

power power
to generate for digital
the field processing

host NFCC host

NFC Initiator
NFC Target
2. NFC Target answers at the same transfer speed

power power
for digital to generate
processing the field
aaa-016756

Figure 31. Active communication mode

The following table gives an overview of the Active communication modes:

Table 20. Overview for Active communication mode

Communication direction ISO/IEC 18092, Ecma 340, NFCIP-1
Baud rate 106 kbit/s 212 kbit/s 424 kbit/s
Bit length (128/13.56) μs (64/13.56) μs (32/13.56) μs
NFC Initiator → NFC Target
[1] [1]
modulation 100 % ASK 8 % - 30 % ASK 8 % - 30 % ASK
bit coding Modified Miller Manchester Manchester
NFC Target → NFC Initiator
[1] [1]
modulation 100 % ASK 8 % - 30 % ASK 8 % - 30 % ASK
bit coding Miller Manchester Manchester

[1] This modulation index range is according to NFCIP-1 standard. It might be that some NFC forum type 3 cards does not withstand the full range as based
on FeliCa range which is narrow (8 % to 14 % ASK).

Product data sheet Rev. 4.2 — 2 February 2024

39 / 69
NXP Semiconductors
PN7150
High performance NFC controller with integrated firmware, supporting all NFC Forum modes

12.7.2.2 Passive communication mode

Passive communication mode means that the NFC Target answers to an NFC Initiator command in a load
modulation scheme.

host NFCC host

NFC Initiator
1. NFC Initiator starts the communication at selected transfer speed NFC Target

power power
to generate for digital
the field processing

host NFCC host

NFC Initiator
NFC Target
2. NFC Target answers using load modulation at the same transfer speed

power power
to generate for digital
the field processing

aaa-016757

Figure 32. Passive communication mode

Table 21 gives an overview of the Passive communication modes:

Table 21. Overview for passive communication mode

Communication direction ISO/IEC 18092, Ecma 340, NFCIP-1
Baud rate 106 kbit/s 212 kbit/s 424 kbit/s
Bit length (128/13.56) μs (64/13.56) μs (32/13.56) μs
NFC Initiator → NFC Target
[1] [1]
modulation 100 % ASK 8 % - 30 % ASK 8 % - 30 % ASK
bit coding Modified Miller Manchester Manchester
NFC Target → NFC Initiator
modulation subcarrier load load modulation load modulation
modulation
subcarrier frequency 13.56 MHz/16 no subcarrier no subcarrier
bit coding Manchester Manchester Manchester

Product data sheet Rev. 4.2 — 2 February 2024

40 / 69
NXP Semiconductors
PN7150
High performance NFC controller with integrated firmware, supporting all NFC Forum modes

12.7.2.3 NFCIP-1 framing and coding

The NFCIP-1 framing and coding in Active and Passive communication modes are defined in the NFCIP-1
standard: ISO/IEC 18092 or Ecma 340.

12.7.2.4 NFCIP-1 protocol support

The NFCIP-1 protocol is not completely described in this document. For detailed explanation of the protocol,
refer to the ISO/IEC 18092 or Ecma 340 NFCIP-1 standard. However the datalink layer is according to the
following policy:
• Transaction includes initialization, anticollision methods and data transfer. This sequence must not be
interrupted by another transaction
• PSL shall be used to change the speed between the target selection and the data transfer, but the speed
should not be changed during a data transfer

12.7.3 Card communication modes

PN7150 can be addressed as NFC forum T3T and T4T tags. This means that PN7150 can generate an answer
in a load modulation scheme according to the ISO/IEC 14443A, ISO/IEC 14443B and the Sony FeliCa interface
description.
Remark: PN7150 does not support a complete card protocol. This has to be handled by the host controller.
Table 20, Table 21 and Table 22 describe the physical parameters.

12.7.3.1 NFC forum T4T, ISO/IEC 14443Acard mode

Table 22. Overview for NFC forum T4T, ISO/IEC 14443A card mode
Communication ISO/IEC 14443A ISO/IEC 14443A higher transfer speeds
direction Transfer speed 106 kbit/s 212 kbit/s 424 kbit/s
Bit length (128/13.56) μs (64/13.56) μs (32/13.56) μs
PCD → PN7150
(data received by PN7150 modulation on PCD 100 % ASK > 25 % ASK > 25 % ASK
from a card) side
bit coding Modified Miller Modified Miller Modified Miller
PN7150 → PCD
(data sent by PN7150 to a modulation on subcarrier load modulation subcarrier load subcarrier load
card) PN7150 side modulation modulation
subcarrier 13.56 MHz/16 13.56 MHz/16 13.56 MHz/16
frequency
bit coding Manchester BPSK BPSK

Product data sheet Rev. 4.2 — 2 February 2024

41 / 69
NXP Semiconductors
PN7150
High performance NFC controller with integrated firmware, supporting all NFC Forum modes

12.7.3.2 NFC forum T4T, ISO/IEC 14443B card mode

Table 23. Overview for NFC forum T4T, ISO/IEC 14443B card mode
Communication ISO/IEC 14443B ISO/IEC 14443B higher transfer speeds
direction Transfer speed 106 kbit/s 212 kbit/s 424 kbit/s
Bit length (128/13.56) μs (64/13.56) μs (32/13.56) μs
PCD → PN7150
(data received by PN7150 modulation on PCD 8 % - 14 % ASK 8 % - 14 % ASK 8 % - 14 % ASK
from a Reader) side
bit coding NRZ NRZ NRZ
PN7150 → PCD
(data sent by PN7150 to a modulation on subcarrier load subcarrier load subcarrier load
Reader) PN7150 side modulation modulation modulation
subcarrier 13.56 MHz/16 13.56 MHz/16 13.56 MHz/16
frequency
bit coding BPSK BPSK BPSK

12.7.3.3 NFC forum T3T, Sony FeliCa card mode

Table 24. Overview for NFC forum T3T, Sony FeliCa card mode
Communication direction FeliCa FeliCa higher transfer speeds
Transfer speed 212 kbit/s 424 kbit/s
Bit length (64/13.56) μs (32/13.56) μs
PCD → PN7150
(data received by PN7150 from a Reader) modulation on 8 % - 12 % ASK 8 % - 12 % ASK
PN7150 side
bit coding Manchester Manchester
PN7150 → PCD
(data sent by PN7150 to a Reader) modulation on PICC load modulation load modulation
side
subcarrier frequency no subcarrier no subcarrier
bit coding Manchester Manchester

12.7.4 Frequency interoperability

When in communication, PN7150 is generating some RF frequencies. PN7150 is also sensitive to some RF
signals as it is looking from data in the field.
In order to avoid interference with others RF communication, it is required to tune the antenna and design the
board according to [6].
Although ISO/IEC 14443 and ISO/IEC 18092/Ecma 340 allows an RF frequency of 13.56 MHz ± 7 kHz, FCC
regulation does not allow this wide spread and limits the dispersion to ± 50 ppm, which is in line with PN7150
capability.

Product data sheet Rev. 4.2 — 2 February 2024

42 / 69
NXP Semiconductors
PN7150
High performance NFC controller with integrated firmware, supporting all NFC Forum modes

13 Limiting values
Table 25. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
VDD(PAD) VDD(PAD) supply voltage supply voltage for host - 4.35 V
interface
VBAT battery supply voltage - 6 V
[1]
VESD electrostatic discharge voltage human body model (HBM) ; 1500 - 1.5 kV
Ω, 100 pF
[2]
charge device model (CDM) - 500 V
Tstg storage temperature -55 +150 °C
[3]
Ptot total power dissipation all modes - 600 mW
VRXN(i) RXN input voltage 0 2.5 V
VRXP(i) RXP input voltage 0 2.5 V

[1] According to ANSI/ESDA/JEDEC JS-001.

[2] According to ANSI/ESDA/JEDEC JS-002
[3] The design of the solution shall be done so that for the different use cases targeted the power to be dissipated from the field or generated by PN7150
does not exceed this value.

Product data sheet Rev. 4.2 — 2 February 2024

43 / 69
NXP Semiconductors
PN7150
High performance NFC controller with integrated firmware, supporting all NFC Forum modes

14 Recommended operating conditions

Table 26. Operating conditions
Symbol Parameter Conditions Min Typ Max Unit
Tamb ambient temperature JEDEC PCB-0.5 -30 +25 +85 °C
VBAT battery supply voltage battery monitor enabled;VSS = [1][1] 2.3 - 5.5 V
0V
[1]
Card Emulation and 2.3 - 5.5 V
[2]
Passive Target;VSS = 0 V
[1]
Reader, Active Initiator 2.7 - 5.5 V
[2]
and Active Target;VSS = 0 V
VDD(PAD) VDD(PAD) supply voltage supply voltage for host
interface
[1]
• 1.8 V host supply;VSS = 0 V 1.65 1.8 1.95 V
[1]
• 3 V host supply;VSS = 0 V 3.0 - 3.6 V
Ptot total power dissipation Reader;IVDD(TX) = 100 mA;VBAT - - 420 mW
= 5.5 V
[3]
IBAT battery supply current in Hard Power Down - 10 14 μA
state; VBAT = 3.6 V;T = 25 °C
in Standby state;VBAT = 3.6 V; T - 20 - μA
= 25 °C
in Monitor state;VBAT = 2.75 V; - - 14 μA
T = 25 °C
[4]
in low-power polling - 150 - μA
loop; VBAT = 3.6 V; T =
25 °C;loop time = 500 ms
[5]
PCD mode at typical 3 V - - 190 mA
[5]
Ith(Ilim) current limit threshold current limiter on VDD(TX) - 180 - mA
current pin; VDD(TX) = 3.3 V

[1] VSS represents VSS(PAD) and VSS(TX).

Product data sheet Rev. 4.2 — 2 February 2024

44 / 69
NXP Semiconductors
PN7150
High performance NFC controller with integrated firmware, supporting all NFC Forum modes

15 Thermal characteristics

15.1 Thermal characteristics HVQFN40

Table 27. Thermal characteristics
Symbol Parameter Conditions Min Typ Max Unit
Rth(j-a) thermal resistance from in free air with exposed pad soldered on a - 40 - K/W
junction to ambient 4 layer JEDEC PCB

15.2 Thermal characteristics WLCSP42

Table 28. Thermal characteristics
Symbol Parameter Conditions Min Typ Max Unit
Rth(j-a) thermal resistance from in free air with exposed pad soldered on a - 42 - K/W
junction to ambient 4 layer JEDEC PCB

Product data sheet Rev. 4.2 — 2 February 2024

45 / 69
NXP Semiconductors
PN7150
High performance NFC controller with integrated firmware, supporting all NFC Forum modes

16 Characteristics

16.1 Current consumption characteristics

Table 29. Current consumption characteristics for operating ambient temperature range
Symbol Parameter Conditions Min Typ Max Unit
IBAT battery supply current in Hard Power Down - 10 20 μA
state; VBAT = 3.6 V; VEN
voltage = 0 V
[1]
in Standby state;VBAT = 3.6 V; - 20 35 μA
in Idle and Listener - 4.55 - mA
modes; VBAT = 3.6 V
in Poller mode;VBAT = 3.6 V - 150 - mA
[2]
in Monitor state;VBAT = 2.75 V - 10 20 μA

[1] Refer to Section 12.1.2 for the description of the power modes.
[2] This is the same value for VBAT = 2.3 V when the monitor threshold is set to 2.3 V.

16.2 Functional block electrical characteristics

16.2.1 Battery voltage monitor characteristics

Table 30. Battery voltage monitor characteristics
Symbol Parameter Conditions Min Typ Max Unit
Vth threshold voltage set to 2.3 V 2.15 2.3 2.45 V
set to 2.75 V 2.6 2.75 2.9 V
Vhys hysteresis voltage 100 150 200 mV

16.2.2 Reset via VEN

Table 31. Reset timing
Symbol Parameter Conditions Min Typ Max Unit
tW(VEN) VEN pulse width to reset 10 - - μs
tboot boot time - - 2.5 ms

16.2.3 Power-up timings

Table 32. Power-up timings
Symbol Parameter Conditions Min Typ Max Unit
tt(VBAT-VEN) transition time from pin VBAT to pin VBAT, VEN 0 0.5 - ms
VEN voltage = HIGH
tt(VDDPAD-VEN) transition time from pin VDD(PAD), VEN 0 0.5 - ms
VDD(PAD) to pin VEN voltage = HIGH
tt(VBAT-VDDPAD) transition time from pin VBAT to pin VBAT,VDD(PAD) = HIGH 0 0.5 - ms
VDD(PAD)

Product data sheet Rev. 4.2 — 2 February 2024

46 / 69
NXP Semiconductors
PN7150
High performance NFC controller with integrated firmware, supporting all NFC Forum modes

16.2.4 Power-down timings

Table 33. Power-down timings
Symbol Parameter Conditions Min Typ Max Unit
tVBAT(L) time VBAT LOW 20 - - ms

2
16.2.5 I C-bus timings
2
Figure 33, Table 34, and Table 35 describe I C-bus timings and frequency specifications.

tf(I2CSDA) tr(I2CSDA) tHD;DAT

I2CSDA

tSU;STA tHD;STA tHIGH

tSU;DAT

tLOW
I2CSCL

aaa-017006
2
Figure 33. I C-bus timings

2
Table 34. High-speed mode I C-bus timings specification
Symbol Parameter Conditions Min Max Unit
2
fclk(I2CSCL) clock frequency on pin I C-bus SCL;Cb < 100 pF 0 3.4 MHz
I2CSCL
tSU;STA set-up time for a repeated Cb < 100 pF 160 - ns
START condition
tHD;STA hold time (repeated) START Cb < 100 pF 160 - ns
condition
tLOW LOW period of the SCL clock Cb < 100 pF 160 - ns
tHIGH HIGH period of the SCL clock Cb < 100 pF 60 - ns
tSU;DAT data set-up time Cb < 100 pF 10 - ns
tHD;DAT data hold time Cb < 100 pF 0 - ns
2
tr(I2CSDA) rise time on pin I2CSDA I C-bus SDA;Cb < 100 pF 10 80 ns
2
tf(I2CSDA) fall time on pin I2CSDA I C-bus SDA;Cb < 100 pF 10 80 ns
Vhys hysteresis voltage Schmitt trigger inputs;Cb < 0.1VDD(PAD) - V
100 pF

Product data sheet Rev. 4.2 — 2 February 2024

47 / 69
NXP Semiconductors
PN7150
High performance NFC controller with integrated firmware, supporting all NFC Forum modes

2
Table 35. Fast mode I C-bus timings specification
Symbol Parameter Conditions Min Max Unit
2
fclk(I2CSCL) clock frequency on pin I2CSCL I C-bus SCL;Cb < 400 pF 0 400 kHz
tSU;STA set-up time for a repeated Cb < 400 pF 600 - ns
START condition
tHD;STA hold time (repeated) START Cb < 400 pF 600 - ns
condition
tLOW LOW period of the SCL clock Cb < 400 pF 1.3 - μs
tHIGH HIGH period of the SCL clock Cb < 400 pF 600 - ns
tSU;DAT data set-up time Cb < 400 pF 100 - ns
tHD;DAT data hold time Cb < 400 pF 0 900 ns
Vhys hysteresis voltage Schmitt trigger inputs;Cb < 0.1VDD(PAD) - V
400 pF

Product data sheet Rev. 4.2 — 2 February 2024

48 / 69
NXP Semiconductors
PN7150
High performance NFC controller with integrated firmware, supporting all NFC Forum modes

16.3 Pin characteristics

16.3.1 NFC_CLK_XTAL1 and NFC_CLK_XTAL2 pins characteristics

Table 36. Input clock characteristics on NFC_CLK_XTAL1 when using PLL
Symbol Parameter Conditions Min Typ Max Unit
Vi(p-p) peak-to-peak input voltage 0.2 - 1.8 V
δ duty cycle 35 - 65 %

Table 37. Pin characteristics for NFC_CLK_XTAL1 when PLL input

Symbol Parameter Conditions Min Typ Max Unit
IIH HIGH-level input current VI = VDD -1 - +1 μA
IIL LOW-level input current VI = 0 V -1 - +1 μA
Vi input voltage - - VDD V
Vi(clk)(p-p) peak-to-peak clock input 200 - - mV
voltage
Ci input capacitance all power modes - 2 - pF

Table 38. Pin characteristics for 27.12 MHz crystal oscillator

Symbol Parameter Conditions Min Typ Max Unit
Ci(NFC_CLK_XTAL1) NFC_CLK_XTAL1 input VDD = 1.8 V - 2 - pF
capacitance
Ci(NFC_CLK_XTAL2) NFC_CLK_XTAL2 input - 2 - pF
capacitance

Table 39. PLL accuracy

Symbol Parameter Conditions Min Typ Max Unit
fo(acc) output frequency deviation added to -50 - +50 ppm
accuracy NFC_CLK_XTAL1 frequency on RF
frequency generated;worst case
whatever input frequency

Product data sheet Rev. 4.2 — 2 February 2024

49 / 69
NXP Semiconductors
PN7150
High performance NFC controller with integrated firmware, supporting all NFC Forum modes

16.3.2 VEN input pin characteristics

Table 40. VEN input pin characteristics
Symbol Parameter Conditions Min Typ Max Unit
VIH HIGH-level input voltage 1.1 - VBAT V
VIL LOW-level input voltage 0 - 0.4 V
IIH HIGH-level input current VEN voltage = VBAT -1 - +1 μA
IIL LOW-level input current VEN voltage = 0 V -1 - +1 μA
Ci input capacitance - 5 - pF

16.3.3 Pin characteristics for IRQ and CLK_REQ

Table 41. pin characteristics for IRQ and CLK_REQ
Symbol Parameter Conditions Min Typ Max Unit
VOH HIGH-level output IOH < 3 mA VDD(PAD) - 0.4 - VDD(PAD) V
voltage
VOL LOW-level output IOL < 3 mA 0 - 0.4 V
voltage
CL load capacitance - - 20 pF
tf fall time CL = 12 pF max
• high speed 1 - 3.5 ns
• slow speed 2 - 10 ns
tr rise time CL = 12 pF max
• high speed 1 - 3.5 ns
• slow speed 2 - 10 ns
[1]
Rpd pull-down resistance 0.35 - 0.85 MΩ

[1] Activated in HPD and Monitor states.

Product data sheet Rev. 4.2 — 2 February 2024

50 / 69
NXP Semiconductors
PN7150
High performance NFC controller with integrated firmware, supporting all NFC Forum modes

16.3.4 Input pin characteristics for RXN and RXP

Table 42. Input pin characteristics for RXN and RXP
Symbol Parameter Conditions Min Typ Max Unit
VRXN(i) RXN input voltage 0 - VDD V
VRXP(i) RXP input voltage 0 - VDD V
Ci(RXN) RXN input capacitance - 12 - pF
Ci(RXP) RXP input capacitance - 12 - pF
Zi(RXN-VDDMID) input impedance between Reader, Card and 0 - 15 kΩ
RXN and VDD(MID) P2P modes
Zi(RXP-VDDMID) input impedance between Reader, Card and 0 - 15 kΩ
RXP and VDD(MID) P2P modes
Vi(dyn)(RXN) RXN dynamic input voltage Miller coded
• 106 kbit/s - 150 200 mV(p-p)
• 212 kbit/s to - 150 200 mV(p-p)
424 kbit/s
Vi(dyn)(RXP) RXP dynamic input voltage Miller coded
• 106 kbit/s - 150 200 mV(p-p)
• 212 kbit/s to - 150 200 mV(p-p)
424 kbit/s
Vi(dyn)(RXN) RXN dynamic input voltage Manchester, NRZ - 150 200 mV(p-p)
or BPSK coded;106
kbit/s to 848 kbit/s
Vi(dyn)(RXP) RXP dynamic input voltage Manchester, NRZ - 150 200 mV(p-p)
or BPSK coded;106
kbit/s to 848 kbit/s
Vi(dyn)(RXN) RXN dynamic input voltage All data coding;106 kbit/ VDD - - V(p-p)
s to
848 kbit/s
Vi(dyn)(RXP) RXP dynamic input voltage All data coding;106 kbit/ VDD - - V(p-p)
s to
848 kbit/s
Vi(RF) RF input voltage RF input voltage 100 - mV(p-p)
detected; Initiator
modes

Product data sheet Rev. 4.2 — 2 February 2024

51 / 69
NXP Semiconductors
PN7150
High performance NFC controller with integrated firmware, supporting all NFC Forum modes

16.3.5 Output pin characteristics for TX1 and TX2

Table 43. Output pin characteristics for TX1 and TX2
Symbol Parameter Conditions Min Typ Max Unit
VOH HIGH-level output VDD(TX) = 3.3 V and VDD(TX) - 150 - - mV
voltage IOH = 30 mA;PMOS driver
fully on
VOL LOW-level output VDD(TX) = 3.3 V and - - 200 mV
voltage IOL = 30 mA;NMOS driver
fully on

Table 44. Output resistance for TX1 and TX2

Symbol Parameter Conditions Min Typ Max Unit
ROL LOW-level output VDD(TX) - 100 mV;CWGsN = - - 85 Ω
resistance 01h

ROL LOW-level output VDD(TX) - 100 mV;CWGsN = - - 5 Ω

resistance 0Fh

ROH HIGH-level output VDD(TX) - 100 mV - - 4 Ω

resistance

16.3.6 Input pin characteristics for I2CADR0 and I2CADR1

Table 45. Input pin characteristics for I2CADR0 and I2CADR1
Symbol Parameter Conditions Min Typ Max Unit
VIH HIGH-level input 0.65VDD(PAD) - VDD(PAD) V
voltage
VIL LOW-level input 0 - 0.35VDD(PAD) V
voltage
IIH HIGH-level input VI = VDD(PAD) -1 - +1 μA
current
IIL LOW-level input VI = 0 V -1 - +1 μA
current
Ci input capacitance - 5 - pF

Product data sheet Rev. 4.2 — 2 February 2024

52 / 69
NXP Semiconductors
PN7150
High performance NFC controller with integrated firmware, supporting all NFC Forum modes

16.3.7 Pin characteristics for I2CSDA and I2CSCL

Table 46. Pin characteristics for I2CSDA and I2CSCL
Symbol Parameter Conditions Min Typ Max Unit
VOL LOW-level output IOL < 3 mA [1] 0 - 0.4 V
voltage
CL load capacitance - - 10 pF
tf fall time CL = 100 pF;Rpull-up = 2 [1] 30 - 250 ns
kΩ;Standard and Fast mode
tf fall time CL = 100 pF;Rpull-up = 1 [1] 80 - 110 ns
kΩ;High-speed mode
tr rise time CL = 100 pF;Rpull-up = 2 [1] 30 - 250 ns
kΩ;Standard and Fast mode
CL = 100 pF; [1] 10 - 100 ns
Rpull-up = 1 kΩ;
High-speed mode
VIH HIGH-level input 0.7VDD(PAD) - VDD(PAD) V
voltage
VIL LOW-level input 0 - 0.3VDD(PAD) V
voltage
IIH HIGH-level input VI = VDD(PAD);high impedance -1 - +1 μA
current
IIL LOW-level input VI = 0 V;high impedance -1 - +1 μA
current
Ci input capacitance - 5 - pF

[1] Only for pin I2CSDA as I2CSCL is only used as input.

16.3.8 VDD pin characteristic

Table 47. Electrical characteristic of VDD
Symbol Parameter Conditions Min Typ Max Unit
VDD VDD supply voltage VSS = 0 V 1.65 1.8 1.95 V

Product data sheet Rev. 4.2 — 2 February 2024

53 / 69
NXP Semiconductors
PN7150
High performance NFC controller with integrated firmware, supporting all NFC Forum modes

17 Package outline

17.1 Package outline HVQFN40

HVQFN40: plastic thermal enhanced very thin quad flat package; no leads;
40 terminals; body 6 x 6 x 0.85 mm SOT618-1

D B A

terminal 1
index area
A
A1
E c

detail X

e1
C
v C A B
e 1/2 e b y1 C y
w C
11 20
L
21
10

Eh e2

1/2 e

1
30
terminal 1
index area 40 31
Dh X

0 2.5 5 mm

Dimensions (mm are the original dimensions) scale

Unit A(1) A1 b c D(1) Dh E(1) Eh e e1 e2 L v w y y1

max 1.00 0.05 0.30 0.2 6.1 4.25 6.1 4.25 0.5 4.5 4.5 0.5 0.1 0.05 0.05 0.1
mm nom 0.85 0.02 0.21 6.0 4.10 6.0 4.10 0.4
min 0.80 0.00 0.18 5.9 3.95 5.9 3.95 0.3
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. sot618-1_po

Outline References European

Issue date
version IEC JEDEC JEITA projection
02-10-22
SOT618-1 MO-220
13-11-05

Figure 34. Package outline, HVQFN40, SOT618-1, MSL3

Product data sheet Rev. 4.2 — 2 February 2024

54 / 69
NXP Semiconductors
PN7150
High performance NFC controller with integrated firmware, supporting all NFC Forum modes

17.2 Package outline WLCSP42

WLCSP42: wafer level chip-scale package; 42 bumps; 2.88 x 2.80 x 0.54 mm (Backside coating included) SOT1459-1

D B A

ball A1
index area
A2
E A

detail X

e1 C
Øv C A B
e b y
Øw C

F
e
E

D
e2
C
1/2 e
B

ball A1 1 2 3 4 5 6 7
index area X

0 3 mm
scale

Dimensions (mm are the original dimensions)

Unit A A1 A2 b D E e e1 e2 v w y

max 0.58 0.23 0.37 0.29 2.90 2.82

mm nom 0.54 0.20 0.34 0.26 2.88 2.80 0.4 2.4 2.0 0.15 0.05 0.05
min 0.50 0.17 0.31 0.23 2.86 2.78
Note: Backside coating 40 µm sot1459-1_po

Outline References European

Issue date
version IEC JEDEC JEITA projection
16-09-01
SOT1459-1 --- ---
16-09-02

Figure 35. Package outline, WLCSP42, SOT1459-1

Product data sheet Rev. 4.2 — 2 February 2024

55 / 69
NXP Semiconductors
PN7150
High performance NFC controller with integrated firmware, supporting all NFC Forum modes

18 Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can
be found in Application Note AN10365 "Surface mount reflow soldering description".

18.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards
(PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection.
There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when
through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with
increased miniaturization.

18.2 Wave and reflow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of
liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have
solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch
smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by component placement and
exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all
reflow solderable.
Key characteristics in both wave and reflow soldering are:
• Board specifications, including the board finish, solder masks and vias
• Package footprints, including solder thieves and orientation
• The moisture sensitivity level of the packages
• Package placement
• Inspection and repair
• Lead-free soldering versus SnPb soldering

18.3 Wave soldering

Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave
parameters, and the time during which components are exposed to the wave
• Solder bath specifications, including temperature and impurities

Product data sheet Rev. 4.2 — 2 February 2024

56 / 69
NXP Semiconductors
PN7150
High performance NFC controller with integrated firmware, supporting all NFC Forum modes

18.4 Reflow soldering

Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak
temperatures (see Figure 36) than a SnPb process, thus reducing the process window.
• Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large
and small components on one board.
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak
temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to
make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low
enough that the packages and/or boards are not damaged. The peak temperature of the package depends on
package thickness and volume and is classified in accordance with Table 48 and Table 49.

Table 48. SnPb eutectic process (from J-STD-020D)

Package thickness (mm) Package reflow temperature (°C)
3
Volume (mm )
< 350 ≥ 350
< 2.5 235 220
≥ 2.5 220 220

Table 49. Lead-free process (from J-STD-020D)

Package thickness (mm) Package reflow temperature (°C)
3
Volume (mm )
< 350 350 to 2 000 > 2 000
< 1.6 260 260 260
1.6 to 2.5 260 250 245
> 2.5 250 245 245

Moisture sensitivity precautions, as indicated on the packing, must be respected at all times.

Product data sheet Rev. 4.2 — 2 February 2024

57 / 69
NXP Semiconductors
PN7150
High performance NFC controller with integrated firmware, supporting all NFC Forum modes

Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 36.

maximum peak temperature

temperature = MSL limit, damage level

minimum peak temperature

= minimum soldering temperature

peak
temperature

time
001aac844

MSL: Moisture Sensitivity Level

Figure 36. Temperature profiles for large and small components

For further information on temperature profiles, refer to [12].

Product data sheet Rev. 4.2 — 2 February 2024

58 / 69
NXP Semiconductors
PN7150
High performance NFC controller with integrated firmware, supporting all NFC Forum modes

19 Abbreviations
Table 50. Abbreviations
Acronym Description
API Application Programming Interface
ASK Amplitude Shift keying
ASK modulation The ASK modulation index is defined as the voltage ratio (Vmax - Vmin)/
index (Vmax + Vmin) × 100%
Automatic device Detect and recognize any NFC peer devices (initiator or target) like: NFC
discovery initiator or target, ISO/IEC 14443-3, -4 Type A&B PICC, MIFARE Classic
and MIFARE Ultralight PICC, ISO/IEC 15693 VICC
BPSK Bit Phase Shift Keying
Card Emulation The IC is capable of handling a PICC emulation on the RF interface including
part of the protocol management. The application handling is done by the host controller
DEP Data Exchange Protocol
DSLDO Dual Supplied LDO
FW FirmWare
HPD Hard Power Down
LDO Low Drop Out
LFO Low Frequency Oscillator
MOSFET Metal Oxide Semiconductor Field Effect Transistor
MSL Moisture Sensitivity Level
NCI NFC Controller Interface
NFC Near Field Communication
NFCC NFC Controller, PN7150 in this data sheet
NFC Initiator Initiator as defined in ISO/IEC 18092 or ECma 340: NFCIP-1 communication
NFCIP NFC Interface and Protocol
NFC Target Target as defined in ISO/IEC 18092 or ECma 340: NFCIP-1 communication
NRZ Non-Return to Zero
P2P Peer to Peer
PCD Proximity Coupling Device. Definition for a Card reader/writer device
according to the ISO/IEC 14443 specification or MIFARE Classic
PCD -> PICC Communication flow between a PCD and a PICC according to the
ISO/IEC 14443 specification or MIFARE Classic
PICC Proximity Interface Coupling Card. Definition for a contactless Smart Card
according to the ISO/IEC 14443 specification or MIFARE Classic
PICC-> PCD Communication flow between a PICC and a PCD according to the
ISO/IEC 14443 specification or MIFARE Classic
PMOS P-channel MOSFET
PMU Power Management Unit

Product data sheet Rev. 4.2 — 2 February 2024

59 / 69
NXP Semiconductors
PN7150
High performance NFC controller with integrated firmware, supporting all NFC Forum modes

Table 50. Abbreviations...continued

Acronym Description
PSL Parameter SeLection
TXLDO Transmitter LDO
UM User Manual
VCD Vicinity Coupling Device. Definition for a reader/writer device according to the
ISO/IEC 15693 specification
VCO Voltage Controlled Oscillator
VICC Vicinity Integrated Circuit Card
WUC Wake-Up Counter

Product data sheet Rev. 4.2 — 2 February 2024

60 / 69
NXP Semiconductors
PN7150
High performance NFC controller with integrated firmware, supporting all NFC Forum modes

20 References
[1] NFC Forum Device Requirements V1.3
[2] NFC Controller Interface (NCI) Technical Specification V1.0
[3] ISO/IEC 14443 parts 2: 2001 COR 1 2007 (01/11/2007), part 3: 2001 COR 1 2006 (01/09/2006) and part
4: 2nd edition 2008 (15/07/2008)
2
[4] UM10204 I C-bus Specification and User Manual (link)
[5] UM10936 - PN7150 User Manual (link)
[6] AN11756 - PN7150 Hardware Design Guide (link)
[7] AN11755 - PN7150 Antenna Design and Matching Guide (link)
[8] ISO/IEC 18092 (NFCIP-1) edition, 15/032013. This is similar to Ecma 340.
[9] ISO/IEC 15693 part 2: 2nd edition (15/12/2006), part 3: 1st edition (01/04/2001)
[10] AN11757 - PN7150 Low-Power Mode Configuration (link)
[11] ISO/IEC 21481 (NFCIP-2) edition, 01/07/2012. This is similar to Ecma 352.
[12] AN10365 - Surface Mount Reflow Soldering Description (link)

Product data sheet Rev. 4.2 — 2 February 2024

61 / 69
NXP Semiconductors
PN7150
High performance NFC controller with integrated firmware, supporting all NFC Forum modes

21 Revision history
Table 51. Revision history
Document ID Release date Data sheet status Change notice Supersedes
PN7150 v4.2 20240202 Product data sheet PN7150 v4.1
Modifications: • Section 8 "Marking HVQFN40": updated the firmware version.
• Section 9 "Marking WLCSP42": updated the firmware version.
PN7150 v4.1 20230127 Product data sheet - PN7150 v4.0
Modifications: • Statement added that "The product version C11006 does not support the standby mode. The
standby is not supported, also during the polling sequence. " in Section 6.1 and Section 7
PN7150 v4.0 20200625 Product data sheet - PN7150 v3.9
Modifications: • Included new product type PN7150B0HN/C11006
• Marked PN7150B0UK/C11002 to be come discontinued
• Added information about withdrawal of PN7150B0HN/C11004
PN7150 v3.9 20190828 Product data sheet - PN7150 v3.8
Modifications: • Added a version history of the different firmware versions, see Section 6
PN7150 v3.8 20181030 Product data sheet - PN7150 v3.7
Modifications: • Section 12 "Functional description": added a note regarding EEPROM memory.
PN7150 v3.7 20180424 Product data sheet - PN7150 v3.6
Modifications: • Section 12.6.1: fixed some cross references.
PN7150 v3.6 20171127 Product data sheet - PN7150 v3.5
Modifications: • Minor typos corrected.
• Included new product type PN7150B0UK/C11002
PN7150 v3.5 20171018 Product data sheet - PN7150 v3.4
Modifications: • Table 19 "Communication overview for NFC forum T5T R/W mode ": updated.
PN7150 v3.4 20171004 Product data sheet - PN7150 v3.3
Modifications: • Descriptive title updated
• Section 2: updated the figure.
• Updated MIFARE branding.
PN7150 v3.3 20160704 Product data sheet - PN7150 v3.2
Modifications: • Figure 1: updated.
• Section 12.7.1.4 "R/W mode for NFC forum Type 5 Tag": updated.
• Section 12.7.3 "Card communication modes": updated.
PN7150 v3.2 201600525 Product data sheet - PN7150 v3.1
PN7150 v3.1 20160511 Product data sheet - PN7150 v3.0
PN7150 v3.0 20151209 Product data sheet - PN7150 v2.1
PN7150 v2.1 20151127 Preliminary data sheet - PN7150 v2.0
PN7150 v2.0 20150701 Preliminary data sheet - PN7150 v1.2
PN7150 v1.2 20150625 Objective data sheet - PN7150 v1.1
PN7150 v1.1 20150212 Objective data sheet - PN7150 v1.0

Product data sheet Rev. 4.2 — 2 February 2024

62 / 69
NXP Semiconductors
PN7150
High performance NFC controller with integrated firmware, supporting all NFC Forum modes

Table 51. Revision history...continued

Document ID Release date Data sheet status Change notice Supersedes
PN7150 v1.0 20150129 Objective data sheet - -
Modifications: • Initial version

Product data sheet Rev. 4.2 — 2 February 2024

63 / 69
NXP Semiconductors
PN7150
High performance NFC controller with integrated firmware, supporting all NFC Forum modes

Legal information

Data sheet status

[1][2] [3]
Document status Product status Definition
Objective [short] data sheet Development This document contains data from the objective specification for product
development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.

[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term 'short data sheet' is explained in section "Definitions".
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple
devices. The latest product status information is available on the Internet at URL https://www.nxp.com.

Definitions Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
Draft — A draft status on a document indicates that the content is still malfunction of an NXP Semiconductors product can reasonably be expected
under internal review and subject to formal approval, which may result to result in personal injury, death or severe property or environmental
in modifications or additions. NXP Semiconductors does not give any damage. NXP Semiconductors and its suppliers accept no liability for
representations or warranties as to the accuracy or completeness of inclusion and/or use of NXP Semiconductors products in such equipment or
information included in a draft version of a document and shall have no applications and therefore such inclusion and/or use is at the customer’s own
liability for the consequences of use of such information. risk.

Short data sheet — A short data sheet is an extract from a full data sheet Applications — Applications that are described herein for any of these
with the same product type number(s) and title. A short data sheet is products are for illustrative purposes only. NXP Semiconductors makes no
intended for quick reference only and should not be relied upon to contain representation or warranty that such applications will be suitable for the
detailed and full information. For detailed and full information see the specified use without further testing or modification.
relevant full data sheet, which is available on request via the local NXP
Customers are responsible for the design and operation of their
Semiconductors sales office. In case of any inconsistency or conflict with the
applications and products using NXP Semiconductors products, and NXP
short data sheet, the full data sheet shall prevail.
Semiconductors accepts no liability for any assistance with applications or
customer product design. It is customer’s sole responsibility to determine
Product specification — The information and data provided in a Product whether the NXP Semiconductors product is suitable and fit for the
data sheet shall define the specification of the product as agreed between customer’s applications and products planned, as well as for the planned
NXP Semiconductors and its customer, unless NXP Semiconductors and application and use of customer’s third party customer(s). Customers should
customer have explicitly agreed otherwise in writing. In no event however, provide appropriate design and operating safeguards to minimize the risks
shall an agreement be valid in which the NXP Semiconductors product associated with their applications and products.
is deemed to offer functions and qualities beyond those described in the
NXP Semiconductors does not accept any liability related to any default,
Product data sheet.
damage, costs or problem which is based on any weakness or default
in the customer’s applications or products, or the application or use by
customer’s third party customer(s). Customer is responsible for doing all
Disclaimers necessary testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications
Limited warranty and liability — Information in this document is believed and the products or of the application or use by customer’s third party
to be accurate and reliable. However, NXP Semiconductors does not give customer(s). NXP does not accept any liability in this respect.
any representations or warranties, expressed or implied, as to the accuracy
or completeness of such information and shall have no liability for the Limiting values — Stress above one or more limiting values (as defined in
consequences of use of such information. NXP Semiconductors takes no the Absolute Maximum Ratings System of IEC 60134) will cause permanent
responsibility for the content in this document if provided by an information damage to the device. Limiting values are stress ratings only and (proper)
source outside of NXP Semiconductors. operation of the device at these or any other conditions above those
In no event shall NXP Semiconductors be liable for any indirect, incidental, given in the Recommended operating conditions section (if present) or the
punitive, special or consequential damages (including - without limitation - Characteristics sections of this document is not warranted. Constant or
lost profits, lost savings, business interruption, costs related to the removal repeated exposure to limiting values will permanently and irreversibly affect
or replacement of any products or rework charges) whether or not such the quality and reliability of the device.
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory. Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
Notwithstanding any damages that customer might incur for any reason
sale, as published at https://www.nxp.com/profile/terms, unless otherwise
whatsoever, NXP Semiconductors’ aggregate and cumulative liability
agreed in a valid written individual agreement. In case an individual
towards customer for the products described herein shall be limited in
agreement is concluded only the terms and conditions of the respective
accordance with the Terms and conditions of commercial sale of NXP
agreement shall apply. NXP Semiconductors hereby expressly objects to
Semiconductors.
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Right to make changes — NXP Semiconductors reserves the right to
make changes to information published in this document, including without
No offer to sell or license — Nothing in this document may be interpreted
limitation specifications and product descriptions, at any time and without
or construed as an offer to sell products that is open for acceptance or
notice. This document supersedes and replaces all information supplied prior
the grant, conveyance or implication of any license under any copyrights,
to the publication hereof.
patents or other industrial or intellectual property rights.
PN7150 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Product data sheet Rev. 4.2 — 2 February 2024

64 / 69
NXP Semiconductors
PN7150
High performance NFC controller with integrated firmware, supporting all NFC Forum modes

Quick reference data — The Quick reference data is an extract of the NXP B.V. — NXP B.V. is not an operating company and it does not distribute
product data given in the Limiting values and Characteristics sections of this or sell products.
document, and as such is not complete, exhaustive or legally binding.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior
Licenses
authorization from competent authorities.
Purchase of NXP ICs with NFC technology — Purchase of an NXP
Suitability for use in non-automotive qualified products — Unless Semiconductors IC that complies with one of the Near Field Communication
this document expressly states that this specific NXP Semiconductors (NFC) standards ISO/IEC 18092 and ISO/IEC 21481 does not convey an
product is automotive qualified, the product is not suitable for automotive implied license under any patent right infringed by implementation of any of
use. It is neither qualified nor tested in accordance with automotive testing those standards. Purchase of NXP Semiconductors IC does not include a
or application requirements. NXP Semiconductors accepts no liability for license to any NXP patent (or other IP right) covering combinations of those
inclusion and/or use of non-automotive qualified products in automotive products with other products, whether hardware or software.
equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, Trademarks
customer (a) shall use the product without NXP Semiconductors’ warranty
of the product for such automotive applications, use and specifications, and Notice: All referenced brands, product names, service names, and
(b) whenever customer uses the product for automotive applications beyond trademarks are the property of their respective owners.
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any NXP — wordmark and logo are trademarks of NXP B.V.
liability, damages or failed product claims resulting from customer design and AMBA, Arm, Arm7, Arm7TDMI, Arm9, Arm11, Artisan, big.LITTLE,
use of the product for automotive applications beyond NXP Semiconductors’ Cordio, CoreLink, CoreSight, Cortex, DesignStart, DynamIQ, Jazelle,
standard warranty and NXP Semiconductors’ product specifications. Keil, Mali, Mbed, Mbed Enabled, NEON, POP, RealView, SecurCore,
Socrates, Thumb, TrustZone, ULINK, ULINK2, ULINK-ME, ULINK-
Translations — A non-English (translated) version of a document, including PLUS, ULINKpro, μVision, Versatile — are trademarks and/or registered
the legal information in that document, is for reference only. The English trademarks of Arm Limited (or its subsidiaries or affiliates) in the US and/or
version shall prevail in case of any discrepancy between the translated and elsewhere. The related technology may be protected by any or all of patents,
English versions. copyrights, designs and trade secrets. All rights reserved.
DESFire — is a trademark of NXP B.V.
Security — Customer understands that all NXP products may be subject to
FeliCa — is a trademark of Sony Corporation.
unidentified vulnerabilities or may support established security standards or
specifications with known limitations. Customer is responsible for the design ICODE and I-CODE — are trademarks of NXP B.V.
and operation of its applications and products throughout their lifecycles I2C-bus — logo is a trademark of NXP B.V.
to reduce the effect of these vulnerabilities on customer’s applications
and products. Customer’s responsibility also extends to other open and/or MIFARE — is a trademark of NXP B.V.
proprietary technologies supported by NXP products for use in customer’s MIFARE Classic — is a trademark of NXP B.V.
applications. NXP accepts no liability for any vulnerability. Customer should MIFARE Ultralight — is a trademark of NXP B.V.
regularly check security updates from NXP and follow up appropriately.
Customer shall select products with security features that best meet rules,
regulations, and standards of the intended application and make the
ultimate design decisions regarding its products and is solely responsible
for compliance with all legal, regulatory, and security related requirements
concerning its products, regardless of any information or support that may be
provided by NXP.
NXP has a Product Security Incident Response Team (PSIRT) (reachable
at PSIRT@nxp.com) that manages the investigation, reporting, and solution
release to security vulnerabilities of NXP products.

Product data sheet Rev. 4.2 — 2 February 2024

65 / 69
NXP Semiconductors
PN7150
High performance NFC controller with integrated firmware, supporting all NFC Forum modes

Tables
Tab. 1. Quick reference data .........................................5 Tab. 26. Operating conditions ....................................... 44
Tab. 2. Ordering information ..........................................7 Tab. 27. Thermal characteristics ................................... 45
Tab. 3. Marking codes ...................................................8 Tab. 28. Thermal characteristics ................................... 45
Tab. 4. WLCSP package marking (top view) .................9 Tab. 29. Current consumption characteristics for
Tab. 5. Pin description .................................................11 operating ambient temperature range ............. 46
Tab. 6. WLCSP package marking (top view) ...............13 Tab. 30. Battery voltage monitor characteristics ............46
Tab. 7. System power mode description ..................... 16 Tab. 31. Reset timing .................................................... 46
Tab. 8. System power modes configuration ................ 17 Tab. 32. Power-up timings ............................................ 46
Tab. 9. System power mode descriptions ................... 17 Tab. 33. Power-down timings ........................................ 47
Tab. 10. PN7150 power states ......................................18 Tab. 34. High-speed mode I2C-bus timings
Tab. 11. Functional modes in active state .....................19 specification .....................................................47
Tab. 12. Functionality for I2C-bus interface ...................22 Tab. 35. Fast mode I2C-bus timings specification .........48
Tab. 13. I2C-bus interface addressing .......................... 22 Tab. 36. Input clock characteristics on NFC_CLK_
Tab. 14. Crystal requirements ....................................... 23 XTAL1 when using PLL ...................................49
Tab. 15. PLL input requirements ................................... 24 Tab. 37. Pin characteristics for NFC_CLK_XTAL1
Tab. 16. Communication overview for ISO/IEC when PLL input ............................................... 49
14443 type A and read/write mode for Tab. 38. Pin characteristics for 27.12 MHz crystal
MIFARE Classic .............................................. 34 oscillator .......................................................... 49
Tab. 17. Overview for FeliCa Reader/ Tab. 39. PLL accuracy .................................................. 49
Writercommunication mode .............................35 Tab. 40. VEN input pin characteristics .......................... 50
Tab. 18. Overview for ISO/IEC 14443B Reader/ Tab. 41. pin characteristics for IRQ and CLK_REQ .......50
Writer communication mode ............................36 Tab. 42. Input pin characteristics for RXN and RXP ......51
Tab. 19. Communication overview for NFC forum Tab. 43. Output pin characteristics for TX1 and TX2 .....52
T5T R/W mode ................................................37 Tab. 44. Output resistance for TX1 and TX2 .................52
Tab. 20. Overview for Active communication mode .......39 Tab. 45. Input pin characteristics for I2CADR0 and
Tab. 21. Overview for passive communication mode .... 40 I2CADR1 ......................................................... 52
Tab. 22. Overview for NFC forum T4T, ISO/IEC Tab. 46. Pin characteristics for I2CSDA and I2CSCL ....53
14443A card mode ..........................................41 Tab. 47. Electrical characteristic of VDD ....................... 53
Tab. 23. Overview for NFC forum T4T, ISO/IEC Tab. 48. SnPb eutectic process (from J-STD-020D) ..... 57
14443B card mode ..........................................42 Tab. 49. Lead-free process (from J-STD-020D) ............ 57
Tab. 24. Overview for NFC forum T3T, Sony FeliCa Tab. 50. Abbreviations ...................................................59
card mode ....................................................... 42 Tab. 51. Revision history ...............................................62
Tab. 25. Limiting values ................................................ 43

Product data sheet Rev. 4.2 — 2 February 2024

66 / 69
NXP Semiconductors
PN7150
High performance NFC controller with integrated firmware, supporting all NFC Forum modes

Figures
Fig. 1. PN7150 transmission modes ............................ 2 Fig. 20. Battery voltage monitor principle ..................... 29
Fig. 2. PN7150 package marking HVQFN40 (top Fig. 21. Resetting PN7150 via VEN pin ....................... 30
view) 4 lines ...................................................... 8 Fig. 22. VBAT is set up before VDD(PAD) ................... 31
Fig. 3. PN7150 package marking HVQFN40 (top Fig. 23. VDD(PAD) and VBAT are set up at the
view) 3 lines ...................................................... 8 same time ........................................................31
Fig. 4. PN7150 package marking WLCSP42 (top Fig. 24. VDD(PAD) is set up or cut-off after PN7150
view) .................................................................. 9 has been enabled ........................................... 32
Fig. 5. PN7150 block diagram ....................................10 Fig. 25. Power-down sequence ....................................32
Fig. 6. Pinning .............................................................11 Fig. 26. Read/write mode for ISO/IEC 14443 type A
Fig. 7. WLCSP42 pinning (bottom view) .................... 13 and read/write mode for MIFARE Classic ........34
Fig. 8. PN7150 connection ......................................... 15 Fig. 27. FeliCa Reader/Writer communication mode
Fig. 9. System power mode diagram ......................... 16 diagram ............................................................35
Fig. 10. Polling loop: all phases enabled ......................20 Fig. 28. ISO/IEC 14443B Reader/Writer
Fig. 11. Polling loop: low-power RF polling .................. 21 communication mode diagram ........................ 36
Fig. 12. 27.12 MHz crystal oscillator connection .......... 23 Fig. 29. R/W mode for NFC forum T5T
Fig. 13. Input reference phase noise characteristics .... 24 communication diagram .................................. 37
Fig. 14. PMU functional diagram ..................................25 Fig. 30. FNFCIP-1 communication mode ..................... 38
Fig. 15. VBAT1 = VBAT2 (between 2.3 V and 5.5 V) ....26 Fig. 31. Active communication mode ........................... 39
Fig. 16. VDD(TX) offset behavior ................................. 27 Fig. 32. Passive communication mode .........................40
Fig. 17. VDD(TX) behavior when PN7150 is in Fig. 33. I2C-bus timings ............................................... 47
Standby state .................................................. 27 Fig. 34. Package outline, HVQFN40, SOT618-1,
Fig. 18. VBAT1 = 5 V, VBAT2 between 2.3 V and MSL3 ............................................................... 54
5.5 V ................................................................28 Fig. 35. Package outline, WLCSP42, SOT1459-1 ........55
Fig. 19. VDD(TX) behavior when PN7150 is supply Fig. 36. Temperature profiles for large and small
using external supply on VBAT1 ..................... 28 components ..................................................... 58

Product data sheet Rev. 4.2 — 2 February 2024

67 / 69
NXP Semiconductors
PN7150
High performance NFC controller with integrated firmware, supporting all NFC Forum modes

Contents
1 Introduction ...................................................... 1 12.7 Contactless interface unit ................................ 32
2 General description ......................................... 2 12.7.1 Reader/Writer communication modes ..............33
3 Features and benefits ..................................... 3 12.7.1.1 Communication mode for ISO/IEC 14443
4 Applications ..................................................... 4 type A, MIFARE Classic and Jewel/Topaz
5 Quick reference data ....................................... 5 PCD ................................................................. 34
6 Versions ............................................................ 6 12.7.1.2 FeliCa PCD communication mode ...................35
6.1 Version C11006 ................................................. 6 12.7.1.3 ISO/IEC 14443B PCD communication
6.2 Version C11004 ................................................. 6 mode ................................................................ 36
6.3 Version C11002 ................................................. 6 12.7.1.4 R/W mode for NFC forum Type 5 Tag ............. 37
7 Ordering information .......................................7 12.7.2 ISO/IEC 18092, Ecma 340 NFCIP-1
8 Marking HVQFN40 ........................................... 8 communication modes .....................................38
9 Marking WLCSP42 ........................................... 9 12.7.2.1 ACTIVE communication mode .........................39
10 Block diagram ................................................ 10 12.7.2.2 Passive communication mode ......................... 40
11 Pinning information .......................................11 12.7.2.3 NFCIP-1 framing and coding ........................... 41
11.1 Pinning HVQFN40 ........................................... 11 12.7.2.4 NFCIP-1 protocol support ................................41
11.2 Pinning WLCSP42 ........................................... 13 12.7.3 Card communication modes ............................ 41
12 Functional description .................................. 15 12.7.3.1 NFC forum T4T, ISO/IEC 14443Acard
12.1 System modes .................................................16 mode ................................................................ 41
12.1.1 System power modes ...................................... 16 12.7.3.2 NFC forum T4T, ISO/IEC 14443B card
12.1.2 PN7150 power states ...................................... 18 mode ................................................................ 42
12.1.2.1 Monitor state ....................................................18 12.7.3.3 NFC forum T3T, Sony FeliCa card mode .........42
12.1.2.2 Hard Power Down (HPD) state ........................18 12.7.4 Frequency interoperability ............................... 42
12.1.2.3 Standby state ...................................................19 13 Limiting values ...............................................43
12.1.2.4 Active state ...................................................... 19 14 Recommended operating conditions ...........44
12.1.2.5 Polling loop ...................................................... 20 15 Thermal characteristics ................................ 45
12.2 Microcontroller ................................................. 21 15.1 Thermal characteristics HVQFN40 .................. 45
12.3 Host interface .................................................. 21 15.2 Thermal characteristics WLCSP42 .................. 45
12.3.1 I2C-bus interface ............................................. 22 16 Characteristics ............................................... 46
12.3.1.1 I2C-bus configuration .......................................22 16.1 Current consumption characteristics ................46
12.4 PN7150 clock concept .....................................23 16.2 Functional block electrical characteristics ........ 46
12.4.1 27.12 MHz quartz oscillator ............................. 23 16.2.1 Battery voltage monitor characteristics ............ 46
12.4.2 Integrated PLL to make use of external 16.2.2 Reset via VEN ................................................. 46
clock .................................................................24 16.2.3 Power-up timings ............................................. 46
12.4.3 Low-power 40 MHz ± 2.5 % oscillator ............. 25 16.2.4 Power-down timings ........................................ 47
12.4.4 Low-power 380 kHz oscillator ..........................25 16.2.5 I2C-bus timings ................................................47
12.5 Power concept .................................................25 16.3 Pin characteristics ............................................49
12.5.1 PMU functional description .............................. 25 16.3.1 NFC_CLK_XTAL1 and NFC_CLK_XTAL2
12.5.2 DSLDO: dual supply LDO ............................... 26 pins characteristics .......................................... 49
12.5.3 TXLDO ............................................................. 26 16.3.2 VEN input pin characteristics ...........................50
12.5.3.1 Configuration 1: supply connection in case 16.3.3 Pin characteristics for IRQ and CLK_REQ .......50
the battery is used to generate RF field ...........26 16.3.4 Input pin characteristics for RXN and RXP ...... 51
12.5.3.2 Configuration 2: supply connection in case 16.3.5 Output pin characteristics for TX1 and TX2 ..... 52
a 5 V supply is used to generate RF field 16.3.6 Input pin characteristics for I2CADR0 and
with the use of TXLDO .................................... 28 I2CADR1 ..........................................................52
12.5.3.3 TXLDO limiter .................................................. 28 16.3.7 Pin characteristics for I2CSDA and I2CSCL .... 53
12.5.4 Battery voltage monitor ....................................29 16.3.8 VDD pin characteristic ..................................... 53
12.6 Reset concept ..................................................30 17 Package outline ............................................. 54
12.6.1 Resetting PN7150 ............................................30 17.1 Package outline HVQFN40 ..............................54
12.6.2 Power-up sequences ....................................... 31 17.2 Package outline WLCSP42 ............................. 55
12.6.2.1 VBAT is set up before VDD(PAD) ....................31 18 Soldering of SMD packages ......................... 56
12.6.2.2 VDD(PAD) and VBAT are set up in the 18.1 Introduction to soldering .................................. 56
same time ........................................................ 31 18.2 Wave and reflow soldering .............................. 56
12.6.2.3 PN7150 has been enabled before 18.3 Wave soldering ................................................ 56
VDD(PAD) is set up or before VDD(PAD) 18.4 Reflow soldering .............................................. 57
has been cut off ...............................................32 19 Abbreviations ................................................. 59
12.6.3 Power-down sequence .................................... 32 20 References ......................................................61
PN7150 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Product data sheet Rev. 4.2 — 2 February 2024

68 / 69
NXP Semiconductors
PN7150
High performance NFC controller with integrated firmware, supporting all NFC Forum modes

21 Revision history .............................................62

Legal information ...........................................64

Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section 'Legal information'.

For more information, please visit: https://www.nxp.com
Date of release: 2 February 2024
Document identifier: PN7150

PN5190B2
No ratings yet
PN5190B2
332 pages
NFC Technology and Applications: Definitive Reference for Developers and Engineers
From Everand
NFC Technology and Applications: Definitive Reference for Developers and Engineers
Richard Johnson
No ratings yet
PN5190
No ratings yet
PN5190
355 pages
MF0ICU2
No ratings yet
MF0ICU2
37 pages
Mastering eBPF: From Networking to Security in the Linux Kernel
From Everand
Mastering eBPF: From Networking to Security in the Linux Kernel
Robert Johnson
No ratings yet
Circuito Integrado st25dv04kch
No ratings yet
Circuito Integrado st25dv04kch
201 pages
Mcxnx4X: 32-Bit Arm Cortex-M33 at 150 MHZ (N94X and N54X)
No ratings yet
Mcxnx4X: 32-Bit Arm Cortex-M33 at 150 MHZ (N94X and N54X)
139 pages
230D6 - Low Standby Power High Performance PWM Controller
No ratings yet
230D6 - Low Standby Power High Performance PWM Controller
21 pages
TP PN7160 Next Gen NFC Controller
No ratings yet
TP PN7160 Next Gen NFC Controller
25 pages
Amf Aut t3403
No ratings yet
Amf Aut t3403
21 pages
RN 00280
No ratings yet
RN 00280
12 pages
ISC NRF52832 A Datasheet-1
No ratings yet
ISC NRF52832 A Datasheet-1
22 pages
ST 25 DV 64 KC
No ratings yet
ST 25 DV 64 KC
202 pages
NRF7002 DK User Guide v0.7.2
No ratings yet
NRF7002 DK User Guide v0.7.2
45 pages
m24sr02 Y-1696501
No ratings yet
m24sr02 Y-1696501
89 pages
NTP53x2 - NTAG 5 Link - 544533 - Rev33
No ratings yet
NTP53x2 - NTAG 5 Link - 544533 - Rev33
133 pages
PN532
No ratings yet
PN532
27 pages
MFRC631
No ratings yet
MFRC631
143 pages
Infineon SAKCIC751 DS v01 - 03 en 748992
No ratings yet
Infineon SAKCIC751 DS v01 - 03 en 748992
39 pages
nRF52840 - OPS - v0.5 - Kopija
No ratings yet
nRF52840 - OPS - v0.5 - Kopija
696 pages
FTF-InS-N2040 Future Electronics-NFC A Closer Look
No ratings yet
FTF-InS-N2040 Future Electronics-NFC A Closer Look
37 pages
CR95HF
No ratings yet
CR95HF
72 pages
CR95HF Datasheet
No ratings yet
CR95HF Datasheet
63 pages
KTU-S5 To S8-draftsyllabus-CIVILENGG-Final PDF
No ratings yet
KTU-S5 To S8-draftsyllabus-CIVILENGG-Final PDF
130 pages
AN11203 - Use of PWM, GPIO and Event Detection
No ratings yet
AN11203 - Use of PWM, GPIO and Event Detection
49 pages
Dalmatiaquarnero01jackson PDF
No ratings yet
Dalmatiaquarnero01jackson PDF
488 pages
UACE 475 Submath Paper 1 2016
No ratings yet
UACE 475 Submath Paper 1 2016
14 pages
LPC2470
No ratings yet
LPC2470
91 pages
PN7462
No ratings yet
PN7462
108 pages
NCP5230 D
No ratings yet
NCP5230 D
13 pages
PTN5100
No ratings yet
PTN5100
53 pages
NCV7381 FlexRay Transceiver
No ratings yet
NCV7381 FlexRay Transceiver
24 pages
DESADV
No ratings yet
DESADV
66 pages
Update DLL g10 Kitchenn 101
No ratings yet
Update DLL g10 Kitchenn 101
3 pages
NanoBeacon Config Tool User Guide EN
No ratings yet
NanoBeacon Config Tool User Guide EN
52 pages
NCX3340
No ratings yet
NCX3340
2 pages
AN11697
No ratings yet
AN11697
24 pages
Car Key Programming Guide
From Everand
Car Key Programming Guide
Rodulf nouh Fidal
No ratings yet
ISL3152E Renesas
No ratings yet
ISL3152E Renesas
36 pages
32-Bit ARM Cortex-M0+ Microcontroller
No ratings yet
32-Bit ARM Cortex-M0+ Microcontroller
39 pages
AN12368 - NTAG 5 Link - I2C Master Mode
No ratings yet
AN12368 - NTAG 5 Link - I2C Master Mode
17 pages
MF0ICU2
No ratings yet
MF0ICU2
36 pages
MIFARE Ultralight C
No ratings yet
MIFARE Ultralight C
15 pages
TN2115s2-SpecV1.05 Public
No ratings yet
TN2115s2-SpecV1.05 Public
10 pages
AN1425
No ratings yet
AN1425
25 pages
Using The PN5180 Without Library: Rev. 1.0 - 7 January 2020 Application Note 581710 Company Public
No ratings yet
Using The PN5180 Without Library: Rev. 1.0 - 7 January 2020 Application Note 581710 Company Public
20 pages
UltraLight C MF0ICU2
No ratings yet
UltraLight C MF0ICU2
43 pages
NFC Reader Design - How To Build Your Own Reader
No ratings yet
NFC Reader Design - How To Build Your Own Reader
42 pages
Semi - Detailed DLL For Problems Involving Rational Functions
100% (2)
Semi - Detailed DLL For Problems Involving Rational Functions
3 pages
N1404W NXP SW Libraries For NFC Readers - Introduction v1.0 Public
No ratings yet
N1404W NXP SW Libraries For NFC Readers - Introduction v1.0 Public
39 pages
Module 1-Ie
No ratings yet
Module 1-Ie
54 pages
Data Sheet
No ratings yet
Data Sheet
32 pages
NCP1271 Soft-Skipt Mode Standby PWM Controller With Adjustable Skip Level and External Latch
No ratings yet
NCP1271 Soft-Skipt Mode Standby PWM Controller With Adjustable Skip Level and External Latch
20 pages
Cbse Class 10 Science Assertion - Reason Questions For Term 2 Exam 2022
0% (1)
Cbse Class 10 Science Assertion - Reason Questions For Term 2 Exam 2022
2 pages
M.Tech. (AR16) Regulations Curriculum&Syllabi PDF
No ratings yet
M.Tech. (AR16) Regulations Curriculum&Syllabi PDF
198 pages
PR5331C3HN: 1. General Description
No ratings yet
PR5331C3HN: 1. General Description
33 pages
CRN120 SDS
No ratings yet
CRN120 SDS
15 pages
MF1S70YYX - V1: 1 General Description
No ratings yet
MF1S70YYX - V1: 1 General Description
37 pages
J CB Backhoe Loader 3CX: Static Dimensions
100% (1)
J CB Backhoe Loader 3CX: Static Dimensions
7 pages
Analytical Chemistry
No ratings yet
Analytical Chemistry
7 pages
Mf1S70Yyx/V1: 1. General Description
No ratings yet
Mf1S70Yyx/V1: 1. General Description
41 pages
PN532C1
No ratings yet
PN532C1
25 pages
BFU760F: 1. Product Profile
No ratings yet
BFU760F: 1. Product Profile
12 pages
MCF51EM256
No ratings yet
MCF51EM256
54 pages
Mf1s50yyx V1 PDF
No ratings yet
Mf1s50yyx V1 PDF
36 pages
Developing An ICT Project
No ratings yet
Developing An ICT Project
26 pages
Python Programming Examples
No ratings yet
Python Programming Examples
19 pages
Emami
100% (1)
Emami
39 pages
R1 002b Product Overview
No ratings yet
R1 002b Product Overview
22 pages
NCP5230 ONSemiconductor
No ratings yet
NCP5230 ONSemiconductor
12 pages
21 Pouces 2008 Alfa Romeo 159 3.2 JTS V6 20V Q4 Ti Tire Sizes (Since Mid-Year 2008 For Europe Australia)
No ratings yet
21 Pouces 2008 Alfa Romeo 159 3.2 JTS V6 20V Q4 Ti Tire Sizes (Since Mid-Year 2008 For Europe Australia)
4 pages
Data Sheet: PNP 5 GHZ Wideband Transistor
No ratings yet
Data Sheet: PNP 5 GHZ Wideband Transistor
10 pages
Integers - DHA 01 - Junoon 2025
No ratings yet
Integers - DHA 01 - Junoon 2025
4 pages
DS Module 4 Trees
No ratings yet
DS Module 4 Trees
21 pages
English: Sequencing and Narrating Events in Personal or Factual Recounts
83% (6)
English: Sequencing and Narrating Events in Personal or Factual Recounts
24 pages
Grade 2 Story Writing Worksheet 2
100% (1)
Grade 2 Story Writing Worksheet 2
21 pages
NCP1230 D
No ratings yet
NCP1230 D
21 pages
Industry-Leading, 2 - Generation NFC Controller: NXP NFC Controller PN544 For Mobile Phones and Portable Equipment
No ratings yet
Industry-Leading, 2 - Generation NFC Controller: NXP NFC Controller PN544 For Mobile Phones and Portable Equipment
4 pages
Easy Way - Get France Schengen Visa in 7 Days
No ratings yet
Easy Way - Get France Schengen Visa in 7 Days
7 pages
How To Download YouTube Shorts On Laptop
100% (1)
How To Download YouTube Shorts On Laptop
3 pages
Wheels: Automotive Engineering Y. Samim ÜNLÜSOY, Kerem Bayar
No ratings yet
Wheels: Automotive Engineering Y. Samim ÜNLÜSOY, Kerem Bayar
9 pages
Vidmate App
No ratings yet
Vidmate App
11 pages
NXP NFC and Contactless Reader Solutions
No ratings yet
NXP NFC and Contactless Reader Solutions
3 pages
Entrep 101 Q1 Reviewer
No ratings yet
Entrep 101 Q1 Reviewer
5 pages
Piagetian Lesson Plan
No ratings yet
Piagetian Lesson Plan
6 pages
Benefits To Startups by Indian Government
No ratings yet
Benefits To Startups by Indian Government
4 pages
CE 335 Practice Exam
No ratings yet
CE 335 Practice Exam
4 pages
Well Integrity
No ratings yet
Well Integrity
2 pages
2015 FIGO CONSENSUS GUIDELINES ON INTRAPARTUM FETAL MONITORING - PPT Video Online Download
No ratings yet
2015 FIGO CONSENSUS GUIDELINES ON INTRAPARTUM FETAL MONITORING - PPT Video Online Download
1 page
Spanish Lesson Plan Week 12
No ratings yet
Spanish Lesson Plan Week 12
1 page

Note: This service is not intended for secure transactions such as banking, social media, email, or purchasing. Use at your own risk. We assume no liability whatsoever for broken pages.