EDA SET 221

Lec 03 Static Combinational Logic

Dr Mayar Ali
 MOSFET
❑ MOSFET: Metal Oxide Semiconductor Field Effect Transistor
❑ Four terminals: gate, source, drain, body (bulk)
❑ NMOS body is usually tied to the lowest potential (VSS, ground, 0V)
❑ PMOS body is usually tied to the highest potential (VDD, power)
▪ VDD is scaled down: 5, 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, …
❑ The gate controls the flow of current between the source and drain

03: Basic CMOS Circuits 2

 Transistor as a Switch
❑ NMOS
▪ Gate HIGH: Switch closed (ON)
▪ Gate LOW: Switch open (OFF)
❑ PMOS
▪ Gate LOW: Switch closed (ON)
▪ Gate HIGH: Switch open (OFF)

03: Basic CMOS Circuits 3

 CMOS Inverter
❑ Ideally, there is no static (idle) power consumption

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Combinational vs. Sequential Logic

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 Static CMOS Circuit
⚫ At every point in time (except during the switching transients)
each gate output is connected to either VDD or VSS via a low-
resistive path.

⚫ The outputs of the gates assume at all times the value of the Boolean
function, implemented by the circuit (ignoring, once again, the
transient effects during switching periods).

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 Static Complementary CMOS

VDD • Properties
• Rail-to-rail swing
In1 • Non-ratioed logic
PMOS only
In2 PUN
• Zero (very low) static
InN power
F(In1,In2,…InN)
In1
In2 PDN
NMOS only
InN

PUN and PDN are dual logic networks

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Series/Parallel NMOS Connection

Transistors can be thought as a switch controlled by its gate signal

NMOS switch closes when switch control input is high
A B

X Y Y = X if A and B

X B Y = X if A OR B
Y

NMOS Transistors pass a “strong” 0 but a “weak” 1

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 Series/Parallel PMOS Connection

PMOS switch closes when switch control input is low

A B

X Y Y = X if A AND B = A + B

X B Y = X if A OR B = AB
Y

PMOS Transistors pass a “strong” 1 but a “weak” 0

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 CMOS NAND Gate
❑ Rule of Conduction Complements
▪ Pull-up network is complement of pull-down
▪ Parallel -> series, series -> parallel

PDN PUN

Bubble pushing with

DeMorgan’s law

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 Synthesize of CMOS digital circuit
In order to synthesize or implement a CMOS digital circuit for logic functions using CMOS
transistors. You have to follow these steps.

1 Simplify the function by Boolean algebra or K-map

2 Get F̅ by collecting “0” as a form of sum of product (SOP)
3 Firstly, draw the pull-down network by using n-channel
E-MOSFET.

1. Any dot term will be drawn as series connection. Ex, A

F̅ =A.B A B
2. Any sum term will be drawn as parallel connection. B
Ex. F̅ =A+B

Vice versa
A
A B
4 Secondly, draw the pull-up network using p-channel E-
B
MOSFET.
dot term
Sum term
1. Parallel connection is converted into series connection.
2. Series connection is converted into parallel connection
 CMOS NOR Gate
❑ Rule of Conduction Complements
▪ Pull-up network is complement of pull-down
▪ Parallel -> series, series -> parallel

PDN PUN

Bubble pushing with

DeMorgan’s law

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 CMOS 4-Input NOR Gate Circuit

If one or more of the inputs = 1

The output = 0 (pull down)
Otherwise: output = 1 (pull up)

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 CMOS Complex Gate (1)
How to get the complex logic
expression Y=f(A,B,C,D)?
PU
1. Forget about the PU transistors
2. Consider the PD transistors (NMOS) (pull up PMOSFETs)
3. Series connected MOS  ANDing*
4. Parallel connected MOS  ORing*
5. Find the SOP (Sum Of Product)
6. Put the “complement” PU PMOSFETs
7. Negate the SOP expression to get Y

* ANDing = logic multiplication or product

* ORing = logic summation

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 CMOS Complex Gate (2)

How to get the complex logic

expression Y=f(A,B,C,D)? PU
(pull up PMOSFETs)
Notice:
QA is in series with 2 parallel branches
 A (? + ?)
One branch = QB
2nd branch = QC in series with QD
 A(B+CD)
Don’t forget to negate what you get:
Y=A(B+CD)

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 CMOS Complex Gate (3)

How to get the complex logic

expression Y=f(A,B,C,D)?
PU network = complement of the PD network:
Complement of a series connection = parallel
Complement of a parallel connection = series

Note that CMOS gates give negated output

by nature of its construction.
For example to get Y=A(B+CD) we’ve to put
an inverter after the output shown in this example.

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 AND-OR-INVERT-22 (AOI22)
❑ An example of a complex logic function in a single stage (8 Ts)

❑ The wrong way of doing it (20 Ts)

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Synthesize of CMOS digital circuit
Synthesize of CMOS digital circuit
Synthesize of CMOS digital circuit
Synthesize of CMOS digital circuit
Synthesize of CMOS digital circuit
Synthesize of CMOS digital circuit
Synthesize of CMOS digital circuit
Synthesize of CMOS digital circuit
 Quiz
❑ What is the name of this gate?
(a) AOI31 (b) OAI33 (c) OAI31

A
B
C D
Y
D
A B C

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 Thank you!

03: Basic CMOS Circuits 27