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SYSTEM VERILOG
OPERATORS: A
COMPREHENSIVE GUIDE
Niranjana R December 3, 2023

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System Verilog operators: is a hardware

description language used in the development
and verification of digital circuits and systems.
Similar to other programming languages, it has
a set of operators that allow designers to
perform various operations on the data.
System Verilog operators are classified into
different categories based on their
functionality. Understanding these operators is
crucial for designing efficient and error-free
digital circuits.

The basic System Verilog operators include

arithmetic, relational, equality, logical, bitwise,
and shift operators. These operators are used
to perform basic mathematical and logical
operations, such as addition, subtraction,
multiplication, division, and comparison, and
logical operations like AND, OR, and NOT.
Advanced System Verilog operators include
reduction, concatenation, replication, and
streaming operators. These operators are
used to perform complex operations on large
data sets, such as data compression,
encryption, and decompression.

Table of Contents

Key Takeaways

System Verilog operators are used in

the development and verification of
digital circuits and systems.
Basic System Verilog operators include
arithmetic, relational, equality, logical,
bitwise, and shift operators.
Advanced System Verilog operators
include reduction, concatenation,
replication, and streaming operators.

Basic System Verilog

Operators

In System Verilog, operators are essential

building blocks for designing digital circuits.
These operators allow us to perform various
operations on digital data and manipulate it to
achieve the desired output. In this section, we
will discuss the three basic types of operators:
Arithmetic, Relational, and Logical.

Arithmetic Operators

Arithmetic operators are used to perform

mathematical operations on operands. The
basic arithmetic operators in System Verilog
are:

Operator Description

+ Addition

– Subtraction

* Multiplication

/ Division

% Modulus

For example, the expression a = b + c adds

the values of b and c and stores the result in a.

Relational Operators

Relational operators are used to compare two

operands. The result of a relational operator is
either true or false. The relational operators in
System Verilog are:

Operator Description

== Equal to

!= Not equal to

< Less than

<= Less than or equal to

> Greater than

>= Greater than or equal to

For example, the expression if (a == b)

compares the values of a and b and executes
the code inside the if statement if they are
equal.

Logical Operators

Logical operators are used to perform logical

operations on operands. The logical operators
in System Verilog are:

Operator Description

&& Logical AND

|| Logical OR

! Logical NOT

For example, the expression if (a && b) checks

if both a and b are true and executes the code
inside the if statement if they are.

Understanding these basic operators is

essential for designing digital circuits in
System Verilog. By using these operators, we
can perform various operations on digital data
and manipulate it to achieve the desired
output.

Advanced System Verilog

Operators

In addition to the basic operators, System

Verilog provides advanced operators to
perform complex operations. These operators
are an essential part of System Verilog and are
widely used in the development of digital
circuits. In this section, we will discuss two of
the most important advanced operators:
Bitwise Operators and Shift Operators.

Bitwise Operators

Bitwise operators are used to manipulate

individual bits of a variable. System Verilog
provides six bitwise operators: AND, OR,
XOR, NAND, NOR, and XNOR. These
operators can be used to perform various
operations such as masking, setting, and
clearing bits.

Operator Description Example

& Bitwise AND a&b

| Bitwise OR a|b

^ Bitwise XOR a^b

~& Bitwise NAND ~&a

~| Bitwise NOR ~|a

~^ Bitwise XNOR ~^a

Shift Operators

Shift operators are used to shift the bits of a

variable left or right. System Verilog provides
four shift operators: left shift, right shift,
arithmetic right shift, and logical right shift.
These operators are used to perform various
operations such as multiplication and division
by powers of two.

Operator Description Example

<< Left Shift a << b

>> Right Shift a >> b

>>> Logical Right Shift a >>> b

Arithmetic Right
>>$ a >>$ b
Shift

In summary, bitwise and shift operators are

essential in System Verilog for manipulating
individual bits and shifting bits left or right. By
using these advanced operators, we can
perform complex operations with ease and
efficiency.

Assignment Operators In
System Verilog

In System Verilog, we use assignment

operators to assign values to variables. The
most commonly used assignment operator is
the “=” operator. We use this operator to
assign a value to a variable. For example, if
we want to assign the value of 5 to a variable
named “a”, we would write “a = 5;”.

System Verilog also provides us with other

assignment operators that we can use to
perform certain operations on variables while
assigning values to them. These operators are
listed in the table below:

Operator Description

Adds the value on the right-hand

side to the value on the left-
+=
hand side and assigns the result
to the left-hand side variable.

Subtracts the value on the right-

hand side from the value on the
-= left-hand side and assigns the
result to the left-hand side
variable.

Multiplies the value on the right-

hand side with the value on the
*= left-hand side and assigns the
result to the left-hand side
variable.

Divide the value on the left-hand

side by the value on the right-
/=
hand side and assign the result
to the left-hand side variable.

Calculates the modulus of the

value on the left-hand side with
%= the value on the right-hand side
and assigns the result to the left-
hand side variable.

Shifts the bits of the left-hand

side value to the left by the
number of bits specified on the
<<=
right-hand side and assigns the
result to the left-hand side
variable.

Shifts the bits of the left-hand

side value to the right by the
number of bits specified on the
>>=
right-hand side and assigns the
result to the left-hand side
variable.

Performs a bitwise AND

operation between the left-hand
side value and the right-hand
&=
side value and assigns the
result to the left-hand side
variable.

Performs a bitwise XOR

operation between the left-hand
side value and the right-hand
^=
side value and assigns the
result to the left-hand side
variable.

Performs a bitwise OR operation

between the left-hand side value
|= and the right-hand side value
and assigns the result to the left-
hand side variable.

By using these assignment operators, we can

perform operations on variables and assign
the result to the same variable in a single
statement. This makes our code more concise
and easier to read.

Conditional Operators In
System Verilog

In System Verilog, conditional operators are

used to create conditional expressions. They
are a shorthand way to write if/else
statements. The conditional operator is also
known as the ternary operator because it takes
three operands. The syntax of the conditional
operator is as follows:

<condition> ? <expression_if_true> :
<expression_if_false>

The conditional operator evaluates the

condition first. If the condition is true, it
evaluates the expression immediately after the
question mark. If the condition is false, it
evaluates the expression immediately after the
colon.

One of the advantages of using the conditional

operator is that it makes the code more
concise and easier to read. It can also be used
in assignments, which can help reduce the
number of lines of code.

Another conditional operator in System Verilog

is the implication operator. The implication
operator is used to create logical implications.
It takes two operands and returns a Boolean
value. The syntax of the implication operator is
as follows:

<condition> |-> <expression>

The implication operator returns true if the

condition is false or if both the condition and
the expression are true. It returns false if the
condition is true and the expression is false.

In summary, System Verilog provides two

types of conditional operators: the conditional
operator and the implication operator. These
operators can help reduce the number of lines
of code and make the code more concise and
easier to read.

Miscellaneous Operators In
System Verilog

In addition to the basic arithmetic, relational,

and logical operators, System Verilog provides
several miscellaneous operators that can be
used in digital circuit design.

Replication Operator

The replication operator {} is used to replicate

a single value or a set of values multiple times.
The syntax for the replication operator is
{N{value}}, where N is the number of times the
value is replicated.

For example, {8{1’b0}} represents a vector of

eight bits, all set to 0. This operator is useful
when designing circuits that require a large
number of identical components.

Concatenation Operator

The concatenation operator {} is used to

concatenate two or more vectors into a single
vector. The syntax for the concatenation
operator is {vector1, vector2, …, vectorN},
where vector1 through vectorN are the vectors
being concatenated.

For example, {a, b} represents a vector that is

the concatenation of vectors a and b. This
operator is useful when designing circuits that
require combining multiple vectors into a single
vector.

Ternary Operator

The ternary operator ?: is a conditional

operator that is used to assign a value to a
variable based on a condition. The syntax for
the ternary operator is condition ? true_value :
false_value, where condition is the condition
being evaluated, true_value is the value
assigned if the condition is true, and
false_value is the value assigned if the
condition is false.

For example, y = (x>0) ? 1 : 0 assigns the

value 1 to y if x is greater than 0, and assigns
the value 0 to y if x is less than or equal to 0.
This operator is useful when designing circuits
that require conditional assignments.

Bit-Select And Part-

Select Operators

The bit-select operator [] and the part-select

operator [start:end] are used to select a single
bit or a range of bits from a vector,
respectively. The syntax for the bit-select
operator is vector[index], where vector is the
vector being selected from and index is the
index of the bit being selected. The syntax for
the part-select operator is vector[start:end],
where vector is the vector being selected from,
start is the index of the starting bit, and end is
the index of the ending bit.

For example, a[7:0] represents a vector that

consists of the eight least significant bits of
vector a. This operator is useful when
designing circuits that require selecting
specific bits or ranges of bits from a vector.

These operators, along with the basic

operators, provide a powerful set of tools for
designing digital circuits using System Verilog.

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