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Roadmap to Vlsi

The document outlines a roadmap for aspiring VLSI engineers, emphasizing the importance of mastering foundational topics such as Digital Electronics, Verilog, and Computer Architecture before specializing. It details the evolving hiring trends towards role-specific interviews and suggests practical projects to align with job roles. Additionally, it provides a structured approach to digital design, verification, and physical design, along with resources for further learning and practice.

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Shubham Akela
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29 views5 pages

Roadmap to Vlsi

The document outlines a roadmap for aspiring VLSI engineers, emphasizing the importance of mastering foundational topics such as Digital Electronics, Verilog, and Computer Architecture before specializing. It details the evolving hiring trends towards role-specific interviews and suggests practical projects to align with job roles. Additionally, it provides a structured approach to digital design, verification, and physical design, along with resources for further learning and practice.

Uploaded by

Shubham Akela
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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ROAD MAP to VLSI

Just watched a highly informative video offering a practical roadmap for aspiring VLSI engineers, aligning with
the significant shifts in hiring trends (more role-specific!). The core message: master the essentials first, then
specialize.
Hiring process in 2025:
• Transitioning from general hiring to role-specific interviews conducted by individual teams.
• Preparation strategy must evolve: build a strong foundation in common topics before diving deep into
a specific domain (Front-end or Back-end).

Essential Topics to Master (The Foundation is Key!)


• Digital Electronics: Fundamental for electronic devices. (Resources: Neso Academy (YT), Morris Mano
book)
• Verilog: Understand its translation to hardware. (Resources: Indranil S Gupta, Samir Palnitkar Book)
• CMOS: Basics for front-end, in-depth for back-end (NMOS/PMOS/Inverter characteristics).
(Resources: Prof. Janakiraman, Prof. Sudeb Dasgupta, Rabaey's book)
• Computer Architecture: Crucial for processor designing and understanding inner workings.
(Resources: Neso Academy, Prof. Smruti Ranjan Sarangi)
• Static Timing Analysis (STA): Focus on concepts, vital for exams/interviews. (Resources: Synopsys
guide, J. Bhaskar & R. Chadha book)
• C Programming: Essential for interacting with EDA tools, foundational. (Resources: Neso Academy,
GeeksforGeeks)
• Understanding Different Flows: Grasp the entire IC design flow and each stage's purpose (RTL-GDSII)
• Low Power Design Techniques: Increasingly important for smaller nodes. (Resource: Indranil S Gupta)
• Scripting: Add-on skill (Python, Perl, TCL) for data analysis and efficiency.
• Aptitude and Puzzles: Develop problem-solving skills and common sense. (Resources: Indiabix,
GeeksforGeeks)

Domain-Specific Topics (Choose Your Specialization)

• Front End:
o RTL Design: Build upon Digital, Verilog, STA, C, CDC. Focus on synthesizable code, power/area
optimization. Hands-on practice is critical.
o Verification: Core skill is Debugging. Requires Digital, Verilog/System Verilog, Computer Arch,
C/C++, UVM, FIFOs, protocols. Write test benches, learn OOP for System Verilog.
o Design for Test (DFT): Focuses on testing for manufacturing defects. Topics include Digital,
CDC, testability, test pattern generation. (Resource mentioned: NPTEL Indrasen Gupta)
• Back End: Includes Synthesis, Physical Design, Physical Verification.
o Essential: CMOS, STA, understanding the full backend flow.
o Master Clock Tree Synthesis (CTS). (References mentioned: VLSI Backend Adventure, Kavita
Sharma's book)

Projects are Crucial!

• Must align with the target job role.


• A project implementing the complete VLSI flow (RTL to GDS) is highly recommended for freshers.
• Open-source tools and project ideas are available (YouTube).
Building a strong foundation in the essential topics is more than half the battle. This structured approach can
make your VLSI preparation much more effective!
Digital Design
➢ LEVEL 1
• Implement Calculator – add, subtract, multiply, divide - Gate level modelling
• Multi bit Barrel shifter
• BCD counter with up and down counting.
➢ LEVEL 2
• Traffic light controller using FSM approach
• Vending machine/washing machine using FSM approach
• Synchronous FIFO
• Booth multiplier.
• Code converter using data path and control path properly. http://lnkiy.in/codeconverterpdf
➢ LEVEL 3
• RISC V – implementation of 5 staged pipelined RISC-V processor. Also implement hardware
detection if possible.
• MIPS – implementation of 5 staged pipelined MIPS Processor. Also implement hardware
detection if possible.
• Half precision floating point adder and multiplier

Design Verification
➢ LEVEL 1
• Write proper testbench to verify vending machine
➢ LEVEL 2
• Test bench for Synchronous FIFO
➢ LEVEL 3
• Do UVM verification for AXI interface
• Formal verification for RISC v processor.
• Half precision floating point adder and multiplier

Physical design
➢ LEVEL 1
o Take simple nand gate and implement its layout.
➢ LEVEL 2
o Take any wrapper from openroad Designs like swerv_wrapper, Do the Floorplaning and adjust
the
▪ PLACE_DENSITY = default
▪ PLACE_DENSITY = default – 40%
Analyse both the timings using OpenTime.
➢ LEVEL 3
a. RISC v processor – RTL to GDS
1. Do the floorplanning according to the hierarchy, have atleast 3 set of floor plans as experiments.
2. Analyse the placement (utilization andcongestion).
3. Spread out the design with differentplace_density.
4. At cts, analyse the clock structure and tryreducing the latency without effecting timingand skew.
5. Annalyse the timing in OpenTime (Do Sizing ,adding buffers)
6. Clean up drc and lvs on the experiment with best results.
Tools:
✓ RTL design/Verification– vivado or eda playground
✓ Synthesis – Yosys
✓ PnR – open road
✓ LVS – netgen
✓ Spice netlist simulation – ngspice
✓ OpenTime – Timing Analysis
✓ Design and characteristics analysis – cadence virtuoso.
✓ LTSpice

Verilog Task:
BEGINNER:
1. Multi bit Barrel shifter.
2. BCD counter with up and down counting.

INTERMEDIATE
1. Traffic light controller using FSM approach
2. Vending machine/washing machine using FSM aproach
3. Synchronous FIFO
4. Booth multiplier.
5. Code converter from binary to gray, bcd, xcess3 and vice versa using datapath and control
path properly.
Hint: for fsm, draw state diagram for different. Draw the
hardware for the fsm and then code it.

ADVANCED
1. MIPS – implementation of 5 staged pipelined MIPS Processor. Also implement hardware
detection (if possible).
2. Fixed point square root algorithm- fpga implementation.

Top-down approach (must for digital vlsi)


Design a full adder circuit in Verilog (hint: keep in mind that it should be synthesizable)
o Write a test bench covering all the possibility to verify it.
o Design the above circuit in c modelling (write its c code) and use it to verify your testbench outputs.
o Now, take a paper and draw the hardware for verified rtl code you have written.
o Try to minimize the area and power restructuring the design.
o Now code back the optimised design in Verilog. And again verify it with the c modelling outputs.
o Synthesize the final verified rtl code and implement the complete PnR flow. Generate its final
layout.
o Do the design rule check (DRC) and layout vs schematic (LVS) for thedesign.
Bottom – Up approach (must for analog and backend)
Design PMOS and NMOS, analyze all the characteristics of Mosfets
1) Id vs Vgs
2) Id vs Vds
3) Voltage transfer characteristics.
❖ By changing the load, compare all the above graphs
❖ Using the above pmos and nmos design a cmos inverter.
❖ Analyse all the graphs as above – for Cmos
❖ Now, design all the gates – AND, OR, NAND, NOR, XOR and XNOR by using your PMOS, NMOS and
CMOS.
❖ Analyse all the above characteristics for each gate.
❖ Take a capacitor as a output load and analyse the rise time (time the capacitor takes to charge) and
fall time (time taken by capacitor to discharge).
❖ After this analyse the logical efforts for these gates, specially compare nand and nor in terms of
speed and power.
❖ Now, design a half adder – for the best possible power and speed (based on the data you have
analysed above) using the gates designed above then design a full adder using the half adders.

ALL Resources:
Morris Mano: https://drive.google.com/file/d/1DOWGNJUsUFFikzIPkTd3L5rr7sHUOMFZ/view?usp=sharing

Digital Electronics:
https://youtube.com/playlist?list=PLBlnK6fEyqRjMH3mWf6kwqiTbT798eAOm&si=PmUeC_0e44zIaV64

Verilog: https://archive.nptel.ac.in/courses/106/105/106105165/

Verilog Samir Palnitkar book:


https://drive.google.com/file/d/1mZu0QvFu1TgbUXBvXbS5iB_ZIysqLH9D/view?usp=sharing

CMOS:

Digital IC Design:
https://youtube.com/playlist?list=PLdzewXO9j7ap_VF56OZUtj_LmWwJaYd7c&si=HPD76XJu8kA03jE5

CMOS Digital Desing:

https://youtube.com/playlist?list=PLLy_2iUCG87Bdulp9brz9AcvW_TnFCUmM&si=EOmfXcMhdp6mSGc8

BOOK: https://drive.google.com/file/d/1K0Oq_VxdHreXVqugcP5haEQrTgpVYyKP/view?usp=sharing

COA:

Neso : https://youtube.com/playlist?list=PLBlnK6fEyqRgLLlzdgiTUKULKJPYc0A4q&si=pNhcaAmgu1akgUw_

Prof. Smruti: https://youtube.com/playlist?list=PL1iLu2CSC9EWAo0ysorNI_nebwF6Rwkr0&si=2FB8L5d7uHQ2wyB2

STA:

Synopsys: https://www.synopsys.com/glossary/what-is-static-timing-analysis.html

FILES: https://drive.google.com/file/d/1zrV-asu0FfGnBZkR5m0m8C_W0qWPfBvW/view?usp=sharing
BOOK: https://drive.google.com/file/d/1wRUH9bKkBZoOlvtkT0JwxZ6IwwWAfNzP/view?usp=sharing

Flow:

https://teamvlsi.com/2020/05/asic-design-flow-overview-v1.html

Practice:

https://drive.google.com/file/d/1QzthlVR83zFYTIka9ZdL8EBNgbVQlBpL/view?usp=sharing

Project:

https://youtube.com/playlist?list=PL0E9jhuDlj9r-XIIgx5PPJpogx7ThS5CB&si=tAeDf-pqBTQMF54V

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