Roadmap to Vlsi
Roadmap to Vlsi
Just watched a highly informative video offering a practical roadmap for aspiring VLSI engineers, aligning with
the significant shifts in hiring trends (more role-specific!). The core message: master the essentials first, then
specialize.
Hiring process in 2025:
• Transitioning from general hiring to role-specific interviews conducted by individual teams.
• Preparation strategy must evolve: build a strong foundation in common topics before diving deep into
a specific domain (Front-end or Back-end).
• Front End:
o RTL Design: Build upon Digital, Verilog, STA, C, CDC. Focus on synthesizable code, power/area
optimization. Hands-on practice is critical.
o Verification: Core skill is Debugging. Requires Digital, Verilog/System Verilog, Computer Arch,
C/C++, UVM, FIFOs, protocols. Write test benches, learn OOP for System Verilog.
o Design for Test (DFT): Focuses on testing for manufacturing defects. Topics include Digital,
CDC, testability, test pattern generation. (Resource mentioned: NPTEL Indrasen Gupta)
• Back End: Includes Synthesis, Physical Design, Physical Verification.
o Essential: CMOS, STA, understanding the full backend flow.
o Master Clock Tree Synthesis (CTS). (References mentioned: VLSI Backend Adventure, Kavita
Sharma's book)
Design Verification
➢ LEVEL 1
• Write proper testbench to verify vending machine
➢ LEVEL 2
• Test bench for Synchronous FIFO
➢ LEVEL 3
• Do UVM verification for AXI interface
• Formal verification for RISC v processor.
• Half precision floating point adder and multiplier
Physical design
➢ LEVEL 1
o Take simple nand gate and implement its layout.
➢ LEVEL 2
o Take any wrapper from openroad Designs like swerv_wrapper, Do the Floorplaning and adjust
the
▪ PLACE_DENSITY = default
▪ PLACE_DENSITY = default – 40%
Analyse both the timings using OpenTime.
➢ LEVEL 3
a. RISC v processor – RTL to GDS
1. Do the floorplanning according to the hierarchy, have atleast 3 set of floor plans as experiments.
2. Analyse the placement (utilization andcongestion).
3. Spread out the design with differentplace_density.
4. At cts, analyse the clock structure and tryreducing the latency without effecting timingand skew.
5. Annalyse the timing in OpenTime (Do Sizing ,adding buffers)
6. Clean up drc and lvs on the experiment with best results.
Tools:
✓ RTL design/Verification– vivado or eda playground
✓ Synthesis – Yosys
✓ PnR – open road
✓ LVS – netgen
✓ Spice netlist simulation – ngspice
✓ OpenTime – Timing Analysis
✓ Design and characteristics analysis – cadence virtuoso.
✓ LTSpice
Verilog Task:
BEGINNER:
1. Multi bit Barrel shifter.
2. BCD counter with up and down counting.
INTERMEDIATE
1. Traffic light controller using FSM approach
2. Vending machine/washing machine using FSM aproach
3. Synchronous FIFO
4. Booth multiplier.
5. Code converter from binary to gray, bcd, xcess3 and vice versa using datapath and control
path properly.
Hint: for fsm, draw state diagram for different. Draw the
hardware for the fsm and then code it.
ADVANCED
1. MIPS – implementation of 5 staged pipelined MIPS Processor. Also implement hardware
detection (if possible).
2. Fixed point square root algorithm- fpga implementation.
ALL Resources:
Morris Mano: https://drive.google.com/file/d/1DOWGNJUsUFFikzIPkTd3L5rr7sHUOMFZ/view?usp=sharing
Digital Electronics:
https://youtube.com/playlist?list=PLBlnK6fEyqRjMH3mWf6kwqiTbT798eAOm&si=PmUeC_0e44zIaV64
Verilog: https://archive.nptel.ac.in/courses/106/105/106105165/
CMOS:
Digital IC Design:
https://youtube.com/playlist?list=PLdzewXO9j7ap_VF56OZUtj_LmWwJaYd7c&si=HPD76XJu8kA03jE5
https://youtube.com/playlist?list=PLLy_2iUCG87Bdulp9brz9AcvW_TnFCUmM&si=EOmfXcMhdp6mSGc8
BOOK: https://drive.google.com/file/d/1K0Oq_VxdHreXVqugcP5haEQrTgpVYyKP/view?usp=sharing
COA:
Neso : https://youtube.com/playlist?list=PLBlnK6fEyqRgLLlzdgiTUKULKJPYc0A4q&si=pNhcaAmgu1akgUw_
STA:
Synopsys: https://www.synopsys.com/glossary/what-is-static-timing-analysis.html
FILES: https://drive.google.com/file/d/1zrV-asu0FfGnBZkR5m0m8C_W0qWPfBvW/view?usp=sharing
BOOK: https://drive.google.com/file/d/1wRUH9bKkBZoOlvtkT0JwxZ6IwwWAfNzP/view?usp=sharing
Flow:
https://teamvlsi.com/2020/05/asic-design-flow-overview-v1.html
Practice:
https://drive.google.com/file/d/1QzthlVR83zFYTIka9ZdL8EBNgbVQlBpL/view?usp=sharing
Project:
https://youtube.com/playlist?list=PL0E9jhuDlj9r-XIIgx5PPJpogx7ThS5CB&si=tAeDf-pqBTQMF54V