Optimization of Sub-threshold Standard Cells for

Energy Efficient Designs

Abstract—Energy efficiency is a critical focus in contemporary The rest of the paper is structured as follows. Section
integrated circuit (IC) design, particularly for ultra-low-power II presents the design methodology, including logic design,
applications. Sub-threshold voltage scaling presents a promising optimization, layout design, and characterization. Section III
solution for reducing energy consumption, though it introduces
performance challenges that necessitate custom design libraries. details the experimental setup used in this research. Section IV
In this work, we present a comprehensive methodology for cre- provides the design and implementation results of our SubVt
ating a specialized sub-threshold standard cell library, utilizing library. In Section V, we compare our implementation with
the SPEA-2 genetic algorithm for optimal transistor sizing. Our other SubVt implementations. Finally, Section VI concludes
library demonstrates an average energy efficiency improvement the paper by discussing our findings and outlining potential
of 44% compared to conventional approaches. We validated
its performance by synthesizing RISC-V processors and EPFL future directions for this work.
benchmark circuits, comparing them against standard foundry
II. S UB -T HRESHOLD D ESIGN M ETHODOLOGY
libraries operating at nominal (1.2 V) and near-threshold 600 mV
voltages. The results show a 13.26× and 1.49× reduction in In this section, we outline the steps to design an efficient
energy consumption, respectively, for the sub-threshold library, SubVt standard cell library. The process starts by selecting
although this comes with an increase in area by 5.21× and the supply voltage. Next, transistor schematics are created for
1.3×, respectively. These findings underscore the viability of sub-
threshold libraries as an effective option for energy-constrained a chosen set of logic gates. Transistor sizing for these gates
designs. is then optimized automatically using the SPEA-2 algorithm
Index Terms—Optimization, Sub-threshold Standard Cells, [4]. Physical layouts are designed according to standard cell
Energy Efficiency, Strength Pareto Evolutionary Algorithm 2 design rules. Once all the cells are created, characterization
is performed to create library files which we further use in
I. I NTRODUCTION design implementation.
Increasing demand for computing power and design com-
plexity make a strong case for pushing the limits of energy effi- A. Sub-Threshold Logic Design
ciency. We view circuit designing as a multi-level problem and
find the need to optimize the standard cells. We study standard
cell design methodologies and identify the potential of supply 1e−15
Etotal
voltage scaling for reducing energy consumption. Scaling the Edynamic
1.4
supply voltage below the switching threshold can lead to Estatic
Minimum Energy Point
maximum energy savings [1]. Leakage currents, otherwise 1.2

considered parasitic, are the primary operating currents when 1.0

the transistor enters weak inversion. These weaker currents
Energy (J)

result in a longer time to charge capacitive loads, limiting 0.8

the circuit’s operating frequency. Standard cells designed for 0.6

operating at supply voltages above the switching threshold
0.4
cannot be readily used with sub-threshold (SubVt ) voltages (352e-3,2.94e-16)

without modifications to the transistor aspect ratios. This 0.2

motivates designing a custom standard cell library for sub-
0.0
threshold operation. To achieve the energy benefits of SubVt
0.3 0.4 0.5 0.6 0.7 0.8
operation, transistor sizing needs to be performed considering Vdd (V)
multiple objectives such as power and delay. Treating standard
cell sizing as a multi-objective optimization problem, in this Fig. 1: Simulation results showing Minimum Energy Point and
work, we expand on the research in [3], our work includes: the contribution of active and leakage energy as the supply
• Automated transistor sizing to reduce Power-Delay prod- voltage is scaled for a CMOS Inverter designed using UMC
uct using SPEA-2 algorithm and designing custom stan- 55 nm technology.
dard cell library.
• Performance evaluation of designed standard cell library We designed our custom SubVt standard cell library using
by synthesizing EFPL benchmark circuits and open- UMC’s 55 nm FD-SOI process technology, which is advanta-
source processor designs. geous for low-power designs due to its reduced sensitivity to
 process variations compared to traditional bulk technologies. is the solution set for Equation (1) where all solutions in P
This process offers three types of transistors: regular (RVT), are non-dominated [2].
high (HVT), and low (LVT) Vt variants, each with specific To avoid the exhaustive search of the entire design space,
trade-offs—HVT transistors offer lower leakage but slower we perform optimization using a heuristic search algorithm,
operation, while LVT transistors switch faster but have higher wherein PDP is used as the sole metric for evaluating the
leakage. quality of potential solutions. To solve the optimization prob-
To optimize energy efficiency, we focused on finding the lem represented by Equation (1) we employ SPEA-2 algorithm
Minimum Energy Point (MEP) [1]. The MEP represents the [3] [4] that offers a better selection process, promoting more
supply voltage at which the energy per operation is minimized, diversity in the solution set, when compared to other genetic
balancing the trade-offs between active energy consumption algorithms, such as the Non-dominated Sorting NSGA-2 [3].
and leakage energy. As the supply voltage decreases into the The initial step involves generating a dataset of transistor
sub-threshold region, propagation delays increase, which can dimensions and their corresponding Ptotal and Tpd values
lead to higher leakage energy. The MEP is the point where using SPICE simulations. This dataset is then processed by
this trade-off results in the lowest total energy consumption the SPEA-2 algorithm [4], which evaluates each candidate and
while ensuring reliable functionality [1]. forms a Pareto front of non-dominated solutions representing
Our analysis found that the inverter logic gate reached its the best trade-offs between power and delay. By applying
MEP at around 350 mV (Fig 1). By applying a similar analysis crossover and mutation operators, the algorithm introduces
to other logic gates (Table I) in the library, we determined diversity and explores a broader design space, preventing
that using RVT transistors provided the best balance of energy premature convergence. The process continues until the pop-
efficiency and performance. We finalized the operating voltage ulation stabilizes, ensuring that the final transistor dimensions
for the entire standard cell library at 400 mV, as this setting achieve the optimal balance between power consumption and
optimized the Power-Delay Product (PDP) for all gates, com- delay. Figure 2 shows the design flow of these steps, with
bining the benefits of low energy consumption with acceptable detailed implementation discussed in Experimental Section III.
performance.
C. Sub-Threshold Standard Cell Design
B. Optimization Methodology Optimization is performed using the above-described
methodology to find the optimal transistor widths(Wn & Wp ),
as all lengths are fixed to Lmin i.e. 60 nm. After meeting
SPICE Simulation
Schematic Dataset the terminating criteria, the best solution is selected and
Design DC & Transient
Analysis
Generation
transistor dimensions are fixed. Finally, these optimized cells
Next Generation

Evaluate
are translated into a physical layout adhering to standard cell
Fitness design rules.
PDK, Optimization

Design Mutation and

Rules, Crossover
Cell Layout
Spice Standard Cell & Natural
Parasitic Selection
Models Layout Extraction

Timing & Terminate?

Library Power Yes No
Characterization model.

Fig. 2: The design flow implemented in our work to create

SubVt Standard Cell Library

Our work aims to optimize both total power consumption

Ptotal and propagation delay Tpd which is formulated as a
multi-objective optimization problem.
min F(x) (1)
x∈S
Fig. 3: Figure shows the CMOS Inverter layout designed ad-
where F : S ⊂ Rn → Rm is the multi-dimensional hering to standard cell design rule for UMC 55nm technology.
function and S is the search space consisting of transistor
dimensions. The optimization of SubVt cells often resulted in larger
transistor dimensions to achieve the desired drive strength.
P = {p ∈ S|∄x ∈ S : f (x) ≺ f (p)} (2) To accommodate the larger cell area and benefit from the
performance improvements of a multi-Vdd design [9], we opted Cadence Spectre, provided the data that formed the initial
to maintain the same cell height as the existing SuperVt population for our evolutionary search.
standard cell library. This allows us to utilize a 12-track The SPEA-2 algorithm was employed for the optimiza-
layout with a height of 2.4 µm. In order to accommodate tion process. In each iteration, the algorithm evaluated the
larger dimension transistors we use multiple fingered device population, generating a Pareto front of optimal trade-offs
technique [8]. This demonstrated a logical and progressive between power consumption and delay. To introduce diversity
performance improvement in the logic gates as the number and prevent premature convergence, we applied Simulated
of fingers in the physical layouts is increased by research Binary Crossover and Polynomial Mutation operators. The
conducted in [8], hence we adopted a layout design technique population size was capped at 20 elements per run, balancing
that leverages multi-fingered devices. the optimization time with the quality of solutions. The search
concluded when the population converged, meaning no further
D. Sub-Threshold Standard Cell Library significant improvements were observed, which served as our
The design process begins with selecting specific logic termination criterion.
gates. We focused on the cells most frequently used by the Post-optimization, we proceeded to layout design using
synthesis tool for RISC-V designs, utilizing a commercial Cadence Virtuoso Layout XL, adhering to standard cell de-
UMC 55 nm library operating at the nominal 1.2 V supply sign rules. Physical verification and parasitic extraction were
voltage (SuperVt ). performed using Siemens Calibre. The extracted parasitic
When operating at very low supply voltages, design choices elements were then used for cell characterization, generating
become critical. Standard cell libraries designed for higher a library with timing and power models for various oper-
voltages may not perform well, or at all, under such con- ating conditions. Cadence Liberate facilitated accurate cell
ditions. Thus, a cell library specifically tailored for low- characterization, while the Cadence Genus tool was used for
voltage operation is advantageous. We selected a subset of logic synthesis, ensuring the final designs met the required
cells capable of functioning effectively at lower voltages. specifications.
This subset, sufficient for synthesizing various digital designs, IV. R ESULTS AND D ISCUSSIONS
includes 9 combinational cells and 3 sequential cells. Circuits This section presents the key findings obtained from the
based on these logic gates were designed and followed the optimization process. To evaluate the effectiveness of the
methodology outlined in Table I. optimized library, we synthesized the EPFL benchmark cir-
Logic Gates Un-optimized PDP Optimized Improvement cuits [10] and open-source RISC-V processors core [11]
(fJ) PDP(fJ) (%) [16]. The performance of our library operating at 400 mV is
INV 0.032 0.014 56.58%
NAND2 0.065 0.025 61.16%
compared against a commercially available low-power UMC
NOR2 0.125 0.063 49.44% 55 nm RVT standard cell library operating at 1.2 V(SuperVt )
XOR2 1.35 0.786 41.78%
XNOR2 0.611 0.249 35.68%
and 600 mV (N earVt ).
AOI2 0.215 0.130 35.44%
OAI2 0.255 0.142 44.47% A. Optimization Analysis
MAOI22 0.757 0.472 37.72%
MOAI22 0.523 0.242 39.53%
1e−8 1e−10
2.1
TABLE I: SubVt Standard cell library composition and Power- Total Power 4.75
Propagation Delay
Delay product Improvement.
2.0 4.50

1.9 4.25

Propagation Delay(s)
III. E XPERIMENTAL S ETUP
Total Power(W)

4.00
1.8
This section details the design and optimization process of
our sub-threshold standard cell library. We describe the steps 1.7
3.75

taken to create the circuit schematics, perform transistor sizing

3.50
optimization, design the physical layouts, and extract the final 1.6
cell models for use in standard cell design flows. 3.25
We started by designing the schematics of the logic gates 1.5

using the Virtuoso Schematic Editor. For simulations, a test 3.00

bench with a fixed load capacitance of 1.844 fF was used, 0 10 20 30 40 50 60

Generations
chosen based on the effective capacitance of a 2-input NAND
gate operating in the SubVt region. We then created a SPICE
netlist that included all necessary circuit and simulation param- Fig. 4: The propagation delay and total power of the dominant
eters. Using this netlist and a SpectreMDL script, we generated solution across generations for CMOS Inverter logic designed
a dataset of Ptotal and Tpd values corresponding to various using UMC 55nm technology.
transistor dimensions. These SPICE simulations, executed in
 Works Process Implementation Min. Operating Power-Delay- Max. Operating Core Area (mm2 )
Technology (nm) Voltage (mV) Product (pJ ) Frequency (kHz)
[9] 90 MSP430 processor [17] 400 5.2 250 0.44
[12] 130 PicoRV32 processor [16] 300 1.68 1777 0.23
[14] 65 CoreVA processor [18] 325 9.9 133 0.24
[15] 65 MSP430 processor [17] 500 23.04 434 0.14
This work 55 PicoRV32 processor [16] 400 1.97 2333 0.20

TABLE II: Comparison of our work against other low-power sub-threshold standard cell library implementation.

B. Synthesis Results
7 × 10 18
The EPFL Benchmark [10] results in Fig. 7 for adder, barrel
shifter, sin and square demonstrate that our SubVt library
offers the least total power consumption and PDP compared
PDP (J)

to the SuperVt and N earVt libraries. However the cost of

6 × 10 18
increased area and lower operating frequency.
The synthesis results for the RISC-V processor cores PULP
[11], PicoRV32 [16] and VexRISCV across different volt-
age regions reveal significant insights into their performance.
5 × 10 18

0 10 20 30 40 50 60
These cores were evaluated based on parameters such as
Generation Power, Delay, Power-Delay Product (PDP), Gate Count, Area,
Fig. 5: The Power-Delay-Product propagation of dominant and Frequency. In the SubVt region, the PicoRV32 core
solution across generations for CMOS Inverter logic designed exhibited the highest frequency at 2.33 MHz, outperforming
using UMC 55nm technology. both the PULP and VEXRISCV cores. Meanwhile, the PULP
core achieved the lowest PDP of 0.608 pJ, making it the most
energy-efficient core in this region. Notably, the PULP RISC-
V processor can be found in Fig. 6 displaying an improvement
During the optimization, we observed that after exceeding in PDP by 13.26× and 1.49× when compared to the SuperVt
60 generations, no significant improvement in objective param- and N earVt library. The maximum achievable frequency for
eters of the Pareto-optimal points (solutions offering the best N earVt library was around 45 MHz but the total power
trade-off between objectives) was observed. Thus meeting our consumed was 69.2 µW. Whereas our SubVt library could
terminating criteria. The transistor dimensions obtained at the achieve a maximum frequency of 1.33 MHz but at a reduced
end of the 60th generation are adopted as the final optimized power consumption of 0.80 µW.
values and are used for subsequent design stages. The synthesis results of EPFL benchmarks and RISC-V
The results in Fig. 4 show the power and delay values processor showcase the potential of the optimization method
of the dominant solution across generations for the inverter and motivate the designer to use the custom-designed SubVt
logic gate. When we analyze the results we can observe that library for energy-efficient designs.
the the power and delay values do not change significantly V. R ELATED W ORK
after the 55th generation even after introducing mutations and Several previous works have explored low-power standard
crossover. Additionally, after the 55th generation, we observed cell design and optimization techniques. Blesken et al. [2]
consistent fitness values across both the entire population and pioneered the concept of multi-objective optimization for stan-
the dominant set over multiple generations. dard logic cells, aiming to strike a balance between resource
Table I compares the PDP of each logic gate before and after allocation and robustness. Building on this, Lutkemeier et al.
optimization using the SPEA-2 algorithm. As evident from the [14] designed a sub-threshold (SubVt ) standard cell library
table, all logic cells achieved significant optimization, with an operating at 325 mV, implemented on a CoreVA processor,
average improvement of 44% across the library. Notably, the which achieved a maximum frequency of 133 kHz, reaching a
AOI cell exhibited the least improvement in PDP compared to PDP of 9.9 pJ. Geisler et al. [3] investigated multi-objective
other basic cells. This difference in optimization effectiveness optimization tools for transistor sizing, comparing algorithms
is attributed to the AOI cell’s topology. Unlike some other like NSGA-II, SPEA-2, and GAIO. They concluded that
basic gates, the pull-down path in an AOI cell typically SPEA-2 provided superior optimization due to its ability to
consists of multiple transistors connected in series and parallel. maintain diversity in the solution set, although their research
In our optimization process, we assumed equal transistor was limited to designing inverters and NAND gates.
widths for all transistors in the pull-up and pull-down path as Several other studies have examined ultra-low-power de-
equivalent to Wp and Wn respectively. Without considering the signs across different process technologies (Table II). In [9],
individual widths for optimization, this approach might have a 90 nm MSP430 processor operated at 400 mV with a PDP
resulted in imbalanced transistor sizing, limiting the overall of 5.2 pJ while research by Djupdal et al. [12] compared low-
P DP improvement for the AOI logic gate. power cores like PicoRV32 [16] and SERV, and developed a
 109 10−2
SubVt
NearVt
105
−11 SuperVt
10

Power-Delay product(J)
10−3
108

Total Power(W)
Frequency(Hz)
Area(µm²)

6 × 104

10−4

4 × 104

107 10−12
3 × 104 10−5

2 × 104
10−6
106
VEXRISCV PICORV32 PULP VEXRISCV PICORV32 PULP VEXRISCV PICORV32 PULP VEXRISCV PICORV32 PULP

(a) (b) (c) (d)

Fig. 6: Comparison of processor synthesis results with SubVt , N earVt and SuperVt library implementation. Figure (a) depicts
the area occupied by each benchmark, figures (b) and (c) display the frequency and power respectively and (d) indicates the
PDP.

105 SubVt
NearVt
10−4 SuperVt
108

Power-Delay product(J)
10−12

Total Power(W)
Frequency(Hz)

10−5
Area(µm²)

107
104
10−6
10−13

106 10−7

Adder Barrel shifter Sin Square Adder Barrel shifter Sin Square Adder Barrel shifter Sin Square Adder Barrel shifter Sin Square

(a) (b) (c) (d)

Fig. 7: Comparison for EPFL Benchmark synthesis results between SubVt , N earVt and SuperVt library implementation.
Figure (a) depicts the area occupied by each benchmark, and figures (b) and (c) display the frequency and power respectively
followed by PDP in figure (d) where the SubVt shows the best results

130 nm library for 250 mV-600 mV operation. They focused a trade-off in operating speeds. Our findings underscore the
on sizing transistors around the threshold voltage to enhance potential of using optimized sub-threshold standard libraries as
noise margins and switching speeds while using a conventional viable alternatives for designs where energy efficiency is more
layout. Their PicoRV32 [16] implementation achieved a PDP important than operating speeds. Future work will include
of 1.68 pJ at 300 mV, with a frequency of 1.7 MHz and an adding more logic gates to the library to improve the efficiency
area of 0.23mm². further.
In comparison, our work builds upon the research by Geisler
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