(Study Guide) Logic Circuits: R. Stephen L. Ruiz 2009
(Study Guide) Logic Circuits: R. Stephen L. Ruiz 2009
Contents
1 Binary Systems 1.1 Positional Number System . . . . 1.2 Number Base Conversion . . . . 1.3 Octal and Hexadecimal Numbers 1.4 Complements . . . . . . . . . . . 1.5 Signed Binary Numbers . . . . . 1.6 Binary Codes . . . . . . . . . . . 1.7 Binary Logic . . . . . . . . . . . 2 Boolean Algebra 2.1 Basic Denitions . . . . . . . . 2.2 Boolean Algebra Dened . . . . 2.3 Basic Theorems and Properties 2.4 Boolean Functions . . . . . . . 2.5 Canonical and Standard Forms 2.6 Other Logic Operations . . . . 2.7 Digital Logic Gates . . . . . . . 2.8 Integrated Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 1 2 2 3 3 5 9 9 9 10 10 12 13 14 15
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1 Binary Systems
1.1 Positional Number System
Each digit position has an associated weight d2 d1 d0 .d1 d2 D = d2 102 + d1 101 + d0 100 + d1 101 + d2 102 10 is the base or radix of the number system. In general, dp1 dp2 d1 d0 .d1 d2 dn
p1
D=
i=n
di ri
(630.4)8 =6 82 + 3 81 + 4 81 =(408.5)10 Decimal to another number system. Integer part repeated division divide the integer part by the radix Last remainder most signicant Fractional part repeated multiplication multiply the fractional part by the radix First integer most signicant
Table 1.1: Numbers with dierent bases Decimal (base 10) 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 Binary (base 2) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Octal (base 8) 00 01 02 03 04 05 06 07 10 11 12 13 14 15 16 17 Hexadecimal (base 16) 0 1 2 3 4 5 6 7 8 9 A B C D E F
M.M. Mano, Digital Design, 3rd ed. Upper Saddle River, NJ: Prentice-Hall, 2002, 1-32.
Binary Systems
Radix Complement
The rs complement with an integer part of n digits rn N for N = 0 and 0 for N = 0.
BCD Addition
Add six if the sum is greater than or equal to (1010)2 or when the sum generates a carry
ASCII
American Standard Code for Information Interchange. 7-bit code to represent 128 characters
Table 1.2: BCD Decimal digit 0 1 2 3 4 5 6 7 8 9 (BCD) 8421 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001
Table 1.3: Other Decimal Codes for Decimal Digits Decimal digit 0 1 2 3 4 5 6 7 8 9 Unused combination
2421 0000 0001 0010 0011 0100 1011 1100 1101 1110 1111 0101 0110 0111 1000 1001 1010
Excess 3 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 0000 0001 0010 1101 1110 1111
8 4 -2 000 011 011 010 010 101 101 100 100 111 000 001 001 110 110 111
-1 0 1 0 1 0 1 0 1 0 1 1 0 1 0 1 0
Binary Systems
Table 1.4: Four-bit Gray(Reected) Code Decimal 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Reected code 0000 0001 0011 0010 0110 0111 0101 0100 1100 1101 1111 1110 1010 1011 1001 1000
EBCDIC
Extended Binary Coded Decimal Interchange Code. 8-bit code IBM code representing characters and numbers.
Baudot Code
Code developed in the early stages of teletype transmission. 5-bit code with two modes of operation: letters and gures
Hollerith Code
Code for programs and data prepared in punched cards. A punched card consists of 80 columns and 12 rows. Each column represents an alphanumeric character of 12 bits.
{myNotes} Logic Circuits 2. logical operations Three basic logical operations: 1. AND x y = z means z = 1 if and only if x = 1 and y = 1; otherwise z = 0. 2. OR x + y = z means z = 1 if and only if x = 1 or if y = 1 or both x = 1 and y = 1. If both x = 0 and y = 0, then z = 0. 3. NOT x = z or ( = z) means if x = 1, then z = 0; but if x = 0, then z = 1. x
A truth table is a table of all possible combinations of the variables showing the relation between the values that the variable may take and the result of the operation. Table 1.5: Truth Table of AND Operation x 0 0 1 1 y 0 1 0 1 xy 0 0 0 1
Binary Systems
Logic Gates
For TTL(transistor-transistor-logic): logic- 0: 0 0.4volts, 0.2v typical logic-1: 2.4 5.0 volts, 3.5v typical For CMOS(Complementary Metal Oxide Semiconductor): logic-0: 0 33% of supply voltage logic-1: 66 100% of supply voltage
y x
0 | 1 | 0 | 1 | 0 0 0 | 1 1 1 | 0 1 | 0
x+y 0 | 1 xy 0 y 0
0 | 1 | 0
1 | 0 | 1 | 0 | 1
2 Boolean Algebra
2.1 Basic Denitions
The most common postulates of a mathematical system that forms the basic assumptions from which the rules, theorems and properties are deduced: 1. Closure. A set S is closed with respect to a binary operator if for every pair of elements of S, the binary operator species a rule for obtaining a unique element of S. 2. Associative law. (x y) z = x (y z) for all x, y, z S 3. Commutative law. x y = y x for all x, y S 4. Identity element. x e = e x for every x S Example: x + 0 = 0 + x = x for every x S 5. Inverse. xy =e Example: a + (a) = 0 6. Distributive law. x (y z) = (x y) (x z)
M.M. Mano, Digital Design, 3rd ed. Upper Saddle River, NJ: Prentice-Hall, 2002, 33-63.
3. Commutative with respect to + and . 4. is distributive over + + is distributive over . 5. There exist a complement such that x + x = 1 and x x = 0 6. There are two distinct elements 1, 0 with 1 = 0
M.M. Mano, Digital Design, 3rd ed. Upper Saddle River, NJ: Prentice-Hall, 2002, 40-63.
Boolean Algebra 11
F1 = x + y z F2 = x y z + x yz + xy The Boolean functions can be represented in a truth table. A truth table is a list of combinations of 1s and 0s assigned to the binary variables and a column that shows the value of the function for each combination. Table 2.2: Truth Table for F1 . x 0 0 0 0 1 1 1 1 y 0 0 1 1 0 0 1 1 z 0 1 0 1 0 1 0 1 F1 0 1 0 0 1 1 1 1
A Boolean function can be represented in a circuit diagram composed of logic gates. There is a unique truth table for a Boolean function. However, in algebraic form, the function can be expressed in a number of ways. Consider: F3 = x y z + x yz + xy
Algebraic Manipulation
A Boolean expression when implemented with logic gates requires a gate for each term and each variable within a term designates an input to the gate. A simpler circuit can be obtained by reducing the number of terms, the number of literals or both in a Boolean expression.
Complement of a Function
The complement of a function can be derived by using DeMorgans theorem.
x 0 0 0 0 1 1 1 1
y 0 0 1 1 0 0 1 1
z 0 1 0 1 0 1 0 1
Boolean Algebra 13 A Boolean function can be expressed algebraically by ORing all minterms that produces a 1 in the function. This expression is called a sum of minterms. The same function can be expressed in product of maxterms by ANDing all maxterms that produces a 0 in the function. These expressions are said to be in canonical form.
Sum of Minterms
A Boolean function can be expressed in sum of minterms by expanding the function into a sum of AND terms. If a term misses one or more variables, it is ANDed with an expression x + x , where x is the missing variable. A short notation using the symbol can stand for the ORing of the terms.
Product of Maxterms
A Boolean function can be expressed in product of maxterms by expanding the function into a product of OR terms. If a term misses one or more variables, it is ORed with an expression xx , where x is the missing variable. A short notation using the symbol can stand for the ANDing of the terms.
Standard Forms
In standard form the terms may contain one, two or any number of literals. The sum of products is a Boolean expression containing AND terms, called product terms of one or more literals. The sum denotes the ORing of these terms. F1 = y + xy + x yz The product of sums is a Boolean expression containing OR terms, called sum terms of one or more literals. The product denotes the ANDing of these terms. F1 = x(y + z)(x + y + z )
Table 2.5: 16 Functions of Two Binary Variables. x 0 0 1 1 y 0 1 0 1 F0 0 0 0 0 F1 0 0 0 1 F2 0 0 1 0 F3 0 0 1 1 F4 0 1 0 0 F5 0 1 0 1 F6 0 1 1 0 F7 0 1 1 1 F8 1 0 0 0 F9 1 0 0 1 F10 1 0 1 0 F11 1 0 1 1 F12 1 1 0 0 F13 1 1 0 1 F14 1 1 1 0 F15 1 1 1 1
Table 2.6: Boolean Expression for the 16 Functions of Two Variables. Boolean Function F0 = 0 F1 = xy F2 = xy F3 = x F4 = x y F5 = y F6 = xy + x y F7 = x + y F8 = (x + y) F9 = xy + x y F10 = y F11 = x + y F12 = x F13 = x + y F14 = (xy) F15 = 1 Operator symbol xy x/y y/x xy x+y xy (x y) y xy x xy xy Name Null AND Inhibition Transfer Inhibition Transfer Exclusive-OR OR NOR Equivalence Complement Implication Complement Implication NAND Identity Comments Binary constant 0 x and y x but not y x y but not x y x or y, but not both x or y Not-OR x equals y Not y If y, then x Not x If x, then y Not-AND Binary constant 1
x 0 0 1 1
AND y xy 0 0 1 0 0 0 1 1
x 0 0 1 1
OR y x+y 0 0 1 1 0 1 1 1
x 0 0 1 1
NAND y (xy) 0 1 1 1 0 1 0 1
x 0 0 1 1
y 0 1 0 1
NOR (x + y) 1 0 0 0
x 0 0 1 1
XOR y xy 0 0 1 1 0 1 1 0
Equivalence x y (x y) 0 0 1 0 1 0 1 0 0 1 1 1
The NAND and NOR operators are commutative but not associative. We dene multple NOR (or NAND) gate as a complemented OR (or AND) gate. Thus x y z = (x + y + z) x y z = (xyz)
The exclusive-OR and equivalence gates are both commutative and associative and can be extended to more than two inputs.
Table 2.10: Levels of Integration. Integration Level Small-scale (SSI) Medium-scale (MSI) Large-scale (LSI) Very large-scale (VLSI) Number of gates < 10 10 - 1,000 1, 000 100, 000 > 100, 0000 Applications Basic gates Elementary digital operations Processors, memory chips, Programmable Logic Devices (PLD) Large memory arrays, complex microcomputer
1. Fan-out - number of standard loads that the output can normally drive.
Boolean Algebra 17
Table 2.11: Logic Families. Family Transistor-transistor logic (TTL) Emitter-coupled logic (ECL) Metal-oxide semiconductor (MOS) Complementary MOS (CMOS) Application standard high-speed high component density Low power consumption
2. Fan-in - number of inputs available in a gate. 3. Power dissipation - power consumed by the gate. 4. Propagation delay - average transition delay for the signal to propagate from input to output. 5. Noise margin - maximum external noise voltage added to the input signal that has no eect in the circuit output.
Table 2.12: Typical Characteristics of IC Logic Families. Logic Family Fan-out Power dissipation (mW) 10 22 2 25 0.1 Propagation delay (ns) 10 3 10 2 25 Noise margin (V) 0.4 0.4 0.4 0.2 3
Standard TTL (74-) Schottky TTL (74S-) Low-power Schottky TTL (74LS-) ECL CMOS (74C-)
10 10 20 25 50