CMOS Analog Design Using All-Region MOSFET

Modeling
1

CMOS Analog Design Using
All-Region MOSFET Modeling

Chapter 5
Current mirrors
CMOS Analog Design Using All-Region MOSFET
Modeling
2
M
1
: iv converter
M
2
: vi converter
The basic current mirror
V
DD

V
OUT

I
IN

I
OUT

M
1
M
2

1:1
| |
( , ) ( , )
D S f r G S G D
W
I I i i G V V G V V
L
( = =

M
1
=M
2

First-order analysis
Both M
1
& M
2
in saturation
( , ) 0
G D
G V V =
Since M
1
& M
2
are identical with same
gate, source and bulk voltages:
OUT IN
I I =
CMOS Analog Design Using All-Region MOSFET
Modeling
3
V
DD

I
IN

I
OUT

1/2:1




W/L
W/L
W/L
V
DD

I
IN
I
OUT

1:2




W/L
W/L
W/L
V
DD

I
IN
I
OUT

1:2




W/L
2W/L
Why not?
Gain-of-two current mirror
CMOS Analog Design Using All-Region MOSFET
Modeling
4
( )( )
( )( )
, 1
, 1
S G T S out
out
in S G T S in
I f V V V v
i
i I f V V V v

+
=
+
( )( )
, 1
D S G T S D D Dsat
I I f V V V V V V = + >
( )
out in out in
out in
in A
i i v v
v v
i V

~ =
V
DD

i
in

+
v
-
i
out

v
out

+
-
M
1

M
2

1:1
Error due to difference in drain voltages
The linear variation of the drain current
with the drain voltage is a crude
approximation. =1/V
A
, V
A
is the Early
voltage, roughly proportional to the
channel length.
I
D

V
D

-V
A

CMOS Analog Design Using All-Region MOSFET
Modeling
5
( )( )
, 1
D S G T S D D Dsat
I I f V V V V V V = + >
V
DD

i
in

i
out

v
out
=v
in

+
-
M
1

M
2

1:1
+
v
in
-
Error due to mismatch is negligible.
The mismatch can be calculated
either using Pelgroms model



or
2
2
2
*2
1
2 1
ln
1
D
I f
oi
D f
ISH
r r
i
N
I WL N i
A
i i
o (
+
| |
=
(
|
+
\ .

+
(
( )
( )
2
2
2
2
0
2
2 2
1 1
D
VT
ISH
D t
f
I
A
A
I WL n
i
o
|

(
| |

(
~ +
` |
(
+ +
\ .


)
2
0
*2
oi VT
t
N A
N n|
| |
=
|
\ .
Error due to mismatch - 1
CMOS Analog Design Using All-Region MOSFET
Modeling
6
Dependence of current matching on inversion level in linear and saturation regions
(|V
DS
| = 20 mV and |V
DS
| = 2 V, respectively, where V
DS
is the drain-to-source
voltage) for the large, medium-size, and small PMOS transistor arrays.
Error due to mismatch - 2
CMOS Analog Design Using All-Region MOSFET
Modeling
7
( )( )
( )
1 1 1 2 2 1
1 1 1 1
1
1
1
1

1 2
gs gb gs gb db
gs gb db
out
in mg T
C C C C C C
C A C C C
I C A A
s
I s g f
t
t t
= + + + +
= + + +
+
~ = ~
+
1. Model is valid as long as et
1
<<1;
2. C
3
introduces a finite zero in the
transfer function;
3.

( )
( )
1 1 3
0
2 2 2
out
in m
v
out ds db
Y g s C C
Y g s C C
=
= + +
~ + +
Frequency response
g
m1
+
g
ds1

i
o

i
i
g
i

C
1
v
o

+
g
ds2

C
2

g
m2
v
i

v
i

C
3

i
i

+
v
-
i
o

M
1

M
2

i
2

1:A
v
o

CMOS Analog Design Using All-Region MOSFET
Modeling
8
( )
( )
2
2 2 2 2
2 2 2
1 2 1 2
1 1 1

m m m
o i o i
m m m
g g g
i i i i i i i i A
g g g
| |
= + + = + + =
|
\ .
2 mg
g v
1
1
mg
ds
g
g
+
ac model (capacitive
effects not accounted for)
i
i

+
v
-
i
out

i
1

i
2

i
i
, i
1
, i
2
noise sources associated with input
signal source, M
1
, and M
2
, respectively.
Superposition & uncorrelated noise sources
Thermal & flicker noise
Noise analysis
1:A
M
1
M
2

2
1
i
2
o
i
2
i
i
2
2
i
CMOS Analog Design Using All-Region MOSFET
Modeling
9
Current gain schemes - 1
V
DD

i
i

i
o=
=Ai
i

......
V
DD

i
i

i
o=
=i
i
/A
......
Gain=A
Gain= 1/A
i
i

i
o=
=i
i
/(NM)
.....
.
.
.
.
.
.
.
N
M
Gain=1/(NM)
CMOS Analog Design Using All-Region MOSFET
Modeling
10
Current gain schemes - 2
I
2R 2R 2R 2R R
R R R R
I/2
I/4
I/8 I/16
CMOS Analog Design Using All-Region MOSFET
Modeling
11
C. C. Enz and E. A. Vittoz, CMOS Low-Power Analog Circuit Design, Chapter 1.2 in Emerging
Technologies, R. Cavin and W. Liu (eds.), Tutorial for ISCAS 96.
Current gain schemes - 3
CMOS Analog Design Using All-Region MOSFET
Modeling
12
( )
2 1
/
o
i G G i =
V
CM

i
-

+
G
1

-

+
G
2

V
CM

Inverting
current mirror
V
DD

V
CM

i
-

+
V
DD

-

+
V
CM

( )
( )
2
1
/
/
o
W L
i i
W L
=
M
1

M
2

Op-amp based current mirror
CMOS Analog Design Using All-Region MOSFET
Modeling
13
Simple current mirror:
Error
Low output impedance large
Possible solution: Increase L
Is frequency response acceptable?
( )
2
2 1 1
2
t
T f
f i
L
|
t
= +
Cascode current mirror - 1
OUT IN
V V =
V
DD

V
OUT

I
IN

I
OUT

M
1
M
2

1:1
V
IN

OUT
OUT
dI
dV
CMOS Analog Design Using All-Region MOSFET
Modeling
14
Basic idea to improve the
performance of the simple current
mirror output voltage follows the
input voltage
Active regulated cascode
current mirror
Choosing V
D
~V
DSsat1
gives
maximum output swing
Cascode current mirror - 2
CMOS Analog Design Using All-Region MOSFET
Modeling
15
The cascode stage
V
DD

i
in

+
v
-
i
out

v
out

+
-
M
1

M
2

1:1
M
3

V
B

X
1. Voltage at node X is (almost) independent
of V
out
(as long as M
3
operates in saturation).

Output impedance (small-signal analysis):
2 2 3 3
3 3
2 2
3 2 3
0 0
;
in
out mg md x out ms x md out
out md md
md md
out ms md ms
i v
i g v g v i g v g v
i g g
g g
v g g g
= =
= + = +
= ~
+
2. V
X
= v and v depends on i
in
error
3. What about V
B
?
Output conductance
of a single transistor
Inverse of
voltage gain
Cascode current mirror - 3
CMOS Analog Design Using All-Region MOSFET
Modeling
16
Suppose M
1
M
2
M
3
M
4
1. First-order analysis: If M
4
operates in
saturation, then V
X
~V
Y
and I
out
~I
in
2. The output conductance:
3
2
3
0 0;
out md
in md
out ms
i g
i v g
v g
= = ~
3. Note that V
DD
> V
CS
+V
GS3
+V
GS1
V
CS
is the minimum voltage for proper
operation of the current source
4. Note that V
out
> V
GS1
+V
DS4,sat
for
saturation of M
4

5. SBCCM is not a low-voltage current
mirror
V
DD

i
in

+
v
-
i
out

v
out

+
-
M
1

M
2

1:1
M
4

X
M
3

Y
+
V
CS
_
Self-biased cascode current mirror - 1
CMOS Analog Design Using All-Region MOSFET
Modeling
17
( )
| |
3
3
1 100 2 ln 1 100 1
1.3 10.25 0.883 0.550 2.03 V
P Y
t
G t
V V
V
|
|

= + + + =
= + + =
V
DD

i
in

i
out

v
out

+
-
M
1

M
2

1:1
M
4

X
M
3

Y
+
V
CS
_
Example: 0.35 um CMOS technology,
V
T0N
=0.55V, n~1.3, I
SQN
=70 nA, W=10
m, L=1 m
a) I
in
=70 A, I
S
=70x10/1=700 nA
i
f
=70/0.7=100
( )
1
1 2 ln 1 1 10.25
1.3 10.25 0.550 0.883
P
f f
t
Y t
V
i i
V V
|
|
= + + + =
= + =
c) Whats V
G3
in a) if V
SB3
=0?
d) Exercise: Repeat a), b),
and c) for Iin=70 nA
b) Whats the minimum V
out
to
keep M
4
in saturation
Self-biased cascode current mirror - 2
CMOS Analog Design Using All-Region MOSFET
Modeling
18
V
DD

i
in

i
out

v
out

+
-
M
1

M
2

1:A
i

M
3

V
B

X
Saturation of M
3
:
3 3,
3,
DS DS sat
out X DS sat
V V
V V V
>
> +
To maximize the output voltage swing
minimize V
X
V
X
= V
DS2,sat
+ AV
V
B
should be designed accordingly.
Error due to different V
DS
for M
1
& M
2

Low-voltage cascode current mirror - 1
CMOS Analog Design Using All-Region MOSFET
Modeling
19
I
in

M
1

M
2

1:A
i

I
out

M
3

X
V
DD

I
B

M
4

Low-voltage cascode current mirror - 2
3 2 2 S DS DSsat
V V V V = = + A
t
V o| A =
( 1 3)
DSsat t f
V i | = + +
Find a set I
B4
& S
4
for the value found for i
f4
UICM applied to M
3
, find V
G3
such that (I) is
satisfied

M
2
on the edge of saturation

(I)
UICM applied to M
4
, find i
f4
such that V
G3
is
obtained

CMOS Analog Design Using All-Region MOSFET
Modeling
20
Low-voltage cascode current mirror - 3
V
DD

I
O

M
1
M
2

I
B

M
4

M
3

V
O

V
DD

I
B5

M
5

+
V
DS
2
_

Symmetric low-voltage cascode
current mirror
( )
5 5 5
1 2 ln 1 1
P t f f
V i i |
(
= + + +

( ) 4 4 4 4
1 2 ln 1 1
P S t f f
V V i i |
(
= + + + +

4 2 2 S DS DSsat
V V V V = = + A
t
V o| A =
( )
( )
5 5
4 4 4
1 1 ln 1 1
1 3 1 1 ln 1 1
f f
f f f
i i
i i i o
(
+ + + =

(
(
+ + + + + + +


( 1 3)
DSsat t f
V i | = + +
(I)=(II)
(II)
(I)
4
4

B
in B in f
S
I
I I i i
I
= + =
CMOS Analog Design Using All-Region MOSFET
Modeling
21
2 m CMOS technology
V
T0N
~0.55 V
Experimental results - 1
CMOS Analog Design Using All-Region MOSFET
Modeling
22
Experimental results - 2
CMOS Analog Design Using All-Region MOSFET
Modeling
23
V
DD

I
I

M
1

M
3

I
B

I
B

V
Bias

M
5

M
7

I
O

V
DD

V
DD

M
2

M
4

M
6

M
8

Class-AB current mirror
CMOS Analog Design Using All-Region MOSFET
Modeling
24
V
DD

I
B1

I
B2
+I
OUT

M
1
M
2

I
IN

Simple MOS current mirror and symbols
used to analyze distortion. Drain voltages
of M
1
and M
2
assumed to be equal.
0 2 1
2 1
2
1 1
2
S T B B B
B B B S t
f
I V I I I
I I I I n
i
|
A A A
= ~
+
| | + +
|
\ .
2 1
2 1
2
S S S
S S S
I I I
I I I
A
=
+
| |
|
\ .
0 02 01 T T T
V V V A =
B
f
S
I
i
I
=

0 1 2 1 2
1 2
1 2
1 2
1 1
ln 1 1 ln 1 1
T B IN B OUT P P
t t S S
B IN B OUT
S S
V I I I I V V
n I I
I I I I
I I
| |
A + +
= = + +
| | | |
+ +
+ + +
| |
| |
\ . \ .
Appendix: current mirror distortion - 1
Distortion in CM is mainly generated by V
T
(doping fluctuations)
mismatch and dependence of the current on the output voltage
CMOS Analog Design Using All-Region MOSFET
Modeling
25
0
0
1
1 1
1
OUT S T
IN S t
f
dI I V
dI I n
i
|
A A
= + ~
+
( )
2
0
3 2
0
1
2
1
OUT T
IN t S
f
d I V
dI n I
i
|
A
~
+
( )
3
0
5 3 2
0
3 1
4
1
OUT T
IN t S
f
d I V
dI n I
i
|
A
~
+
( )
( )
0
2
2
3
2
0
3
3
5
1
8
1
1 1
32
1
T
MO M
M S t
f
T
MO M
M S t
f
V
I I
HD
I I n
i
V
I I
HD
I I n
i
|
|
A
= =
+
A | |
= =
|
\ .
+
Appendix: current mirror distortion - 2