What is Microcontroller?

A microcontroller can be considered a self-contained

system with a processor, memory and peripherals
and can be used as an embedded system.
Microcontrollers are "embedded" inside some other
device (often a consumer product) so that they can
control the features or actions of the product.
Another name for a microcontroller, therefore, is
"embedded controller."
Microcontrollers are dedicated to one task and run
one specific program. The program is stored in ROM
(read-only memory) and generally does not change.

What is Microcontroller?

Microcontrollers are often low-power

devices.
A microcontroller has a dedicated
input device and often (but not always)
has a small LED or LCD display for
output.
A microcontroller is often small and low
cost. The components are chosen to
minimize size and to be as inexpensive
as possible.

What is Microcontroller?

A microcontroller is often, but not always,

ruggedized in some way.

The microcontroller controlling a car's engine, for

example, has to work in temperature extremes
that a normal computer generally cannot handle.
A car's microcontroller in Alaska has to work fine
in -30 degree F (-34 C) weather, while the same
microcontroller in Nevada might be operating at
120 degrees F (49 C). When you add the heat
naturally generated by the engine, the
temperature can go as high as 150 or 180
degrees F (65-80 C) in the engine compartment.
On the other hand, a microcontroller embedded
inside a VCR hasn't been ruggedized at all.

What is Microcontroller?

It is a small chip used for processing

information.
The microcontroller has a central
processing unit (CPU), memory,
timers, input and output ports on a
single chip.
Microcontrollers are mainly used for
specific purposes.

How it Looks like ?

Inside a Microcontroller

The main building blocks of a

microcontroller are as seen

Uses of Microcontrollers

History of Microcontrollers

Other Microcontrollers

Microcontroller and
Microprocessor

Microprocessor and
Microcontroller

Difference Continued

Von Neumann
architecture

The von Neumann architecture is a

design model for a stored-program
digital computer that uses a central
processing unit (CPU) and a single
separate storage structure ("memory")
to hold both instructions and data.
It is named after the mathematician
and early computer scientist John von
Neumann.

Von Neumann Block

Diagram

Harvard architecture

The Harvard architecture is a computer

architecture with physically separate storage
and signal pathways for instructions and data.
The term originated from the Harvard Mark I
relay-based computer, which stored
instructions on punched tape (24 bits wide)
and data in electro-mechanical counters.
In a Harvard architecture, there is no need to
make the two memories share characteristics.
The word width, timing, implementation
technology, and memory address structure
can differ.

Harvard architecture

Under von Neumann architecture the CPU

can be either reading an instruction or
reading/writing data from/to the memory.
It cannot occur at the same time since the
instructions and data use the same bus
system.
In a computer using the Harvard
architecture, the CPU can both read an
instruction and perform a data memory
access at the same time.

Harvard architecture (Block

diagram)

CISC Architecture

CISC stands for Complex Instruction

Set Computer.
Complex instruction set computing,
or CISC is a computer instruction set
architecture (ISA) in which each
instruction can execute several lowlevel operations, such as a load from
memory, an arithmetic operation, and a
memory store, all in a single instruction.

CISC Architecture

In the early days of the computer industry,

high level programming languages were not
available and most of the work was done in
assembly language. Therefore CPU designers
tried to make instructions that would do as
much work as possible.
The general thinking at that time was that
hardware design was easier than compiler
design, so large parts of the complexity of the
software went into the hardware (and/or
microcode). This design philosophy was named
Complex Instruction Set Computer (CISC).

RISC Architecture

Reduced instruction set computing, or

RISC, is a CPU design strategy based on
the insight that simplified (as opposed to
complex) instructions can provide higher
performance if this simplicity enables much
faster execution of each instruction.
With the advent of higher level languages,
a new design strategy started to gain more
and more popularity: instructions which "do
less" may still provide high performances if
this simplicity can be utilized to make
instructions execute very quickly.

Introduction to 8051

8051 Features

The features of the 8051 core are

8-bit CPU optimized for control applications

Extensive Boolean processing (Single-bit logic) capabilities
64K Program Memory address space
64K Data Memory address space
4K bytes of on-chip Program Memory
128 bytesof on-chip Data RAM
32 bidirectional and individually addressable 1/0 lines
Two 16-bit timer/counters
Full duplex UART
6-source/5-vector interrupt structure with two priority levels
On-chip clock oscillator

Some handy notes

Handy notes - Memory

Differences in
microcontrollers

Other flavours of 8051

8051 Pin Diagram

P1.
P1.1
0
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
(RXD)P3.0
(TXD)P3.1
(INT0)P3.2
(INT1)P3.3
(T0)P3.4
(T1)P3.5
(WR)P3.6
(RD)P3.
XTAL2
7
XTAL1
GND

1
2
3
4
5
6
7
8
9
1
1
0
1
1
2
3
1
1
4
1
5
1
6
7
1
1
8
2
9
0

8051
(8031
)

4
3
0
3
9
8
3
3
7
3
6
5
3
3
4
3
3
2
3
1
2
0
2
9
8
2
2
7
2
6
2
5
2
4
2
3
2
1

Vcc
P0.0(A
P0.1(AD1)
D0)
P0.2(A
P0.3(AD
D2)
3)
P0.4(AD
P0.5(AD5
4)
)P0.6(AD6)
P0.7(AD
7)
EA/VPP
ALE/PRO
G
PSEN
P2.7(A15)
P2.6(A1
P2.5(A1
4)
P2.4(A1
3)
P2.3(A1
2)
P2.2(A1
1)
P2.1(A9
0)
)P2.0(A8
)

8051 Pins

Vcc pin 40
Vcc provides supply voltage to the chip.
The voltage source is +5V.
GND pin 20 ground
XTAL1 and XTAL2 pins 19,18

8051 Pins

RST pin 9 reset

It is an input pin and is active high normally low .

The high pulse must be high at least 2 machine

cycles.
It is a power-on reset.

Upon applying a high pulse to RST, the

microcontroller will reset and all values in registers
will be lost.

Reset values of some 8051 registers

8051 Pins

/EA pin 31 external access

There is no on-chip ROM in 8031 and 8032 .
The /EA pin is connected to GND to indicate the code is
stored externally.
/PSEN ALE are used for external ROM.
For 8051, /EA pin is connected to Vcc.
/ means active low.
/PSEN pin 29 program store enable
This is an output pin and is connected to the OE pin of the
ROM.

Port 3
P3 Bit

Function

Pin

P3.0

RxD

10

P3.1

TxD

11

P3.2

INT0

12

P3.3

INT1

13

P3.4

T0

14

P3.5

T1

15

P3.6

WR

16

P3.7

RD

17

Block Diagram of 8051

The CPU

CPU - Basics

CPU - Working

CPU - Working

CPU - Basics

CPU - Basics

CPU - Basics

CPU - Basics

CPU - Working

Appropriate flags are set.

Due to addition caused an overflow
of bits or parity change.

Another Block Diagram

Types of Memory

Types of Memory

On-Chip Memory refers to any memory

(Code, RAM, or other) that physically exists
on the microcontroller itself. On-chip
memory can be of several types.
External Code Memory is code (or
program) memory that resides off-chip. This
is often in the form of an external EPROM.
External RAM is RAM memory that resides
off-chip. This is often in the form of
standard static RAM or flash RAM.

Types of Memory

Code Memory

Code memory is the memory that holds the actual

8051 program that is to be run.
This memory is limited to 64K and comes in many
shapes and sizes.
Code memory may be found on-chip, either burned
into the microcontroller as ROM or EPROM.
Code may also be stored completely off-chip in an
external ROM or, more commonly, an external EPROM.
When the program is stored on-chip the 64K
maximum is often reduced to 4k, 8k, or 16k. This
varies depending on the version of the chip that is
being used.

Types of Memory

External RAM

As the name suggests, External RAM is any random

access memory which is found off-chip.
Since the memory is off-chip it is not as flexible in
terms of accessing, and is also slower.
For example, to increment an Internal RAM location
by 1 requires only 1 instruction and 1 instruction
cycle. To increment a 1-byte value stored in External
RAM requires 4 instructions and 7 instruction cycles.
In this case, external memory is 7 times slower!
What External RAM loses in speed and flexibility it
gains in quantity.

Types of Memory

On-chip memory

On-chip memory is really one of two

types: Internal RAM and Special
Function Register (SFR) memory.

Register Banks

The 8051 uses 8 "R" registers which

are used in many of its instructions.
These "R" registers are numbered
from 0 through 7 (R0, R1, R2, R3, R4,
R5, R6, and R7). These registers are
generally used to assist in
manipulating values and moving data
from one memory location to another.

Register Banks

For example, to add the value of R4 to the Accumulator,

we would execute the following instruction:

ADD A,R4

Thus if the Accumulator (A) contained the value 6 and R4 contained

the value 3, the Accumulator would contain the value 9 after this
instruction was executed.
However, as the memory map shows, the "R" Register R4 is really
part of Internal RAM. Specifically, R4 is address 04h. This can be see
in the bright green section of the memory map. Thus the above
instruction accomplishes the same thing as the following operation:

ADD A,04h

This instruction adds the value found in Internal RAM address 04h to
the value of the Accumulator, leaving the result in the Accumulator.
Since R4 is really Internal RAM 04h, the above instruction effectively
accomplished the same thing.

Bit Memory

The 8051, being a communicationsoriented microcontroller, gives the user

the ability to access a number of bit
variables. These variables may be either
1 or 0.
There are 128 bit variables available to
the user, numberd 00h through 7Fh. The
user may make use of these variables
with commands such as SETB and CLR.

Special Function Register

(SFR) Memory

Special Function Registers (SFRs) are

areas of memory that control specific
functionality of the 8051 processor.

For example, four SFRs permit access to

the 8051s 32 input/output lines.
Another SFR allows a program to read or
write to the 8051s serial port.
Other SFRs allow the user to set the serial
baud rate, control and access timers, and
configure the 8051s interrupt system.

Memory Mapped I/O and Port

Mapped I/O

Memory-mapped I/O uses the same address bus to

address both memory and I/O devices, and the CPU
instructions used to access the memory are also used
for accessing devices.
In order to accommodate the I/O devices, areas of the
CPU's addressable space must be reserved for I/O.
Port-mapped I/O uses a special class of CPU instructions
specifically for performing I/O.
Generally found on Intel microprocessors, specifically
the IN and OUT instructions which can read and write
one to four bytes (outb, outw, outl) to an I/O device.
I/O devices have a separate address space from general
memory, either accomplished by an extra "I/O" pin on
the CPU's physical interface, or an entire bus dedicated
to I/O.

What are SFRs ?

The 8051 is a flexible microcontroller with a relatively

large number of modes of operations.
The program may inspect and/or change the operating
mode of the 8051 by manipulating the values of the
8051's Special Function Registers (SFRs).
SFRs are accessed as if they were normal Internal
RAM.
The only difference is that Internal RAM is from
address 00h through 7Fh whereas SFR registers exist
in the address range of 80h through FFh.
Each SFR has an address (80h through FFh) and a
name.

SFR Descriptions

P0 (Port 0, Address 80h, BitAddressable):

This is input/output port 0. Each bit of this SFR

corresponds to one of the pins on the
microcontroller.
For example, bit 0 of port 0 is pin P0.0, bit 7 is
pin P0.7.
Writing a value of 1 to a bit of this SFR will
send a high level on the corresponding I/O pin
whereas a value of 0 will bring it to a low level.

SFR Description

SP (Stack Pointer, Address 81h):

This is the stack pointer of the microcontroller.

This SFR indicates where the next value to be taken
from the stack will be read from in Internal RAM.
If you push a value onto the stack, the value will be
written to the address of SP + 1. That is to say, if SP
holds the value 07h, a PUSH instruction will push
the value onto the stack at address 08h.
This SFR is modified by all instructions which modify
the stack, such as PUSH, POP, LCALL, RET, RETI, and
whenever interrupts are provoked by the
microcontroller.

SFR Description

DPL/DPH (Data Pointer Low/High,

Addresses 82h/83h):

The SFRs DPL and DPH work together to

represent a 16-bit value called the Data Pointer.
The data pointer is used in operations regarding
external RAM and some instructions involving
code memory.
Since it is an unsigned two-byte integer value,
it can represent values from 0000h to FFFFh (0
through 65,535 decimal).

SFR Description

PCON (Power Control, Addresses

87h):

The Power Control SFR is used to control the

8051's power control modes.
Certain operation modes of the 8051 allow the
8051 to go into a type of "sleep" mode which
requires much less power. These modes of
operation are controlled through PCON.
Additionally, one of the bits in PCON is used to
double the effective baud rate of the 8051's
serial port.

SFR Description

TCON (Timer Control, Addresses 88h,

Bit-Addressable):

The Timer Control SFR is used to configure and

modify the way in which the 8051's two timers
operate.
This SFR controls whether each of the two timers is
running or stopped and contains a flag to indicate
that each timer has overflowed.
Additionally, some non-timer related bits are
located in the TCON SFR. These bits are used to
configure the way in which the external interrupts
are activated and also contain the external
interrupt flags which are set when an external
interrupt has occurred.

SFR Description

TMOD (Timer Mode, Addresses 89h):

The Timer Mode SFR is used to configure the

mode of operation of each of the two timers.
Using this SFR your program may configure
each timer to be a 16-bit timer, an 8-bit
autoreload timer, a 13-bit timer, or two separate
timers.
Additionally, you may configure the timers to
only count when an external pin is activated or
to count "events" that are indicated on an
external pin.

SFR Description

TL0/TH0 (Timer 0 Low/High,

Addresses 8Ah/8Ch):

These two SFRs, taken together,

represent timer 0.
Their exact behavior depends on how
the timer is configured in the TMOD
SFR; however, these timers always
count up.

SFR Description

TL1/TH1 (Timer 1 Low/High,

Addresses 8Bh/8Dh):

These two SFRs, taken together,

represent timer 1.
Their exact behavior depends on how
the timer is configured in the TMOD
SFR; however, these timers always
count up.

SFR Description

P1 (Port 1, Address 90h, BitAddressable):

This is input/output port 1.

Each bit of this SFR corresponds to one of the
pins on the microcontroller.
For example, bit 0 of port 1 is pin P1.0, bit 7 is
pin P1.7.
Writing a value of 1 to a bit of this SFR will
send a high level on the corresponding I/O pin
whereas a value of 0 will bring it to a low level.

SFR Description

SCON (Serial Control, Addresses

98h, Bit-Addressable):

The Serial Control SFR is used to

configure the behavior of the 8051's onboard serial port.
This SFR controls the baud rate of the
serial port, whether the serial port is
activated to receive data, and also
contains flags that are set when a byte
is successfully sent or received.

SFR Description

SBUF (Serial Control, Addresses 99h):

The Serial Buffer SFR is used to send and

receive data via the on-board serial port.
Any value written to SBUF will be sent out the
serial port's TXD pin. Likewise, any value which
the 8051 receives via the serial port's RXD pin
will be delivered to the user program via SBUF.
In other words, SBUF serves as the output port
when written to and as an input port when read
from.

SFR Description

P2 (Port 2, Address A0h, BitAddressable):

This is input/output port 2.

Each bit of this SFR corresponds to one of the
pins on the microcontroller.
For example, bit 0 of port 2 is pin P2.0, bit 7 is
pin P2.7.
Writing a value of 1 to a bit of this SFR will
send a high level on the corresponding I/O pin
whereas a value of 0 will bring it to a low level.

SFR Description

IE (Interrupt Enable, Addresses A8h):

The Interrupt Enable SFR is used to enable

and disable specific interrupts.
The low 7 bits of the SFR are used to
enable/disable the specific interrupts, where
as the highest bit is used to enable or disable
ALL interrupts.
Thus, if the high bit of IE is 0 all interrupts are
disabled regardless of whether an individual
interrupt is enabled by setting a lower bit.

SFR Description

P3 (Port 3, Address B0h, BitAddressable):

This is input/output port 3.

Each bit of this SFR corresponds to one of the
pins on the microcontroller.
For example, bit 0 of port 3 is pin P3.0, bit 7 is
pin P3.7.
Writing a value of 1 to a bit of this SFR will
send a high level on the corresponding I/O pin
whereas a value of 0 will bring it to a low level.

SFR Description

IP (Interrupt Priority, Addresses B8h, BitAddressable):

The Interrupt Priority SFR is used to specify the relative

priority of each interrupt.
On the 8051, an interrupt may either be of low (0) priority
or high (1) priority.
An interrupt may only interrupt interrupts of lower priority.
For example, if we configure the 8051 so that all interrupts
are of low priority except the serial interrupt, the serial
interrupt will always be able to interrupt the system, even
if another interrupt is currently executing. However, if a
serial interrupt is executing no other interrupt will be able
to interrupt the serial interrupt routine since the serial
interrupt routine has the highest priority.

SFR Description

PSW (Program Status Word, Addresses

D0h, Bit-Addressable):

The Program Status Word is used to store a

number of important bits that are set and cleared
by 8051 instructions.
The PSW SFR contains the carry flag, the auxiliary
carry flag, the overflow flag, and the parity flag.
Additionally, the PSW register contains the register
bank select flags which are used to select which of
the "R" register banks are currently selected.

SFR Description

ACC (Accumulator, Addresses E0h, BitAddressable):

The Accumulator is one of the most-used SFRs

on the 8051 since it is involved in so many
instructions.
The Accumulator resides as an SFR at E0h,
which means the instruction MOV A,#20h is
really the same as MOV E0h,#20h. However, it
is a good idea to use the first method since it
only requires two bytes whereas the second
option requires three bytes.

SFR Description

B (B Register, Addresses F0h,

Bit-Addressable):

The "B" register is used in two

instructions: the multiply and divide
operations.
The B register is also commonly used
by programmers as an auxiliary
register to temporarily store values.

Addressing Modes.

The CPU can access the data in

various ways which is called as
addressing modes.

Immediate
Register
Direct
Register Indirect
Indexed

Addressing Modes.

Immediate Addressing

Immediate addressing is so-named because the value

to be stored in memory immediately follows the
operation code in memory. That is to say, the instruction
itself dictates what value will be stored in memory.
For example, the instruction:

MOV A,#20h
This instruction uses Immediate Addressing because the
Accumulator will be loaded with the value that
immediately follows; in this case 20 (hexidecimal).

Immediate addressing is very fast since the value to be

loaded is included in the instruction. However, since the
value to be loaded is fixed at compile-time it is not very
flexible.

Addressing Modes.

Register Addressing Mode

Register addressing mode involves the

use of registers to hold the data to be
manipulated.
Example of register addressing mode

MOV A,R0
MOV R2,A

Here is source and destination registers

must match the size.

Addressing Modes.

Direct Addressing

Direct addressing is so-named because the value to

be stored in memory is obtained by directly retrieving
it from another memory location. For example:

MOV A,30h
This instruction will read the data out of Internal RAM
address 30 (hexidecimal) and store it in the Accumulator.

Direct addressing is generally fast since, although the

value to be loaded isnt included in the instruction, it
is quickly accessable since it is stored in the 8051s
Internal RAM.
It is also much more flexible than Immediate
Addressing since the value to be loaded is whatever
is found at the given address--which may be variable.

Addressing Modes.

Indirect Addressing

Indirect addressing is a very powerful addressing mode which in

many cases provides an exceptional level of flexibility. Indirect
addressing is also the only way to access the extra 128 bytes of
Internal RAM found on an 8052.
Indirect addressing appears as follows:

MOV A,@R0
This instruction causes the 8051 to analyze the value of the R0
register. The 8051 will then load the accumulator with the value from
Internal RAM which is found at the address indicated by R0.

For example, lets say R0 holds the value 40h and Internal RAM
address 40h holds the value 67h. When the above instruction is
executed the 8051 will check the value of R0. Since R0 holds
40h the 8051 will get the value out of Internal RAM address 40h
(which holds 67h) and store it in the Accumulator. Thus, the
Accumulator ends up holding 67h.
Indirect addressing always refers to Internal RAM; it never refers
to an SFR.

Addressing Modes.

Indexed Addressing Mode

This mode is widely used in accessing

data elements of look-up table entries
located in the program ROM space of
the 8051.
The instruction used for this purpose
is MOVC A,@A + DPTR

Registers
A
B
R0

DPTR

DPH

DPL

R1
R2

PC

PC

R3
R4
R5
R6
R7
Some 8-bitt Registers of
the 8051

Some 8051 16-bit Register

Programming
Microcontrollers

Why Assembly ?

What is a Assembly
Language ?

Assembler and Compiler

Integrated Development
Environment (IDE)

IDE

IDE

IDE

IDE

Keil uVision

Assembly Instructions

In assembly the instruction is made up of

Opcode
Operand

The first byte of an instruction is known as the opcode

(operation code) because this is the byte that is
decoded by the processor - from this code the
processor can work out what operation it must
perform.
For a one-byte instruction there is only the opcode.
For a two-byte instruction the second byte is the
operand. The operand can be data or an 8-bit address.
For a three-byte instruction the second and third bytes
make up the operand.

Types of Instructions

Depending on operation they

perform, all instructions are divided
in several groups:

Arithmetic Instructions
Branch Instructions
Data Transfer Instructions
Logic Instructions
Bit-oriented Instructions

PSW Register

PSW Register

Parity Bit (P)

The parity bit reflects the number of 1s in the

accumulator (A).
If the Accumulator contains an odd number of
1s, then P = 1
If the Accumulator contains an even number of
1s, then P = 0
It is mainly used during data transmit and
receive via serial communication.

Bit 1. This bit is intended to be used in

the future versions of microcontrollers.

PSW Register

OV, the Overflow flag

This flag is set whenever the result of

a signed number operation is too
large, causing the high order bit to
overflow into the sign bit.

PSW Register

AC, the auxiliary carry flag

If there is a carry from bit 3 to bit 4 during an

ADD or SUB operation, this bit is set.
This flag is used by instructions that perform
BCD arithmetic.

CY, the carry flag

This flag is set whenever there is a carry out

from the bit 7.
This flag bit is affected after an 8-bit addition
and subtraction.
The carry flag is used to detect errors in
unsigned arithmetic operations.

8051 Directives

ORG (origin)
The ORG directive is used to indicate the
beginning of the address. The number that
comes after ORG can be either in hex or in
decimal. If the number is not followed by H,
it is decimal and the assembler will convert
it to hex. Some assemblers use ". ORG"
(notice the dot) instead of "ORG" for the
origin directive. Check your assembler.
E.g. ORG 500H

8051 Directives

END directive
Another important pseudocode is the END
directive. This indicates to the assembler the
end of the source (asm) file. The END directive
is the last line of an 8051 program, meaning
that in the source code anything after the END
directive is ignored by the assembler. Some
assemblers use ". END" (notice the dot) instead
of "END".

8051 Directives

EQU (equate)
This is used to define a constant without
occupying a memory location. The EQU
directive does not set aside storage for a data
item but associates a constant value with a
data label so that when the label appears in
the program, itp constant value will be
substituted for the label. The following uses
EQU for the counter constant and then the
constant is used to load the R3 register.

8051 Directives

DB (define byte)

The DB directive is the most widely used

data directive in the assembler. It is used
to define the 8-bit data. When DB is used
to define data, the numbers can be in
decimal, binary, hex, or ASCII formats.
The DB directive is the only directive that
can be used to define ASCII strings larger
than two characters; therefore, it should
be used for all ASCII data definitions.

8051 Directives

Label Rules

First, each label name must be unique.

The names used for labels in Assembly
language programming consist of alphabetic
letters in both uppercase and lowercase, the
digits 0 through 9, and the special characters
question mark (?), period (.), at (@), underline
(_), and dollar sign ($).
The first character of the label must be an
alphabetic character. In other words it cannot
be a number.
Every assembler has some reserved words that
must not be used as labels in the program.

DJNZ

Operation:DJNZ
Function:Decre
ment and Jump
if Not Zero
Syntax:DJNZ
register,reladdr

DJNZ

DJNZ decrements the value of register by 1.

If the initial value of register is 0,
decrementing the value will cause it to reset
to 255 (0xFF Hex).
If the new value of register is not 0 the
program will branch to the address
indicated by relative addr.
If the new value of register is 0 program
flow continues with the instruction following
the DJNZ instruction.

DJNZ example

JZ

Operation:JZ
Function:Jump if
Accumulator Zero
Syntax:JNZ
reladdr

JNZ

Operation:JNZ
Function:Jump if
Accumulator Not
Zero
Syntax:JNZ
reladdr

CJNE

Operation:CJNE
Function:Compar
e and Jump If Not
Equal
Syntax:CJNE
operand1,operand
2,reladdr

CJNE

CJNE compares the value of operand1

and operand2 and branches to the
indicated relative address if operand1
and operand2 are not equal.
If the two operands are equal program
flow continues with the instruction
following the CJNE instruction.
The Carry bit (C) is set if operand1 is
less than operand2, otherwise it is
cleared.

CJNE
REPEAT:

MOV A,TH0
MOV R0,TL0
CJNE A,TH0,REPEAT

JC

Operation:JC
Function:Jump if
Carry Set
Syntax:JC reladdr
JC will branch to the
address indicated by
reladdr if the Carry Bit
is set.
If the Carry Bit is not
set program execution
continues with the
instruction following
the JC instruction.

JC
JC example
MOV C,P1.4
JC LINE1

JNC

Operation:JNC
Function:Jump if
Carry Not Set
Syntax:JNC reladdr
JNC branches to the
address indicated by
reladdr if the carry bit
is not set.
If the carry bit is set
program execution
continues with the
instruction following
the JNB instruction.

JNC example
JNC example
MOV C,P1.4
JNC LINE1

JB

Operation:JB
Function:Jump if Bit Set
Syntax:JB bit addr, reladdr
JB branches to the address
indicated by reladdr if the
bit indicated by bit addr is
set.
If the bit is not set program
execution continues with
the instruction following
the JB instruction.
JB 45h,LABEL1

JNB

Operation:JNB
Function:Jump if Bit Not
Set
Syntax:JNB bit
addr,reladdr
JNB will branch to the
address indicated by
reladdress if the indicated
bit is not set.
If the bit is set program
execution continues with
the instruction following
the JNB instruction.
JNB 45h,LABEL1

JBC

Operation:JBC
Function:Jump if Bit Set and
Clear Bit
Syntax:JBC bit addr, reladdr
JBC will branch to the
address indicated by reladdr
if the bit indicated by bit
addr is set. Before branching
to reladdr the instruction will
clear the indicated bit.
If the bit is not set program
execution continues with the
instruction following the JBC
instruction.
JBC 45h, LABEL1

LOOP and JUMP Instructions

JZ

Jump if A=0

JNZ

Jump if A/=0

DJNZ

Decrement and jump if A/=0

CJNE A,byte

Jump if A/=byte

CJNE reg,#data

Jump if byte/=#data

JC

Jump if CY=1

JNC

Jump if CY=0

JB

Jump if bit=1

JNB

Jump if bit=0

JBC

Jump if bit=1 and clear bit