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Superscalar Vs Superpipeline Processor

Superscalar and super pipeline are approaches to improve processor performance by executing multiple instructions in parallel. Superscalar executes independent instructions simultaneously in multiple pipelines, while super pipeline breaks pipeline stages into smaller stages to reduce clock period and increase instructions in flight. Both aim to improve scalar operation performance, but superscalar executes one stage per clock in each pipeline while super pipeline can perform two stages per clock. Super pipeline benefits from more parallelism but has potential for more stalls due to dependencies between instructions in flight.

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693 views

Superscalar Vs Superpipeline Processor

Superscalar and super pipeline are approaches to improve processor performance by executing multiple instructions in parallel. Superscalar executes independent instructions simultaneously in multiple pipelines, while super pipeline breaks pipeline stages into smaller stages to reduce clock period and increase instructions in flight. Both aim to improve scalar operation performance, but superscalar executes one stage per clock in each pipeline while super pipeline can perform two stages per clock. Super pipeline benefits from more parallelism but has potential for more stalls due to dependencies between instructions in flight.

Uploaded by

Normalia Samian
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPTX, PDF, TXT or read online on Scribd
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Topic

Super scalar
&
Super Pipeline
approach to processor

Superscalar
1st invented in 1987
Superscalar processor executes multiple
independent instructions in parallel.
Common instructions (arithmetic, load/store etc)
can be initiated simultaneously and executed
independently.
Applicable to both RISC & CISC, but usually in RISC

Why Superscalar
Most operations are on scalar quantities
Superscalar was designed to improve the
performance of these operations by
executing them concurrently in multiple
pipelines

Superscalar Performance
In superscalar multiple independent instruction pipelines
are used. Each pipeline consists of multiple stages, so that
each pipeline can handle multiple instructions at a time.
A superscalar processor typically fetches multiple
instructions at a time and then attempts to find nearby
instructions that are independent of one another and can
therefore be executed in parallel.
If the input to one instruction depends on the output of a
preceding instruction, then the latter instruction cannot
complete execution at the same time or before the former
instruction.

General Superscalar
Organization
The configuration below, supports the
parallel execution of two integer
operations, two floating point operations
and one memory operation.

Super Pipeline
Super-pipeline is an alternative approach
to achieve greater performance
1st invented in 1988
Many pipeline stages need less than half
a clock cycle

Super pipeline cont


Super-pipelining is the breaking of stages
of a given pipeline into smaller stages
(thus making the pipeline deeper) in an
attempt to shorten the clock period and
thus enhancing the instruction
throughput by keeping more and more
instructions in flight at a time.

Super pipeline Performance


The performance is shown below in the
figure:

Superscalar versus
super-pipeline
Simple pipeline system
performs only one pipeline
stage per clock cycle
Super-pipeline system is
capable of performing two
pipeline stages per clock cycle
Superscalar performs only
one pipeline stage per clock
cycle in each parallel pipeline

Super pipeline benefit &


drawback
Benefits:
The major benefit of super-pipelining is the increase
in the number of instructions which can be in the
pipeline at one time and hence the level of
parallelism.
Drawbacks:
The larger number of instructions "in flight" (i.e., in
some part of the pipeline) at any time, increases the
potential for data dependencies to introduce stalls.

Limitations of superscalar
The superscalar approach depends on the
ability to execute multiple instructions in
parallel. The term Instruction-level
parallelism refers to the degree to which
the instructions of a program can be
executed in parallel.
A combination of compiler-based
optimization and hardware techniques can
be used to maximize instruction-level
parallelism.

Limitations to parallelism
Fundamental limitations to parallelism
True data dependency
Procedural dependency
Resource conflicts
Output dependency
Anti-dependency

Data dependency problem


The major problem of executing multiple
instructions in a scalar program is the
handling of data dependencies. If data
dependencies are not effectively handled,
it is difficult to achieve an execution rate
of more than one instruction per clock
cycle.

Any Question

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