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    Soc Verif Udemy Lec 5 Methodologies Sim Formal

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    renju91
    The document discusses different verification methods including simulation-based verification, formal verification using equivalence checking and model checking, semi-formal verification, and assertion-based verification. Simulation-based verification uses a testbench and simulator to generate test cases while formal verification exhaustively checks all states mathematically. Semi-formal verification combines simulation and formal techniques. Assertion-based verification specifies intended design behavior to improve verification and debug.

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    Soc Verif Udemy Lec 5 Methodologies Sim Formal

    Uploaded by

    renju91
    79 views14 pages
    The document discusses different verification methods including simulation-based verification, formal verification using equivalence checking and model checking, semi-formal verification, and assertion-based verification. Simulation-based verification uses a testbench and simulator to generate test cases while formal verification exhaustively checks all states mathematically. Semi-formal verification combines simulation and formal techniques. Assertion-based verification specifies intended design behavior to improve verification and debug.

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    SOC verification from verification academy

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    The document discusses different verification methods including simulation-based verification, formal verification using equivalence checking and model checking, semi-formal verification, and assertion-based verification. Simulation-based verification uses a testbench and simulator to generate test cases while formal verification exhaustively checks all states mathematically. Semi-formal verification combines simulation and formal techniques. Assertion-based verification specifies intended design behavior to improve verification and debug.

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    © All Rights Reserved
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    Download as pptx, pdf, or txt
    79 views14 pages

    Soc Verif Udemy Lec 5 Methodologies Sim Formal

    Uploaded by

    renju91
    The document discusses different verification methods including simulation-based verification, formal verification using equivalence checking and model checking, semi-formal verification, and assertion-based verification. Simulation-based verification uses a testbench and simulator to generate test cases while formal verification exhaustively checks all states mathematically. Semi-formal verification combines simulation and formal techniques. Assertion-based verification specifies intended design behavior to improve verification and debug.

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    You are on page 1of 14

    Verification Methods

    Simulation Based
    Formal Verification
    Semi Formal Verificaion
    Assertions

    Verification with System Verilog 8/2/2017 1


    Simulation Based Verification

    1 Simulator
    0 0
    1 1
    1 1 ?
    =
    Test
    Vector Implementation
    Generator
    1 1
    0 0 checker
    1

    8/2/2017 Verification with System Verilog 2


    Formal Verification

    What is Formal Verification?


    It is the method by which we prove or disprove a design
    implementation against a formal specification or
    property
    Uses mathematical reasoning
    It algorithmically and exhaustively explores all
    possible input values over time.
    works well for small designs where the number of
    inputs, outputs and states is small

    8/2/2017 Verification with System Verilog 3


    Formal - Equivalence Checking

    Equivalence checker checks the logical equivalence of


    the final version of the netlist with the RTL

    Equivalence checker checks for functional equivalence


    and not functional correctness

    8/2/2017 Verification with System Verilog 4


    Formal - Equivalence Checking

    Design
    RTLC / GatesC
    Implementation
    Step 2
    Reference/Golden
    Design
    Design Equivalence
    RTLA / GatesA Checker
    Implementation
    Reference/Golden Step C
    A == B ?
    Design

    Design
    RTLB / GatesB

    Target/Modified
    Design

    8/2/2017 Verification with System Verilog 5


    Formal Model Checking

    Exhaustive search of FSM for state/property


    violations
    Two inputs to the algorithm
    A finite state transition system (FSM) representing
    the implementation
    A formal property representing the specification

    The algorithm checks whether the FSM models the


    property correctly
    8/2/2017 Verification with System Verilog 6
    Formal Model Checking

    Formal
    G(p F q)
    Property
    PASS

    MC

    p
    algorithm
    p

    q FAIL q

    counterexample
    FSM model

    8/2/2017 Verification with System Verilog 7


    Advantages of Formal Verification

    Covers exhaustive state space, something difficult to


    achieve by simulations
    Does not require generation of input stimulus, since
    exhaustive stimulus can be generated automatically by tool
    No need to generate expected output sequences
    Correctness of design guaranteed mathematically

    Verification with System Verilog 8/2/2017 8


    Disadvantages

    Scalability
    each added flop doubles the state space. Limited to
    designs with small state spaces like interfaces, small FSMs.
    What properties to verify?
    For some methods, needs the specification to be
    translated into properties to verify that properties hold
    under all inputs and all states.

    Verification with System Verilog 8/2/2017 9


    Semi-Formal Verification

    Best of both worlds (Simulation & Formal)


    Use simulation to reach interesting states in the design
    Then fork off formal to do exhaustive analysis around the
    interesting state
    Finds bugs sitting deep in the design
    Useful for bug hunting

    8/2/2017 Verification with System Verilog 10


    Assertion Based Verification

    What is Assertion?
    An Assertion is a statement about a designs intended
    behavior ,which must be verified
    Benefits of Assertions:
    Improving Observability and debug ability
    Improving integration through correct usage checking
    Improving verification efficiency
    Improving communication through documentation
    Useful in both static and dynamic simulations

    8/2/2017 Verification with System Verilog 11


    Assertion Types

    Immediate Assertion
    assert (A == B) else $error("It's gone wrong");

    Concurrent Assertion

    property p1;
    @(posedge clk) disable iff (Reset) not b ##1 c;
    endproperty
    assert property (p1) else $error(B ##1C failed);

    Verification with System Verilog 8/2/2017 12


    Assertion Based Verification

    Using Assertions in Formal Verification


    Formally specify all functional requirements and behavior
    of design in a language
    Use a procedure to prove that all specified properties hold
    true
    Using Assertions in Dynamic Simulation
    Specified properties are useful as checks and for coverage

    8/2/2017 Verification with System Verilog 13


    Summary

    Simulation based Verification is used to


    find most bugs
    Formal verification is useful in select areas
    Assertions are a great value add

    Verification with System Verilog 8/2/2017 14

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