Data Converters Successive Approximation ADC Professor Y.

Chiu
EECT 7327 Fall 2014

Successive Approximation
(SA) ADC

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Data Converters Successive Approximation ADC Professor Y. Chiu
EECT 7327 Fall 2014

Successive Approximation ADC

Vi VX

VDAC b1

...

...
DAC Do

bN
Shift
Register

Binary search algorithm N*Tclk to complete N bits

Conversion speed is limited by comparator, DAC, and digital logic
(successive approximation register or SAR)

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Data Converters Successive Approximation ADC Professor Y. Chiu
EECT 7327 Fall 2014

Binary Search Algorithm

VDAC
Vi
VFS

VFS
2

1 0 0 1 1 0
0 t
MSB LSB
Tclk

DAC output gradually approaches the input voltage

Comparator differential input gradually approaches zero

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Data Converters Successive Approximation ADC Professor Y. Chiu
EECT 7327 Fall 2014

Charge Redistribution SA ADC

1e

VX

SAR
8C 4C 2C C C

Do

VR
1 1 1 1 1
Vi

4-bit binary-weighted capacitor array DAC

Capacitor array samples input when 1 is asserted (bottom-plate)
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Data Converters Successive Approximation ADC Professor Y. Chiu
EECT 7327 Fall 2014

Charge Redistribution (MSB)

1e

VX

SAR
8C 4C 2C C C

Do

VR
1 1 1 1 1
Vi

VR 8C - Vi 16C VR
Vi 16C = VR - VX C4 - VX C3 + C2 + C1 + C0 VX - Vi
16C 2

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Data Converters Successive Approximation ADC Professor Y. Chiu
EECT 7327 Fall 2014

Comparison (MSB)
VX
1
0 t

Sample 1
MSB

VR
MSB TEST : V X Vi
2

If VX < 0, then Vi > VR/2, and MSB = 1, C4 remains connected to VR

If VX > 0, then Vi < VR/2, and MSB = 0, C4 is switched to ground

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Data Converters Successive Approximation ADC Professor Y. Chiu
EECT 7327 Fall 2014

Charge Redistribution (MSB-1)

1e

VX

SAR
8C 4C 2C C C

Do

VR
1 1 1 1 1
Vi

VR 12C Vi 16C 3
Vi 16C VR VX 12C VX 4C VX VR Vi
16C 4

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Data Converters Successive Approximation ADC Professor Y. Chiu
EECT 7327 Fall 2014

Comparison (MSB-1)
VX
1 2
0 t

Sample 1 0
MSB

3
MSB -1 TEST : VX VR Vi
4

If VX < 0, then Vi > 3VR/4, and MSB-1 = 1, C3 remains connected to VR

If VX > 0, then Vi < 3VR/4, and MSB-1 = 0, C3 is switched to ground

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Data Converters Successive Approximation ADC Professor Y. Chiu
EECT 7327 Fall 2014

Charge Redistribution (Other Bits)

1e

VX

SAR
8C 4C 2C C C

Do

VR
1 1 1 1 1
Vi

Test completes when all four bits are determined w/ four charge
redistributions and comparisons

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Data Converters Successive Approximation ADC Professor Y. Chiu
EECT 7327 Fall 2014

After Four Clock Cycles

VX
1 2 3 4
0 t

Sample 1 0 0 1
MSB LSB

Usually, half Tclk is allocated for charge redistribution and half for
comparison + digital logic
VX always converges to 0 (Vos if comparator has nonzero offset)

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Data Converters Successive Approximation ADC Professor Y. Chiu
EECT 7327 Fall 2014

Summing-Node Parasitics
1e CP

Vos
SAR
8C 4C 2C C C

Do

VR
1 1 1 1 1
Vi

If Vos = 0, CP has no effect eventually; otherwise, CP attenuates VX

Auto-zeroing can be applied to the comparator to reduce offset
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Data Converters Successive Approximation ADC Professor Y. Chiu
EECT 7327 Fall 2014

Summary of SA ADC
Power efficiency only comparator consumes DC power
DAC nonlinearity limits the INL and DNL of the SA ADC
N-bit precision requires N-bit matching from the cap array
Calibration can be performed to remove mismatch errors (Lee, JSSC84)
Comparator offset Vos introduces an input-referred offset ~ (1+CP/Cj)*Vos
CP in general has little effect on the conversion (VX0 at the end of the
search); however, VX is always attenuated due to charge sharing of CP
Binary search is sensitive to intermediate errors made during search if an
intermediate decision is wrong, the digitization process cannot recover
DAC must settle into LSB bound within the time allowed
Comparator offset must be constant (no hysteresis or time-dependent offset)
Non-binary search algorithm can be used (Kuttner, ISSCC02)

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Data Converters Successive Approximation ADC Professor Y. Chiu
EECT 7327 Fall 2014

References
1. J. L. McCreary and P. R. Gray, JSSC, pp. 371-379, issue 6, 1975.
2. R. E. Suarez, P. R. Gray, and D. A. Hodges, JSSC, pp. 379-385, issue 6, 1975.
3. H.-S. Lee, D. A. Hodges, and P. R. Gray, JSSC, pp. 813-819, issue 6, 1984.
4. M. de Wit, K.-S. Tan, and R. K. Hester, JSSC, pp. 455-461, issue 4, 1993.
5. C. M. Hammerschmied and H. Qiuting, JSSC, pp. 1148-1157, issue 8, 1998.
6. S. Mortezapour and E. K. F. Lee, JSSC, pp. 642-646, issue 4, 2000.
7. G. Promitzer, JSSC, pp. 1138-1143, issue 7, 2001.
8. F. Kuttner, ISSCC 2002, pp. 176-177.
9. S. M. Chen and R. W. Brodersen, JSSC, pp. 2350-2359, issue 2, 2006.
10. N. Verma and A. Chandrakasan, ISSCC 2006, pp. 222-223.
11. G. Van der Plas et al., ISSCC 2008, pp. 242-243.
12. M. van Elzakker et al., ISSCC 2008, pp. 244-245.
13. W. Liu, P. Huang, and Y. Chiu , JSSC, pp. 2661-2672, issue 11, 2011.

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