INTRODUCTION TO

EMBEDDED SYSTEMS
1

A R M P R O C ESSO R
I N TE R R UP T P R O C ESSI N G

Created by Mr. THOMAS KWANTWI 4/28/2018

 ARM Exceptions: Review
2

Exception Mode

Fast Interrupt Request FIQ

Interrupt Request IRQ

SWI and Reset SVC

Pre-fetch Abort & Data Abort Abort

Undefined instruction undefined

Created by Mr. THOMAS KWANTWI 4/28/2018

 When Exception Occurs…
3

 Exception causes mode change and

 Saves the CPSR to the SPSR of the exception mode
 Saves the PC to the lr of the exception mode
 Sets the CPSR to the exception mode
 Sets PC to the address of the exception handler

Created by Mr. THOMAS KWANTWI 4/28/2018

 Vector Table
4

 Vector table – a table of addresses that the ARM core

branches
 Fixed offset for each type of exception
 These addresses contain instructions of one of the
following forms:
 B<address>: branching relative to PC
 LDR PC, [PC, #offset]: loads handler address from
memory to PC
 MOV PC, #immediate: loads immediate value into
PC
Created by Mr. THOMAS KWANTWI 4/28/2018
 Exception Priorities
5

Exceptions Priority I bit F bit

Reset 1 1 1

Data abort 2 1 -

FIQ 3 1 1

IRQ 4 1 -

Pre-fetch abort 5 1 -

SWI 6 1 -

Undefined 6 1 -
instructions

Created by Mr. THOMAS KWANTWI 4/28/2018

 Exception Handlers
6

 Reset handler
 Initializes the system, setting up stack pointers,
memory, external interrupt sources before enabling
IRQ or FIQ
 Code should be designed to avoid further triggering
of exceptions
 Data Abort
 Occurs when memory controller indicates that an
invalid memory address has been accessed
 An FIQ exception can be raised within data abort
handler
Created by Mr. THOMAS KWANTWI 4/28/2018
 Exception Handlers (contd.)
7

 FIQ
 Occurs when an external peripheral generates the FIQ
input signal
 Core disables both FIQ and IRQ interrupts
 IRQ
 Occurs when an external device generates the IRQ input
signal
 IRQ handler will be entered if neither an FIQ exception
or Data abort exception occurs
 On entry IRQ exception is disabled and should remain
disabled for the handler if not enabled by the handler
Created by Mr. THOMAS KWANTWI 4/28/2018
 Exception Handlers (contd.)
8

 Pre-fetch Abort
 Occurs when an attempt to fetch an instruction
results in memory fault
 FIQ exception can be serviced
 Undefined instruction
 Occurs when an instruction is not in the ARM or
Thumb instruction
 SWI and undefined instruction have the same level
of priority because they cannot occur together

Created by Mr. THOMAS KWANTWI 4/28/2018

 Returning from Exception Handler
9

 Exception handler must not corrupt Ir

 After servicing is complete, return to normal
execution occurs
 By moving the correct value of link register r14 into
PC
 By restoring CPSR from SPSR

Created by Mr. THOMAS KWANTWI 4/28/2018

 Interrupt Assignment
10

 An interrupt controller connects multiple external

interrupts to either FIQ or IRQ
 IRQ are normally assigned to general purpose
interrupts
 Examples: periodic timer interrupt to force a context
switch
 FIQ is reserved for an interrupt source which
requires fast response time

Created by Mr. THOMAS KWANTWI 4/28/2018

 Interrupt Latency
11

 Hardware and software latency

 Software methods to reduce latency
 Nested handler which allows further interrupts to
occur even when servicing an existing interrupt by
re-enabling the interrupts inside service routine
 Program interrupt controller to ignore interrupts of
the same or lower priority
o Higher priority interrupts will have lower average
latency

Created by Mr. THOMAS KWANTWI 4/28/2018

 Stack Organization
12

 For each processor mode stack has to be set up

 To be done every time processor is reset
o Change to each mode by storing CPSR bit pattern
and initialize SP
 Design decisions
 Location and mode (descending stack is common)
 Size
o Nested interrupt handler requires larger stack

Created by Mr. THOMAS KWANTWI 4/28/2018

 ARM I/O System
13

 Handles all I/O devices using memory mapped I/O

 Interrupt support:
 fast interrupt
 Normal interrupt
 DMA Support
 Large bandwidth data transfer

Created by Mr. THOMAS KWANTWI 4/28/2018

 Details on ARM Core
14

ARM CPU Core

Processor Core + Cache + MMU

Created by Mr. THOMAS KWANTWI 4/28/2018

 ARM 7 Processor Core
15

 Low-end ARM core for applications like mobile

phones
 TDMI
 T: Thumb
 D: On chip debug support enabling processor to halt
in response to debug request
 M: Enhances multiplier, yield a full 64-bit result
 I: Embedded ICE Hardware
 Von Neumann architecture
 3 stage pipeline, CPI ~1.9

Created by Mr. THOMAS KWANTWI 4/28/2018

 ARM7TDMI organization
16
s can c hain 2
extern0 Embedded s can c hain 0
extern1
ICE
opc, r/w,
mreq, trans,
mas[1:0]
A[31: 0] process or other
core s ignals

D[ 31:0] s can c hain 1

Din[ 31:0]
bu s JTAG TAP
Dout [31:0]
splitter controller

TCK TMSTRST TDI TDO

Created by Mr. THOMAS KWANTWI 4/28/2018
 ARM single-cycle instruction pipeline
operation
17

 At any time, 3 different instructions may occupy each

of these stages, so the hardware in each stage has to
be capable of independent operations
 When the processor is executing data processing
instructions, the latency = 3 cycles and the
throughput=1 instruction cycle
 When accessing r15 (PC), R15 = address of current
instruction +8
 Before returning from exception handler proper
adjustment of lr value is required

Created by Mr. THOMAS KWANTWI 4/28/2018

 Pipeline Operation
18

 Not always cycle per instruction completion

-Example LDMIA r0, [r2,r3] (multiple load:
-2 register to load, instruction in execution for two
cycles
Execution of prefetched instruction delayed
 Branch , Subroutine call, Exceptions affect pipeline
efficiency

Created by Mr. THOMAS KWANTWI 4/28/2018

 The ARM7TDMI core interface signals
m c lk
19 A[ 31:0 ]
cloc k
control w ait
D in[ 31:0 ]
ec lk
configuration bi gend D out [31: 0]

irq D [31 :0] memory

interrupts ¼ q interfac e
is yn c bl [3:0 ]
r/w
initi aliz ation res et m a s [1: 0]
m re q
en in
en out se q
lo ck
en outi
ab e tra ns
al e MM U
m o de[4 :0] interfac e
bus ap e ab ort
control db e
tb e Tb it state
bu s en
hi ghz ARM7TDMI ta ps m [ 3:0]
bu s dis ir[ 3:0]
ec apc lk core td oen TAP
tc k1 information
db grq
tc k2
bre akp t
s c reg[ 3:0]
db gac k
exec dri ve bs
exte rn1 ec apc lk bs
exte rn0 ic apc lk bs
debug db gen hi ghz
ran geou t0 boundary
pc lk bs sc an
ran geou t1 rs t clk bs
db grqi
ex tensi on
s d inbs
c om m rx s d outb s
c om m t x s h clk bs
op c s h clk 2bs
coprocess or c pi
interfac e c pa TR ST
TC K JTAG
c pb
TMS controls
Vd d TD I
power Vs s TD O
Created by Mr. THOMAS KWANTWI 4/28/2018
 Interface signals
20
 Clock control
 All state change within the processor are controlled by mclk, the memory
clock
 Internal clock = mclk AND \wait
 eclk clock output reflects the clock used by the core
 Memory interface
 32-bit address A[31:0], bidirectional data bus D[31:0], separate data out
Dout[31:0], data in Din[31:0]
 seq indicates that the memory address will be sequential to that used in the
previous cycle

mreq s eq Cy cl e Us e
0 0 N Non-sequential memory access
0 1 S Sequential memory access
1 0 I Internal cycle – bus and memory inactive
1 1 C Coprocessor register transfer – memory inactive
Created by Mr. THOMAS KWANTWI 4/28/2018
 Interface signals (contd.)
21

 Lock indicates that the processor should keep the bus to ensure the
atomicity of the read and write phase of a SWAP instruction
 \r/w, read or write
 mas[1:0], encode memory access size – byte, half-word or word
 bl[3:0], externally controlled enables on latches on each of the 4 bytes
on the data input bus
 MMU interface
 \trans (translation control), 0: user mode, 1: privileged mode
 \mode[4:0], bottom 5 bits of the CPSR (inverted)
 Abort, disallow access
 State
 T bit, whether the processor is currently executing ARM or Thumb
instructions
 Configuration
 Bigend, big-endian or little-endian

Created by Mr. THOMAS KWANTWI 4/28/2018

 Interface signals (contd.)
22

Interrupt
 \fiq,
fast interrupt request, higher priority
 \irq, normal interrupt request

 isync, allow the interrupt synchronizer to be

passed
Initialization
 \reset, starts the processor from a known state,
executing from address 0000000016

Created by Mr. THOMAS KWANTWI 4/28/2018

 Memory Access
23
 The ARM7 is a Von Neumann, 0x1A
load/store architecture, i.e., 0x19
 Only 32 bit data bus for both inst. And 0x18
data.
0x17
 Only the load/store inst. (and SWP) 0x16
access memory.
0x15
 Memory is addressed as a 32 bit 0x14
address space 0x13
 Data type can be 8 bit bytes, 16 bit
half-words or 32 bit words, and may 0x12

be seen as a byte line folded into 4- 0x11

byte words
 Words must be aligned to 4 byte 0x10

boundaries, and half-words to 2 byte 0x0C

boundaries. 0x08

 Always ensure that memory controller 0x04

supports all three access sizes 0x00

Memory as words
Created by Mr. THOMAS KWANTWI 4/28/2018
 ARM Memory Interface
24

 Sequential (S cycle)
 (nMREQ, SEQ) = (0, 1)
 The ARM core requests a transfer to or from an address which is either the
same, or one word or one-half-word greater than the preceding address.
 Non-sequential (N cycle)
 (nMREQ, SEQ) = (0, 0)
 The ARM core requests a transfer to or from an address which is unrelated
to the address used in the preceding address.
 Internal (I cycle)
 (nMREQ, SEQ) = (1, 0)
 The ARM core does not require a transfer, as it performing an internal
function, and no useful pre-fetching can be performed at the same time
 Coprocessor register transfer (C cycle)
 (nMREQ, SEQ) = (1, 1)
 The ARM core wished to use the data bus to communicate with a
coprocessor, but does not require any action by the memory system.

Created by Mr. THOMAS KWANTWI 4/28/2018

 ARM9TDMI
25

 Harvard Architecture
 Increase available memory bandwidth
o Instruction memory interface
o Data memory interface
 Simultaneous access to instruction and data memory
 5 stage pipeline
 Fetch
 Decode
 Execute
 Buffer Data (access data memory or buffer)
 Write back
 Changes implemented to
 Increase CPI~1,5
 Improve maximum clock frequency

Created by Mr. THOMAS KWANTWI 4/28/2018

 DSP enhancements in ARM9E
26

 New instruction additions give architecture V5TE

 New 32x16 and 16x16 multiply and multiply-accumulate
instructions
 SMLAxy, SMLAWy, SMALxy, SMULxy, SMULWy
 Allows independent access to 16-bit halves of registers
o Gives efficient use of 32-bit bandwidth for packed 16-bit
operands
 Zero overhead fractional saturating arithmetic
 QADD, QSUB, QDADD, QDSUB
 Count leading zeros instruction
 CLZ for faster normalization and division
 Single cycle 32x16 multiply instructions

Created by Mr. THOMAS KWANTWI 4/28/2018

 Cached ARM7TDMI Macrocells
27

EmbeddedICE & JTAG CP15

ARM Core

Physical
Address
AMBA
MMU
Address
Virtual AMBA
Address Interface
AMBA
Inst. & data
Data

Write
Inst. & data cache
Buffer

Created by Mr. THOMAS KWANTWI 4/28/2018

 Simple ARM based System
28

 On-chip there will be an ARM core together with a

number of system dependant peripherals.
 Also required will be some form of interrupt controller
which receives interrupts from the peripherals and raised
the IRQ or FIQ input to the ARM as appropriate.
 This interrupt controller may also provide hardware
assistance for prioritizing interrupts.
 As far as memory is concerned there is likely to be some
(cheap) narrow off-chip ROM (or flash) used to store
most of the runtime data and perhaps some code copied
out of the flash.
 Then on-chip there may well be some 32-bit memory
used to store the interrupt handlers and perhaps stacks
Created by Mr. THOMAS KWANTWI 4/28/2018
 Example ARM-based System
29

16-bit RAM 32-bit RAM

Interrupt
Controller Peripherals
r

8-bit ROM
ARM Core

Created by Mr. THOMAS KWANTWI 4/28/2018

 ARM v5TEJ
30

 J: supports implementation of Java virtual machine

 Offering hardware and software acceleration for
optimized byte code execution

Created by Mr. THOMAS KWANTWI 4/28/2018

 ARM v6 Architecture
31

 SIMD (single instruction multiple data) instructions

for exploiting data parallelism
 High code density and low power
 By slicing up the existing 32-bit data path into four
8-bit and two 16-bit slices
 Sum of absolute difference instructions
 Dual 16x16 multiply
 Cryptographic multiplication
 Multiprocessing synchronization primitive

Created by Mr. THOMAS KWANTWI 4/28/2018

 Use of ARM Core
32

 ARM based products to market from manufacturers:

Atmel, Cirrus Logic, Intel, Samsung
 Most product based upon 7TDMI-core and 920T-
cores
 ARM is mostly used as a processor core in SOC and
ASICs
 There are a number of ASSP (application specific
standard product)available, for example,
communication applications
 Example: Philips VWS22100: ARM7 based GSM
base band chip

Created by Mr. THOMAS KWANTWI 4/28/2018

 Summary
33

 we have looked at exception processing

 Looked at pipeline architecture
 Discussed key aspects of ARM CPU core
 Next we look at DSP processors

Created by Mr. THOMAS KWANTWI 4/28/2018