DESIGN UNITS

 VHDL provides five different types of primary constructs, called

design units. They are
1. Entity declaration
2. Architecture body
3. Configuration declaration
4. Package declaration
5. Package body
 ENTITY DECLARATION
 The entity declaration describes the external view of the entity,
for example, the input and output signal names.
 The entity declaration specifies the name of the entity being
modeled and lists the set of interface ports.
 Ports are signals through which the entity communicates with
the other models in its external environment.
 Here is an example of an entity declaration for the half-adder
circuit
entity HALF_ADDER is
port (A, B: in BIT; SUM, CARRY: out BIT);
end HALF_ADDER;
-- This is a comment line
 The entity declaration does not specify anything about the
internals of the entity.
 It only specifies the name of the entity and the interface ports.
 ARCHITECTURE BODY
 The architecture body contains the internal description of the entity,
for example, as a set of interconnected components that represents
the structure of the entity, or as a set of concurrent or sequential
statements that represents the behavior of the entity.
 Each style of representation can be specified in a different
architecture body or mixed within a single architecture body.
 The internal details of an entity are specified by an architecture body
using any of the following modeling styles:
1. As a set of interconnected components (to represent structure),
2. As a set of concurrent assignment statements (to represent
dataflow),
3. As a set of sequential assignment statements (to represent be-
havior),
4. Any combination of the above three.
 The architecture body is composed of two parts: the declarative part
(before the keyword begin) and the statement part (after the keyword
begin).
 STRUCTURAL STYLE OF MODELING
 In the structural style of modeling, an entity is described as a set
of interconnected components.
 Such a model for the HALF_ADDER entity is described in an
architecture body as shown below:
architecture HA_STRUCTURE of HALF_ADDER is
component XOR2
port (X, Y: in BIT; Z: out BIT);
end component;
component AND2
port (L, M: in BIT; N: out BIT);
end component;
begin
X1: XOR2 port map (A, B, SUM);
A1: AND2 port map (A, B, CARRY);
end HA_STRUCTURE;
 Contd…
 A structural representation for the DECODER2x4 entity,
architecture DEC_STR of DECODER2x4 is
component INV
port (A: in BIT; Z: out BIT);
end component;
component NAND3
port (A, B, C: in BIT; Z: out BIT);
end component;
signal ABAR, BBAR: BIT;
begin
I0: INV port map (A, ABAR);
I1: INV port map (B, BBAR);
N0: NAND3 port map (ABAR, BBAR, ENABLE, Z(0));
N1: NAND3 port map (ABAR, B, ENABLE, Z(1));
N2: NAND3 port map (A, BBAR, ENABLE, Z(2));
N3: NAND3 port map (A, B, ENABLE, Z(3));
end DEC_STR;
 Contd…
 A component instantiation statement is a concurrent statement,
as defined by the language.
 Therefore, the order of these statements is not important.
 The structural style of modeling describes only an
interconnection of components (viewed as black boxes) without
implying any behavior of the components themselves, nor of the
entity that they collectively represent.
 DATAFLOW STYLE OF MODELING
 In this modeling style, the flow of data through the entity is
expressed primarily using concurrent signal assignment
statements.
 The structure of the entity is not explicitly specified in this
modeling style, but it can be implicitly deduced.
 Consider the following alternate architecture body for the
HALF_ADDER entity that uses this style.
architecture HA_CONCURRENT of HALF_ADDER is
begin
SUM <= A xor B after 8 ns;
CARRY <= A and B after 4 ns;
end HA_CONCURRENT;
 Contd…
 In a signal assignment statement, the symbol <= implies an
assignment of a value to a signal.
 The value of the expression on the right-hand-side of the
statement is computed and is assigned to the signal on the left-
hand-side, called the target signal.
 A concurrent signal assignment statement is executed only when
any signal used in the expression on the right-hand-side has an
event on it, that is, the value for the signal changes.
 Concurrent signal assignment statements are concurrent
statements, and therefore, the ordering of these statements in an
architecture body is not important.
 BEHAVIORAL STYLE OF MODELING
 The behavioral style of modeling specifies the behavior of an
entity as a set of statements that are executed sequentially in the
specified order.
 This set of sequential statements, that are specified inside a
process statement, do not explicitly specify the structure of the
entity but merely specifies its functionality.
 A process statement is a concurrent statement that can appear
within an architecture body.
 For example
entity LS_DFF is
port (Q: out BIT; D, CLK: in BIT):
end LS_DFF;
architecture LS_DFF_BEH of LS_DFF is
begin
process (D, CLK)
begin
if (CLK = '1') then
Q <= D;
end if;
end process;
end LS_DFF_BEH;
 Contd…
 A process statement, too, has a declarative part (between the
keywords process and begin), and a statement part (between the
keywords begin and end process).
 The statements appearing within the statement part are
sequential statements and are executed sequentially.
 The list of signals specified within the parenthesis after the
keyword process constitutes a sensitivity list and the process
statement is invoked whenever there is an event on any signal in
this list.
 Signal assignment statements appearing within a process are
called sequential signal assignment statements.
 Sequential signal assignment statements, including variable
assignment statements, are executed sequentially independent of
whether an event occurs on any signals in its right-hand-side
expression or not; contrast this with the execution of concurrent
signal assignment statements in the dataflow modeling style.
 MIXED STYLE OF MODELING
 It is possible to mix the three modeling styles that we have seen
so far in a single architecture body.
 That is, within an architecture body, we could use component
instantiation statements (that represent structure), concurrent
signal assignment statements (that represent dataflow), and
process statements (that represent behavior).
 Here is an example of a mixed style model for a full-adder
entity FULL_ADDER is
port (A, B, CIN: in BIT; SUM, COUT: out BIT);
end FULL_ADDER;
architecture FA_MIXED of FULL_ADDER is
component XOR2
port (A, B: in BIT; Z: out BIT);
end component;
signal S1: BIT;
 Contd…
begin
X1: XOR2 port map (A, B, S1 ); - structure
process (A, B, CIN) - behavior.
variable T1, T2, T3: BIT;
begin
T1 :=A and B;
T2 := B and CIN;
T3:=A and CIN;
COUT <= T1 or T2 or T3;
end process;
SUM <= S1 xor CIN; - dataflow
end FA_M!XED;
 CONFIGURATION DECLARATION
 A configuration declaration is used to select one of the possibly many
architecture bodies that an entity may have, and to bind components,
used to represent structure in that architecture body, to entities
represented by an entity-architecture pair or by a configuration, that
reside in a design library.
 Consider the following configuration declaration for the HALF_ADDER
entity:
library CMOS_LIB, MY_LIB;
configuration HA_BINDING of HALF_ADDER is
for HA-STRUCTURE
for X1:XOR2
use entity CMOS_LIB.XOR_GATE(DATAFLOW);
end for;
for A1:AND2
use configuration MY_LIB.AND_CONFIG;
end for;
end for;
end HA_BINDING;
 Contd…
 When an architecture body does not contain any component
instantiations, for example, when dataflow style is used, such an
architecture body can also be selected to create a configuration.
 For example, the DEC_DATAFLOW architecture body can be
selected for the DECODER2x4 entity using the following
configuration declaration.
configuration DEC_CONFIG of DECODER2x4 is
for DEC_DATAFLOW
end for;
end DEC_CONFIG;
 PACKAGE DECLARATION
 A package declaration is used to store a set of common
declarations like components, types, procedures, and functions.
 These declarations can then be imported into other design units
using a context clause.
 Here is an example of a package declaration.
package EXAMPLE_PACK is
type SUMMER is (MAY, JUN, JUL, AUG, SEP);
component D_FLIP_FLOP
port (D, CK: in BIT; Q, QBAR: out BIT);
end component;
constant PIN2PIN_DELAY: TIME := 125 ns;
function INT2BIT_VEC (INT_VALUE: INTEGER)
return BIT_VECTOR;
end EXAMPLE_PACK;
 Contd…
 Notice that the behavior of the function INT2BIT_VEC does not
appear in the package declaration; only the function interface
appears.
 The definition or body of the function appears in a package body.
 Assume that this package has been compiled into a design
library called DESIGN_LIB.
 Consider the following context clauses associated with an entity
declaration.
library DESIGN_LIB;
use DESIGN_LIB.EXAMPLE_PACK.all;
entity RX is . . .
 It is also possible to selectively import declarations from a
package declaration into other design units. For example,
library DESIGN_LIB;
use DESIGN_LIB.EXAMPLE_PACK.D_FLIP_FLOP;
use DESIGN_LIB.EXAMPLE_PACK.PIN2PIN_DELAY;
architecture RX_STRUCTURE of RX is . . .
 Contd…
 Another approach to selectively import items declared in a
package is by using selected names. For example,
library DESIGN_LIB;
package ANOTHER_PACKAGE is
function POCKET_MONEY
(MONTH: DESIGN_LIB.EXAMPLE_PACK.SUMMER)
return INTEGER;
constant TOTAL_ALU: INTEGER; -- A deferred constant.
end ANOTHER_PACKAGE;
 PACKAGE BODY
 A package body is primarily used to store the definitions of
functions and procedures that were declared in the
corresponding package declaration, and also the complete
constant declarations for any deferred constants that appear in
the package declaration.
 A package body is always associated with a package declaration.
 A package declaration can have at most one package body
associated with it.
 Contrast this with an architecture body and an entity declaration
where multiple architecture bodies may be associated with a
single entity declaration.
 A package body may contain other declarations as well.
 The name of the package body must be the same as that of the
package declaration with which it is associated.
 It is important to note that a package body is not necessary if the
corresponding package declaration has no function and
procedure declarations and no deferred constant declarations.
 Contd…
 Here is the package body for the package EXAMPLE_PACK
declared in the previous section:
package body EXAMPLE_PACK is
function INT2BIT_VEC (INT_VALUE: INTEGER)
return BIT_VECTOR is
begin
--Behavior of function described here.
end INT2BIT_VEC;
end EXAMPLE_PACK;
 Contd…
 Here is the package body that is associated with the package
ANOTHER_PACKAGE that was declared in the previous section.
package body ANOTHER_PACKAGE is
constant TOTAL_ALU: INTEGER := 10; -- A complete constant declaration
function POCKET_MONEY -- Function body.
(MONTH: DESIGN_UB.EXAMPLE_PACK.SUMMER)
return INTEGER is
begin
case MONTH is
when MAY => return 5;
when JUL | SEP => return 6;
when others => return 2;
end case;
end POCKET_MONEY;
end ANOTHER_PACKAGE;