Chapter 18: The Pentium and Pentium Pro

Microprocessors
Introduction
• The Pentium microprocessor signals an
improvement to the architecture found in
the 80486 microprocessor.
• These changes are internal to the Pentium,
which makes software upward-compatible
from earlier Intel 80X86 microprocessors.
• A later improvement to the Pentium was
the addition of the MMX instructions.

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Chapter Objectives
Upon completion of this chapter, you will be able to:

• Contrast the Pentium and Pentium Pro with

the 80386 and 80486 microprocessors.
• Describe the organization and interface of
the 64-bit-wide Pentium memory system
and its variations.
• Contrast the changes in the memory-
management unit and paging unit
when compared to the 80386 and
80486 microprocessors.
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Chapter Objectives (cont.)
Upon completion of this chapter, you will be able to:

• Detail the new instructions found with the

Pentium microprocessor.
• Explain how the superscalar dual integer
units improve performance of the Pentium
microprocessor.
• Describe the operation of the branch
prediction logic.

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Chapter Objectives (cont.)
Upon completion of this chapter, you will be able to:

• Detail the improvements in the Pentium Pro

when compared with the Pentium.
• Explain how the dynamic execution
architecture of the Pentium Pro functions.

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18–1 INTRO TO THE PENTIUM
PROCESSOR
– the pin-out of the Pentium processor,
packaged in a huge 237-pin PGA (pin
grid array)
– Pentium is available in two versions:
• the full-blown Pentium
• P24T version called the Pentium OverDrive
– P24T version contains a 32-bit data bus,
for insertion into 80486 machines which
contain the P24T socket
Figure 18–1 The pin-out of the Pentium microprocessor.
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• Each Pentium output pin is capable of
providing 4.0 mA of current at logic 0
level and 2.0 mA at logic 1 level.
– compared to the 2.0 mA available 8086-80286
• Each input pin represents a small load
requiring only 15 µA of current.
• In some systems, except the smallest,
these current levels require bus buffers.

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The Memory System
• Memory system for the Pentium is 4G bytes.
– just as in 80386DX and 80486 processors
• Pentium uses a 64-bit data bus to address
memory in eight 512M byte banks.
• Memory is divided into eight banks with each
bank storing byte-wide data with a parity bit.
• The Pentium, like 80486, employs internal
parity generation and checking logic for the
memory system’s data bus information.

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 – Pentium systems do not use parity checks,
because ECC is available
– 64-bit-wide memory is important to double-
precision floating-point data
– Pentium is able to retrieve floating-point data
with one read cycle, instead of two as in 80486

Figure 18–2 The 8-byte-wide memory banks of the Pentium microprocessor.

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• The memory system is numbered in bytes,
from byte 00000000H to byte FFFFFFFFH.
• Memory selection is accomplished with
bank enable signals (BE7-BE0).
• The banks allow Pentium to access any
single byte, word, doubleword, or quadword
with one memory transfer cycle.
• A new feature is ability to check and generate
parity for the address bus (A31–A5).

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• The AP pin provides the system with parity
information and the APCHK indicates a bad
parity check for the address bus.
• Pentium takes no action when an address
parity error is detected.
• The error must be assessed by the system
and the system must take appropriate action.
– an interrupt, if so desired

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Input/Output System
• Input/output system of Pentium is completely
compatible with earlier Intel processors.
• I/O port number appears on lines A15–A3
• Bank enable signals select actual memory
banks used for the I/O transfer.
• I/O privilege information is added to the TSS
segment when Pentium is in protected mode.
• If blocked I/O is accessed, Pentium generates
a type 13 interrupt, I/O privilege violation.
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System Timing
• Pentium nonpipelined memory cycle consists
of two clocking periods: T1 and T2.
• Figure 18–3 shows basic nonpipelined read
• 66 MHz Pentium is capable of 33 million
memory transfers per second.
– assuming memory can operate at that speed
• W/R becomes valid if ADS is logic 0 at the
positive edge of the clock (end of T1).
– clock must qualify cycle as read or write

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Figure 18–3 The nonpipelined read cycle for the Pentium microprocessor.

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• During T1, the processor issues the ADS, W/R
address, and M/IO signals.
• In order to qualify W/R & generate appropriate
MRDC and MWTC signals, we use a flip-flop
to generate the W/R signal.
• A two-line-to-one-line multiplexer then
generates memory and I/O control signals.
• See Fig 18–4 for a circuit that generates I/O
control and memory signals for Pentium.

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Figure 18–4 A circuit that generates the memory and I/O control signals.

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• During T2, the data bus is sampled in
synchronization with the end of T2 at
the positive transition of the clock pulse.
• Setup time before the clock is given as 3.8 ns.
• Hold time after the clock is given as 2.0 ns.
– the data window around the clock is 5.8 ns
• The address appears on the 8.0 ns maximum
after the start of T1.

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• Pentium at 66 MHz allows 30.3 ns (two
clocking periods), minus the address delay
of 8.0 ns and minus data setup of 3.8 ns.
• Memory access time without any wait states
is 30.3 – 8.0 – 3.8, or 18.5 ns.
• This is enough to allow access to SRAM.
– not DRAM without inserting wait states
• SRAM is normally found in the form of an
external level 2 cache.

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• Wait states are inserted by controlling the
BRDY input to the Pentium.
• BRDY must become logic 0 by the end of T2
– or additional T2 states are inserted in the timing
• Inserting wait states lengthens timing to allow
additional time for the memory to access data.
• In the timing shown, access time has been
lengthened so 60 ns DRAM can be used.
– requires insertion of four wait states of 15.2 ns
(one clocking period) each to lengthen access
time to 79.5 ns
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 – a read cycle timing diagram that contains wait
states for slower memory.

Figure 18–5 The Pentium timing diagram with four wait states inserted for an access
time of 79.5 ns.
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• BRDY is a synchronous signal generated by
using the system clock.
• Figure 18–6 illustrates a circuit to generate
BRDY for inserting any number of wait states
into the Pentium timing diagram.
• The ADS signal is delayed between 0 and 7
clocking periods by the 74Fl61 shift register
to generate the BRDY signal.
• The exact number of wait states is selected
by the 74F151 eight-line-to-one-line
multiplexer.
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Figure 18–6 A circuit that generates wait states by delaying ADS. This circuit is wired
to generate four wait states.

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• The burst cycle is a more efficient method
of reading memory data.
– burst cycle in Pentium transfers four 64-bit
numbers per cycle in five clocking periods
• A burst without wait states requires the
memory system transfer data every 15.2 ns.
• With a level 2 cache, this speed is no problem
as long as the data are read from the cache.
• If the cache does not contain the data, wait
states must be inserted, reducing throughput.

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Figure 18–7 The Pentium burst cycle operation that transfers four 64-bit data
between the microprocessor and memory.

– wait states can be inserted to allow more time to

the memory system for accesses

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Branch Prediction Logic
• Used by Pentium to reduce time required for
a branch caused by internal delays.
• Delays are minimized when a branch is
encountered, because the processor begins
prefetch instruction at the branch address.
• If the branch prediction logic errs, the branch
requires an extra three clocking periods to
execute.
– in most cases, branch prediction is correct
and no delay ensues
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Cache Structure
• Pentium contains two 8K-byte cache
memories instead of one as in 80486.
– one 8K-byte instruction cache stores only
instructions
– another 8K-byte cache stores data used by
instructions
• In the 80486 unified cache, a data-intensive
program quickly filled the cache, and slowed
execution speed.
– this cannot occur in Pentium separate caches
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Superscalar Architecture
• Pentium has three execution units.
– One executes floating-point instructions
– the other two (U-pipe and V-pipe) execute
integer instructions
• This means it is possible to execute three
instructions simultaneously.
– because the floating-point unit is also used for
MMX instructions, Pentium can simultaneously
execute two integers and one MMX instruction.

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18–2 SPECIAL PENTIUM
REGISTERS
• Pentium is essentially the same as 80386
and 80486
– except some additional features and changes
to the control register set have occurred
• This section highlights the differences
between the 80386 control register structure
and the flag register.

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Control Registers
– a new control register, CR4, has been added
to the control register array

Figure 18–8 The structure of the Pentium control registers.

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EFLAG Register
– the extended flag (EFLAG) register has
been changed in the Pentium
– four new flag bits have been added to control
or indicate conditions about some of the new
features in the Pentium

Figure 18–9 The structure of the Pentium EFLAG register.

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Built-In Self-Test (BIST)
• Accessed on power-up by placing logic 1 on
INIT while the RESET changes from 1 to 0.
• BIST tests 70% of the internal structure
of the Pentium in approximately 150 µs.
• Upon completion, Pentium reports outcome
in register EAX.
• If EAX = 0, BIST has passed and Pentium
is ready for operation.
– if EAX contains any other value, the Pentium
has malfunctioned and is faulty
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18–3 PENTIUM MEMORY
MANAGEMENT
• The memory-management unit within the
Pentium is upward-compatible with 80386
and 80486 processors.
• Many features of these earlier processors
are basically unchanged in the Pentium.
• The main change is in the paging unit and a
new system memory-management mode.

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Paging Unit
• Paging table structure can become large in
a system with a large memory.
– to fully repage 4G memory, requires over 4M
bytes of memory for the page tables
• Paging functions with a new Pentium
extension with 4M-byte memory pages.
– the new feature reduces the structure to a single
page directory, with no page tables
• The new 4M-byte page sizes are selected
by the PSE bit in control register 0.
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• In the 4M paging scheme there is no page
table entry in the linear address.
• See Figure 18–10 for the 4M paging system
in the Pentium processor.
• The leftmost 10 bits of the linear address
select an entry in the page directory.
– just as with 4K pages
• Unlike 4K pages, there are no page tables.
– the page directory addresses a 4M-byte page

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Figure 18–10 The linear address 00200001H repaged to memory location
01000002H in 4M-byte pages. Note that there are no page tables.

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Memory-Management Mode
• System memory-management mode (SMM)
is on the same level as protected, real, and
virtual modes,
– but it is provided to function as a manager
• It is intended for high-level system functions
such as power management and security.
• Access to the SMM is accomplished via a
new external hardware interrupt applied to
the SMI pin on the Pentium.

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• When the SMM interrupt is activated, the
processor begins executing system-level
software in an area of memory called the
system management RAM, or SMMRAM
– called the SMM state dump record
• SMI disables all other normal interrupts
• Return from memory-management mode
interrupt to the interrupted program, at the
point of the interruption, is done with a new
instruction called RSM.

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• SMM mode allows the Pentium to treat the
memory system as a flat, 4G-byte system.
• SMM interrupt also stores the state of the
Pentium in a dump record.
– allows a system to enter a sleep mode and
reactivate at the point of program interruption
• SMMRAM must be powered during sleep.
– many laptop computers have a separate battery
to power SMMRAM many hours in sleep mode
• Table 18–2 lists contents of the dump record.

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• Halt auto restart and I/O trap restarts are used
when SMM mode is exited by RSM.
– allows RSM to return to the halt-state or interrupt
I/O instruction
• If neither a halt nor an I/O is in effect upon
entering SMM mode, RSM reloads the state
dump and returns to the interruption point.
• SMM mode can be used before the normal
OS is placed in memory and executed.

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18–4 NEW PENTIUM
INSTRUCTIONS
• Pentium contains one new instruction that
functions with normal system software;
– remainder of new instructions are added to
control memory-management mode and
serializing instructions
• Table 18–3 lists the new instructions added
to the Pentium instruction set.

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• CMPXCHG8B is an extension of CMPXCHG,
added to 80486 instruction set.
– compares the 64-bit number in EDX & EAX with
that of a 64-bit memory location or register pair
• CPUID reads the CPU identification code
and other information from the Pentium.
• To use CPUID, load EAX with the input value,
then execute CPUID.
– Table 18–4 shows different information
returned from CPUID for various input
values for EAX

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• If 0 is placed in EAX before executing CPUID,
the processor returns vendor identification in
EBX, EDX, and EBX.
– Intel Pentium returns “GenuineIntel” in ASCII
– “Genu” in EBX, “ineI’ in EDX, and “ntel” in ECX
• Example 18-1 shows a program to read the
vendor information with CPUID.
– then display it on the video screen in an
ActiveX label as shown in Figure 18–11
• CPUID functions in real and protected modes
and can be used in any Windows application.
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Figure 18–11 Screen shot of the program of Example 18–1 using the CPUID
instruction.

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18–5 INTRO TO THE PENTIUM PRO
• Before a processor can be used in a system,
the function of each pin must be understood.
• This section details the operation of each pin,
along with the external memory system and
I/O structures of the Pentium Pro processor.
• Figure 18–12 illustrates the pin-out of the
Pentium Pro processor, packaged in an
immense 387-pin PGA (pin grid array).

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Figure 18–12 The pin-out of the Pentium Pro microprocessor.

– Pentium Pro is available in two versions

– one version with 256K level 2 cache
– the other contains a 512K level 2 cache
– the most notable difference in the pin-
out of Pentium Pro is the provision for
a 36-bit address bus
– allows access to 64G bytes of memory

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• Pro requires a +3.3 V or +2.7 V power supply.
– current maximum is 9.9 A at 150 MHz
– maximum power dissipation of 26.7 W
• A heat sink with good airflow is required.
• Multiple Vcc and Vss connections must all be
connected for proper operation.
• There are some pins labeled N/C (no
connection) that must not be connected.
• Each output pin is capable of providing an
ample 48.0 mA of current at a logic 0 level.
• Each input pin is a 15 µA current load.
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Internal Structure of Pentium Pro
• Pentium Pro is structured differently than
earlier processors.
– which contained an execution unit, and cached
bus interface unit buffering the execution unit
• Figure 18–13 shows a block diagram of
the internal structure of the Pentium Pro
processor.

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Figure 18–13 The internal structure of the Pentium Pro microprocessor.

– system buses, which

communicate to memory
and I/O, connect to an
internal level 2 cache
– often on the main board
in most other systems
– level 2 cache in the Pro is
either 256K or 512K bytes
– integration of the level 2
cache speeds processing
and reduces number of
components in a system
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• The bus interface unit (BIU) controls access
to system buses through the level 2 cache.
– generates memory address and control signals,
and passes/fetches data or instructions to an 8K
level 1 data cache or a level 1 instruction cache
• The instruction cache is connected to the
instruction fetch and decode unit (IFDU).
– separate instruction decoders decode three
instructions simultaneously
– outputs are passed to the instruction pool,
where they remain until the dispatch and
execution unit or retire unit obtains them
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• The dispatch and execute unit (DEU)
retrieves instructions from the instruction pool
when complete, and executes them.
• DEU has three instruction execution units:
– two for processing integer instructions
– one for floating-point instructions
• Reservation station (RS) schedules up to five
events and can process four simultaneously.
• Retire unit (RU) removes instructions that
have been executed from the instruction pool.
– three decoded instructions per clock pulse
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Figure 18–14 The Pentium Pro dispatch and execution unit (DEU).

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The Memory System
• The memory system for Pentium Pro is 4G
bytes in size, just as in 80386DX–Pentium
processors
• 2M paging is new to the Pentium Pro to
allow memory above 4G to be accessed.
– access between 4G and 64G is made possible
by additional address signals A32–A35

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 – Pro uses a 64-bit data bus to address memory in
eight banks that each contain 8G bytes of data.
– additional memory is enabled with bit position 5
of CR4 , accessible when 2M paging is enabled

Figure 18–15 The eight memory banks in the Pentium Pro system. Note that each
bank is 8 bits wide and 8G long if 36-bit addressing is enabled.
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• Pentium Pro, like 80486 and Pentium, uses
internal parity generation and checking logic
for the memory system data bus information.
– 64-bit-wide memory is important to double-
precision floating-point data
• In the Pentium Pro processor, bank enable
signals are presented on the address bus
(A15–A8) during the second clock cycle of a
memory or I/O access.
– must be extracted from the address bus to
access memory banks

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• Separate banks allow Pro to access any
single byte, word, doubleword, or quadword
with one memory transfer cycle.
• Often eight separate write strobes for writing
to the memory system.
• Memory write information is provided on the
request lines from the processor during the
second clock phase of a memory or I/O
access.
• Pro is also able to check and generate parity
for the address bus during certain operations.
The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,
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• New to Pro is a built-in error-correction circuit
(ECC) allowing correction of a one-bit error
and the detection of a two-bit error.
– to detect/correct, memory must have room for an
extra 8-bit number stored with each 64-bit number
• The extra 8 bits store an error-correction code
that allows Pro to correct any single-bit error.
• A 1M  64 is a 64M SDRAM without ECC,
and a 1M  72 is an SDRAM with EEC.
• ECC code is far more reliable than the old
parity scheme, now rarely used.
The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,
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Input/Output System
• The input/output system of Pentium Pr
is completely compatible with earlier Intel
processors.
• I/O port number appears on address lines
A15–A3 with the bank enable signals used
to select the actual memory banks used
for the I/O transfer.

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

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System Timing
• The basic Pentium Pro memory cycle consists
of two sections.
– the address phase and the data phase
• During address phase, Pro sends the address
(T1) & control signals (T2) to memory and I/O.
• The control signals include the ATTR lines
(A31–A24), DID lines (A23–A16), bank enable
signals (A15–A8), and the EXF lines (A7–A3).
• See Figure 18–16 for the basic timing cycle.

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

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Figure 18–16 The basic Pentium Pro timing.

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• Cycle type appears on the request pins.
• During the data phase, four 64-bit-wide
numbers are fetched/written to the memory.
• The 66 MHz Pentium Pro is capable of 33
million memory transfers per second.
– assuming memory can operate at that speed
• Setup time before the clock is given as 5.0 ns;
hold time after the clock is given as 1.5 ns.
– the data window around the clock is 6.5 ns
– the address appears on the 8.0 ns maximum
after the start of T1
The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,
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• The Pentium Pro at 66 MHz allows 30 ns (two
clocking periods), minus the address delay
time of 8.0 ns and also minus the data setup
time of 5.0 ns.
• Memory access time without any wait states
is 30 – 8.0 – 5.0, or 17.0 ns.
• This is enough time to allow access to an
SRAM, but not to any DRAM.
– without inserting wait states into the timing

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

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18–6 SPECIAL PENTIUM PRO
FEATURES
• The Pentium Pro is essentially the same
processor as 80386, 80486, and Pentium,
except that some additional features and
changes to the control register set have
occurred.
• This section highlights the differences
between 80386 control register structure
and the Pentium Pro control register.

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Control Register 4
– CR4 has two new control bits added to the
control register array

– following is a description of the Pentium CR4

bits and the new Pentium Pro control bits in
control register CRM4

Figure 18–17 The new control register 4 (CR4) in the Pentium Pro microprocessor.
The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,
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Control Register 4 - Control Bits
• VME - Virtual mode extension enables
support for the virtual interrupt flag in
protected mode.
– if VME = 0, virtual interrupt support is disabled
• PVI - Protected mode virtual interrupt
enables support for the virtual interrupt flag
in protected mode.
• TSD - Time stamp disable controls the
RDTSC instruction.

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Control Register 4 - Control Bits
• DE - Debugging extension enables I/O
breakpoint debugging extensions when set.
• PSE - Page size extension enables 4M-byte
memory pages when set in the Pentium, or
2M-byte pages when set in the Pentium Pro
whenever PSE is also set.
• PAE - Page address extension enables
address lines A35–A32 when a special new
addressing mode, controlled by PGE, is
enabled for the Pentium Pro.
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Control Register 4 - Control Bits
• MCE - Machine check enable enables the
machine checking interrupt.
• PGE - Page extension controls the new,
larger 64G addressing mode when it is set
along with PAE and PSE.

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SUMMARY
• The Pentium microprocessor is almost
identical to the earlier 80386 and 80486
microprocessors.
• The main difference is that the Pentium has
been modified in-ternally to contain a dual
cache (instruction and data) and a dual
integer unit.
• The Pentium also operates at a higher
clock speed of 66 MHz.

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SUMMARY (cont.)
• The 66 MHz Pentium requires 3.3 A of
current, and the 60 MHz version requires
2.91 A.
• The power supply must be a +5.0 V supply
with a regulation of ±5%.
• Newer versions of the Pentium require a
3.3 V or 2.7 V power supply.
• The data bus on the Pentium is 64 bits wide
and contains eight byte-wide memory
banks selected with bank enable signals.
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SUMMARY (cont.)
• Memory access time, without wait states,
is only about 18 ns in the 66 MHz Pentium.
• The superscalar structure of the Pentium
contains three independent process-ing
units: a floating-point processor and two
integer processing units labeled U and V
by Intel.
• The cache structure of the Pentium is
modified to include two caches.

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SUMMARY (cont.)
• One 8K x 8 cache is designed as an
instruction cache;
• The other 8K x 8 cache is a data cache.
• The data cache can be operated as either
a write-through or a write-back cache.
• A new mode of operation called the system
memory-management (SMM) mode has
been added to the Pentium.

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SUMMARY (cont.)
• The SMM mode is accessed via the system
memory-management interrupt applied to
the SMI input pin.
• In response to SMI the Pentium begins
executing software at memory location
38000H.
• New instructions include the CMPXCHG8B,
RSM, RDMSR, WRMSR, and CPUID.

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SUMMARY (cont.)
• The built-in self-test (BIST) allows the
Pentium to be tested when power is first
applied to the system.
• A normal power-up reset activates the
RESET input to the Pentium.
• A BIST power-up reset activates INIT and
then deactivates the RESET pin.
• EAX is equal to a 00000000H in the BIST
passes.

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SUMMARY (cont.)
• A new proprietary Intel modification to the
paging unit allows 4M-byte memory pages
instead of the 4K-byte pages.
• This is accomplished by using the page
directory to address 1024 page tables that
each contains 4M of memory.
• The Pentium Pro is an enhanced version of
the Pentium microprocessor that contains
level 1 and level 2 caches of 256K or 512K
found on most main boards.
The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,
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SUMMARY (cont.)
• The Pentium Pro operates by using the
same 66 MHz bus speed as the Pen-tium
and the 80486.
• It uses an internal clock generator to
multiply the bus speed by various factors to
obtain higher internal execution speeds.
• The only significant software difference
between the Pentium Pro and earlier
microprocessors is the addition of the
FCMOV and CMOV instructions.
The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,
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SUMMARY
• The only hardware difference between the
Pentium Pro and earlier microprocessors is
the addition of 2M paging and four extra
address lines that allow ac-cess to a
memory address space of 64G bytes.
• Error correction code has been added to
the Pentium Pro, which corrects any single-
bit error and detects any two-bit error.

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