EE-227

Digital Logic
Design
Fall-2018

Chapter 7
Latches, Flip-Flops,
and Timers

EE-227 Digital Logic Design

Course Instructor: Engr. Khalid Iqbal Soomro
 Latches
The latch is a type of temporary storage device that has
two stable states (bistable) and is normally placed in a
category separate from that of flip-flops.

Latches are similar to flip-flops because they are bistable

devices that can reside in either of two states using a
feedback arrangement, in which the outputs are connected
back to the opposite inputs.

The main difference between latches and flip-flops is in

the method used for changing their state.

EE-227 Digital Logic Design 5/1/2019 2

 InfoNote
Latches are sometimes used for multiplexing data onto
a bus.

For example, data being input to a computer from an

external source have to share the data bus with data
from other sources.

When the data bus becomes unavailable to the external

source, the existing data must be temporarily stored,
and latches placed between the external source and the
data bus may be used to do this.

EE-227 Digital Logic Design 5/1/2019 3

 The S-R (SET-RESET) Latch
A latch is a type of bistable logic device or multivibrator. An active-
HIGH input S-R (SET-RESET) latch is formed with two cross-coupled
NOR gates, as shown in Figure 7–1(a); an active-LOW input S . R
latch is formed with two cross-coupled NAND gates, as shown in
Figure 7–1(b). Notice that the output of each gate is connected to an
input of the opposite gate. This produces the regenerative feedback
that is characteristic of all latches and flip-flops.
S

FIGURE 7–1 Two versions of SET-RESET (S-R) latches.

EE-227 Digital Logic Design 5/1/2019 4

 Latches
The active-HIGH S-R latch is in a stable (latched) condition
when both inputs are LOW.
0 R 1
0
Assume the latch is initially RESET Q
(Q = 0) and the inputs are at their Latch
inactive level (0). To SET the latch initially
(Q = 1), a momentary HIGH signal RESET
10
is applied to the S input while the R Q
0 S
remains LOW.
0 R 1
0
To RESET the latch (Q = 0), a Q
momentary HIGH signal is Latch
applied to the R input while the S initially
remains LOW. SET
1
0
Q
0 S

EE-227 Digital Logic Design 5/1/2019 5

 Latches
The active-LOW S-R latch is in a stable (latched) condition
when both inputs are HIGH.
Assume the latch is initially RESET 1 S 1
0
Q
(Q = 0) and the inputs are at their
Latch
inactive level (1). To SET the latch initially
(Q = 1), a momentary LOW signal RESET
is applied to the S input while the R 1
0
1 R Q
remains HIGH.
To RESET the latch a momentary 1 S 1
0
Q
LOW is applied to the R input
Latch
while S is HIGH. initially
Never apply an active set and 1 SET
0
Q
reset at the same time (invalid). 1R

EE-227 Digital Logic Design 5/1/2019 6

 Logic symbols for
both the active-HIGH
input and the active-
LOW input latches are
shown in Figure 7–4.

Figure 7–4
EE-227 Digital Logic Design 5/1/2019 7
EE-227 Digital Logic Design 5/1/2019 8
 Latches
The active-LOW S-R latch is available as the 74LS279A IC.
It features four internal latches with (2)
1S1
two having two S inputs. To SET any (3) (4) 1Q
1S2
of the latches, the S line is pulsed low. (1)
1R
It is available in several packages. (6)
2S (7)
S-R latches are frequently used for 2Q
(5)
2R
switch debounce circuits as shown:
VCC (11)
3S1
(12) (9) 3Q
3S2
(10)
3R
(15)
2 S Q 4S (13)
S 4Q
(14)
4R
R R Position Position
1 1 to 2 2 to 1
74LS279A

EE-227 Digital Logic Design 5/1/2019 9

 Latches
A gated latch is a variation on the basic latch.
The gated latch has an additional S
Q
input, called enable (EN) that must
be HIGH in order for the latch to
EN
respond to the S and R inputs.
Show the Q output with Q
relation to the input signals. R
Assume Q starts LOW.
Keep in mind that S and R are only active when EN is HIGH.
S
R

EN
Q
EE-227 Digital Logic Design 5/1/2019 10
EE-227 Digital Logic Design 5/1/2019 11
 Latches
The D latch is a variation of the S-R latch but combines the
S and R inputs into a single D input as shown:
D D Q
Q

EN EN

Q
Q

A simple rule for the D latch is:

Q follows D when the Enable is active.

EE-227 Digital Logic Design 5/1/2019 12

 Latches
The truth table for the D latch summarizes its operation. If
EN is LOW, then there is no change in the output and it is
latched.
Inputs Outputs
D EN Q Q Comments
0 1 0 1 RESET
1 1 1 0 SET
X 0 Q0 Q0 No change

EE-227 Digital Logic Design 5/1/2019 13

 Latches D Q

EN
Determine the Q output for the
Q
D latch, given the inputs shown.

EN

Notice that the Enable is not active during these times, so

the output is latched.

EE-227 Digital Logic Design 5/1/2019 14[E-1]

 InfoNote
Semiconductor memories consist of large numbers of individual cells.
Each storage cell holds a 1 or a 0.

One type of memory is the Static Random Access Memory or SRAM,

which uses flip-flops for the storage cells because a flip-flop will retain
either of its two states indefinitely as long as dc power is applied, thus
the term static.

This type of memory is classified as a volatile memory because all the

stored data are lost when power is turned off.

Another type of memory, the Dynamic Random Access Memory or

DRAM, uses capacitance rather than flip-flops as the basic storage
element and must be periodically refreshed in order to maintain the
stored data.

EE-227 Digital Logic Design 5/1/2019 15

 Flip-flops

Flip-flops are synchronous bistable devices, also known as

bistable multivibrators.

In this case, the term synchronous means that the output

changes state only at a specified point (leading or trailing
edge) on the triggering input called the clock (CLK), which
is designated as a control input, C; that is, changes in the
output occur in synchronization with the clock.

Flip-flops are edge-triggered or edge-sensitive whereas

gated latches are level-sensitive.

EE-227 Digital Logic Design 5/1/2019 16

 Flip-flops
An edge-triggered flip-flop changes state either at the positive
edge (rising edge) or at the negative edge (falling edge) of the
clock pulse and is sensitive to its inputs only at this transition of
the clock.

Two types of edge-triggered flip-flops are covered in this section:

D and J-K. The logic symbols for these flip-flops are shown in
Figure 7–13.

Notice that each type can be either positive edge-triggered (no

bubble at C input) or negative edge-triggered (bubble at C input).

The key to identifying an edge-triggered flip-flop by its logic

symbol is the small triangle inside the block at the clock (C)
input. This triangle is called the dynamic input indicator.
EE-227 Digital Logic Design 5/1/2019 17
 FIGURE 7-13 Edge-triggered flip-flop logic symbols (top: positive edge-triggered;
bottom: negative edge-triggered).

EE-227 Digital Logic Design 5/1/2019 18

 Flip-flops
A flip-flop differs from a latch in the manner it changes
states. A flip-flop is a clocked device, in which only the
clock edge determines when a new bit is entered.
The active edge can be positive or negative.

D Q D Q

C C

Dynamic Q Q
input
indicator (a) Positive edge-triggered (b) Negative edge-triggered

EE-227 Digital Logic Design 5/1/2019 19

 Flip-flops

The truth table for a positive-edge triggered D flip-flop

shows an up arrow to remind you that it is sensitive to its
D input only on the rising edge of the clock; otherwise it is
latched. The truth table for a negative-edge triggered D
flip-flop is identical except for the direction of the arrow.

Inputs Outputs Inputs Outputs

D CLK Q Q Comments D CLK Q Q Comments
1 1 0 SET 1 1 0 SET
0 0 1 RESET 0 0 1 RESET

(a) Positive-edge triggered (b) Negative-edge triggered

EE-227 Digital Logic Design 5/1/2019 20

EE-227 Digital Logic Design 5/1/2019 21
 J-K Flip-flop
The J and K inputs of the J-K flip-flop are synchronous inputs
because data on these inputs are transferred to the flip-flop’s
output only on the triggering edge of the clock pulse.

When J is HIGH and K is LOW, the Q output goes HIGH on the

triggering edge of the clock pulse, and the flip-flop is SET.

When J is LOW and K is HIGH, the Q output goes LOW on the

triggering edge of the clock pulse, and the flip-flop is RESET.

When both J and K are LOW, the output does not change from
its prior state. When J and K are both HIGH, the flip-flop
changes state. This is called the toggle mode.

EE-227 Digital Logic Design 5/1/2019 22

 FIGURE 7-17 Operation of a positive edge-triggered J-K flip-flop.

EE-227 Digital Logic Design 5/1/2019 23

 Flip-flops
The J-K flip-flop is more versatile than the D flip flop. In
addition to the clock input, it has two inputs, labeled J and
K. When both J and K = 1, the output changes states
(toggles) on the active clock edge (in this case, the rising
edge).
Inputs Outputs
J K CLK Q Q Comments
0 0 Q0 Q0 No change
0 1 0 1 RESET
1 0 1 0 SET
1 1 Q0 Q0 Toggle

The two control inputs are labeled J and K in honor of Jack Kilby, who
invented the integrated circuit.
EE-227 Digital Logic Design 5/1/2019 24
 Flip-flops
J Q

CLK
Determine the Q output for the J-K
flip-flop, given the inputs shown. K Q

Notice that the outputs change on the leading edge of the clock.

Set Toggle Set Latch

CLK

EE-227 Digital Logic Design 5/1/2019 25

 Flip-flops

A D-flip-flop does not have a toggle mode like the J-K flip-
flop, but you can hardwire a toggle mode by connecting Q
back to D as shown. This is useful in some counters as you
will see in Chapter 8.
D Q

For example, if Q is LOW, Q is CLK CLK

HIGH and the flip-flop will toggle
on the next clock edge. Because the Q
flip-flop only changes on the active
edge, the output will only change
once for each clock pulse.
D flip-flop hardwired for
a toggle mode

EE-227 Digital Logic Design 5/1/2019 26[E-2]

 Asynchronous Preset & Clear Inputs

For the flip-flops discussed, the D and J-K inputs are

called synchronous inputs because data on these inputs
are transferred to the flip-flop’s output only on the
triggering edge of the clock pulse; that is, the data are
transferred synchronously with the clock.

Most integrated circuit flip-flops also have asynchronous

inputs. These are inputs that affect the state of the flip-flop
independent of the clock. They are normally labeled preset
(PRE) and clear (CLR), or direct set (SD) and direct reset
(RD) by some manufacturers.

EE-227 Digital Logic Design 5/1/2019 27

 Asynchronous Preset & Clear Inputs
An active level on the preset input will set the flip-flop, and an
active level on the clear input will reset it. A logic symbol for a D
flip-flop with preset and clear inputs is shown in Figure 7–25.

These inputs are active-LOW, as indicated by the bubbles. These

preset and clear inputs must both be kept HIGH for synchronous
operation. In normal operation, preset and clear would not be
LOW at the same time.

FIGURE 7-25 Logic symbol for a D flip-flop

with active-LOW preset and clear inputs.

EE-227 Digital Logic Design 5/1/2019 28

 Asynchronous Preset & Clear Inputs
Figure 7–26 shows the logic diagram for an edge-triggered D flip-flop
with active-LOW preset (PRE) and clear (CLR) inputs.

This figure illustrates basically how these inputs work. As you can see,
they are connected so that they override the effect of the synchronous
input, D and the clock.

FIGURE 7-26
Logic diagram for a
basic D flip-flop
with active-LOW
preset and clear
inputs.

EE-227 Digital Logic Design 5/1/2019 29

EE-227 Digital Logic Design 5/1/2019 30
 Solution
1. During clock pulses 1, 2, and 3, the preset (PRE) is LOW,
keeping the flip-flop SET regardless of the synchronous D
input.

2. For clock pulses 4, 5, 6, and 7, the output follows the

input on the clock pulse because both PRE and CLR are
HIGH.

3. For clock pulses 8 and 9, the clear (CLR) input is LOW,

keeping the flip-flop RESET regardless of the synchronous
inputs.

The resulting Q output is shown in Figure 7–27(b).

EE-227 Digital Logic Design 5/1/2019 31

 J-K Flip-flops

Synchronous inputs are transferred in the triggering edge

of the clock (for example the D or J-K inputs). Most flip-
flops have other inputs that are asynchronous, meaning
they affect the output independent of the clock.
PRE
Two such inputs are normally labeled
preset (PRE) and clear (CLR). These Q
J
inputs are usually active LOW. A J-K
flip flop with active LOW preset and CLK
CLR is shown.
K Q

CLR

EE-227 Digital Logic Design 5/1/2019 32

 PRE

Flip-flops J Q

CLK

Determine the Q output for the J-K Q

K
flip-flop, given the inputs shown.
CLR
Set Toggle Set Reset Toggle Latch
CLK

K Set
PRE Reset
CLR

EE-227 Digital Logic Design 5/1/2019 33

 Flip-flop Characteristics

The performance, operating requirements, and limitations of

flip-flops are specified by several operating characteristics
or parameters found on the data sheet for the device.

Generally, the specifications are applicable to all CMOS

and bipolar (TTL) flip-flops.

EE-227 Digital Logic Design 5/1/2019 34

 Propagation delay

A propagation delay time is the interval of time required

after an input signal has been applied for the resulting
output change to occur. Four categories of propagation
delay times are important in the operation of a flip-flop:

1. Propagation delay tPLH as measured from the triggering

edge of the clock pulse to the LOW-to-HIGH transition of
the output. This delay is illustrated in Figure 7–31(a).

2. Propagation delay tPHL as measured from the triggering

edge of the clock pulse to the HIGH-to-LOW transition of
the output. This delay is illustrated in Figure 7–31(b).

EE-227 Digital Logic Design 5/1/2019 35

 Propagation delay

CLK 50% point

FIGURE 7-31 Propagation delays, clock to output.

The typical propagation delay time for the 74AHC family (CMOS) is 4 ns.
Even faster logic is available for specialized applications.
EE-227 Digital Logic Design 5/1/2019 36
 3. Propagation delay tPLH as measured from the leading edge of
the preset input to the LOW-to-HIGH transition of the output.
This delay is illustrated in Figure 7–32(a) for an active-LOW
preset input.
4. Propagation delay tPHL as measured from the leading edge of
the clear input to the HIGH-to-LOW transition of the output.
This delay is illustrated in Figure 7–32(b) for an active-LOW
clear input. The 74AHC family has specified delay times under 5 ns.

FIGURE 7-32 Propagation delays, preset input to output and clear input to output.
EE-227 Digital Logic Design 5/1/2019 37
 Set-up time
The set-up time (ts) is the minimum interval required for
the logic levels to be maintained constantly on the inputs
(J and K, or D) prior to the triggering edge of the clock
pulse in order for the levels to be reliably clocked into the
flip-flop. This interval is illustrated in Figure 7–33 for a D
flip-flop.

FIGURE 7-33 Set-up time (ts).

EE-227 Digital Logic Design 5/1/2019 38

 Hold Time
The hold time (th) is the minimum interval required for the
logic levels to remain on the inputs after the triggering edge
of the clock pulse in order for the levels to be reliably
clocked into the flip-flop. This is illustrated in Figure 7–34
for a D flip-flop.

FIGURE 7-34 Hold time (th).

EE-227 Digital Logic Design 5/1/2019 39[E-3]

 Max Clock Frequency & Pulse Widths

Maximum Clock Frequency

The maximum clock frequency (fmax) is the highest rate at
which a flip-flop can be reliably triggered. At clock
frequencies above the maximum, the flip-flop would be
unable to respond quickly enough, and its operation would
be impaired.

Pulse Widths
Minimum pulse widths (tW) for reliable operation are
usually specified by the manufacturer for the clock, preset,
and clear inputs. Typically, the clock is specified by its
minimum HIGH time and its minimum LOW time.

EE-227 Digital Logic Design 5/1/2019 40

 Power Dissipation
The power dissipation of any digital circuit is the total power
consumption of the device. For example, if the flip-flop operates on a
+5 V dc source and draws 5 mA of current, the power dissipation is:
P = VCC x ICC = 5 V x 5 mA = 25 mW

A useful comparison between logic families is the speed-power product

which uses two of the specifications discussed: the average propagation
delay and the average power dissipation. The unit is energy.

What is the speed-power product for 74AHC74A? Use

the data from Table 7-5 to determine the answer.
From Table 7-5, the average propagation delay is 4.6 ns.
The quiescent power dissipated is 1.1 mW. Therefore, the
speed-power product is 5 pJ [Where pJ is Pico Joules]
EE-227 Digital Logic Design 5/1/2019 41
 Flip-Flop Applications
Parallel Data Storage
A common requirement in digital systems is to store several bits of
data from parallel lines simultaneously in a group of flip-flops.
This operation is illustrated in Figure 7–35(a) using four flip-flops.
Each of the four parallel data lines is connected to the D input of a
flip-flop. The clock inputs of the flip-flops are connected together,
so that each flip-flop is triggered by the same clock pulse.

In this example, positive edge-triggered flip-flops are used, so the

data on the D inputs are stored simultaneously by the flip-flops on
the positive edge of the clock, as indicated in the timing diagram in
Figure 7–35(b). Also, the asynchronous reset (R) inputs are
connected to a common CLR line, which initially resets all the flip-
flops.
EE-227 Digital Logic Design 5/1/2019 42
 FIGURE 7-35
Example of flip-flops
used in a basic register
for parallel data storage.

EE-227 Digital Logic Design 5/1/2019 43

 Flip-Flop Applications
Frequency Division
Another application of a flip-flop is dividing (reducing) the
frequency of a periodic waveform. When a pulse waveform
is applied to the clock input of a D or J-K flip-flop that is
connected to toggle (D = Q or J = K = 1), the Q output is a
square wave with one-half the frequency of the clock input.

Thus, a single flip-flop can be applied as a divide-by-2

device, as is illustrated in Figure 7–36 for both a D and a J-K
flip-flop. As you can see in part (c), the flip-flop changes
state on each triggering clock edge (positive edge-triggered
in this case). This results in an output that changes at half
the frequency of the clock waveform.

EE-227 Digital Logic Design 5/1/2019 44

 Flip-flop Applications

For frequency division, it is simple to use a flip-flop in

the toggle mode or to chain a series of toggle flip flops to
continue to divide by two. HIGH HIGH

One flip-flop will divide fin

J QA J QB fout
by 2, two flip-flops will
divide fin by 4 (and so on). fin CLK CLK
A side benefit of frequency
division is that the output K K
has an exact 50% duty
fin
cycle.
Waveforms:
fout

EE-227 Digital Logic Design 5/1/2019 45

EE-227 Digital Logic Design 5/1/2019 46
 One-Shots
The one-shot or monostable multivibrator is a device
with only one stable state. When triggered, it goes to
its unstable state for a predetermined length of time,
then returns to its stable state. +V

REXT CEXT
For most one-shots, the length of time Q
CX
in the unstable state (tW) is determined RX/CX
by an external RC circuit. Trigger

Q
Trigger

Q
tW

EE-227 Digital Logic Design 5/1/2019 47

 One-Shots
Nonretriggerable one-shots do not respond to any
triggers that occur during the unstable state.
Retriggerable one-shots respond to any trigger, even if
it occurs in the unstable state. If it occurs during the
unstable state, the state is extended by an amount
equal to the pulse width.
Retriggerable one-shot:
Trigger
Retriggers
Q
tW

EE-227 Digital Logic Design 5/1/2019 48

 One-Shots

An application for a retriggerable one-shot is a power

failure detection circuit. Triggers are derived from the
ac power source, and continue to retrigger the one
shot. In the event of a power failure, the one-shot is
not triggered and an alarm can be initiated.
Triggers Missing trigger
derived due to power
from ac failure

Q Retriggers Retriggers Power failure indication

tW
tW
tW

EE-227 Digital Logic Design 5/1/2019 49

 InfoNote

Most systems require a timing source to provide accurate

clock waveforms. The timing section controls all system
timing and is responsible for the proper operation of the
system hardware.

The timing section usually consists of a crystal-controlled

oscillator and counters for frequency division. Using a high-
frequency oscillator divided down to a lower frequency
provides for greater accuracy and frequency stability.

EE-227 Digital Logic Design 5/1/2019 50

 The 555 timer

The 555 timer is a versatile and widely used IC device

because it can be configured in two different modes as
either a monostable multivibrator (one-shot) or as an
astable multivibrator (pulse oscillator).

The IC was designed by Hans R. Camenzind in 1970

and brought to market in 1971 by Signetics and It was
called “The IC Time Machine”.

The 555 Timer IC is called a 555 because of the 3 - 5K

internal resistor divider network which are used to set
comparator levels.

EE-227 Digital Logic Design 5/1/2019 51

 The 555 timer

The 555 timer can be configured in various ways,

including as a one-shot. A basic one shot is shown. The
pulse width is determined by R1C1 and is approximately
+V
tW = 1.1R1C1. CC

(4) (8)
R1
(7) RESET VCC
DISCH
(6) (3)
The trigger is a THRES OUT
negative-going (2) (5) tW = 1.1R1C1
TRIG CONT
pulse. GND
C1 (1)

EE-227 Digital Logic Design 5/1/2019 52

 The 555 timer
Determine the pulse width for the circuit shown.

tW = 1.1R1C1 = 1.1(10 kW)(2.2 mF) = 24.2 ms

+VCC
+15 V

(4) (8)
R1
10 kW (7) RESET VCC
DISCH
(6) (3)
THRES OUT
(2) (5) tW = 1.1R1C1
TRIG CONT
C1 GND
(1)
2.2 mF

EE-227 Digital Logic Design 5/1/2019 53

 The 555 timer

The 555 can be configured as a basic astable multivibrator

with the circuit shown. In this circuit C1 charges through
R1 and R2 and discharges through only R2. The output
+V
frequency is given by: CC

1.44
f 
 R1  2R2  C1
(4) (8)
R1
RESET VCC
(7)
DISCH
The frequency and duty cycle R2 (6)
THRES OUT
(3)

are set by these components. (2) (5)

TRIG CONT
C1 GND
(1)

EE-227 Digital Logic Design 5/1/2019 54

 The 555 timer
Given the components, you can read the frequency from
the chart. Alternatively, you can use the chart to pick
components for a desired frequency.
+VCC
100

10 (4) (8)
R1
RESET VCC
1.0 (7)
DISCH
C1 (mF)

10

1
1M

10

10

kW
0k
MW

kW
W

(6) (3)
W

0.1 R2 THRES OUT

(2) (5)
TRIG CONT
0.01
C1 GND
(1)
0.001
0.1 1.0 10 100 1.0k 10k 100k

f (Hz)
EE-227 Digital Logic Design 5/1/2019 55
 The 555 timer Applications

The 555 timer IC is used in a

variety of timer, pulse generation,
and oscillator applications.

The 555 can be used to provide

time delays, as an oscillator, and as
a flip-flop element.

Derivatives provide two or four

timing circuits in one package.

EE-227 Digital Logic Design 5/1/2019 56

 Selected Key Terms

Latch A bistable digital circuit used for storing a bit.

Bistable Having two stable states. Latches and flip-flops are
bistable multivibrators.
Clock A triggering input of a flip-flop.

D flip-flop A type of bistable multivibrator in which the output

assumes the state of the D input on the triggering
edge of a clock pulse.

J-K flip-flop A type of flip-flop that can operate in the SET,

RESET, no-change, and toggle modes.
 Selected Key Terms

Propagation The interval of time required after an input signal

delay time has been applied for the resulting output signal to
change.
Set-up time The time interval required for the input levels to be
on a digital circuit.
Hold time The time interval required for the input levels to
remain steady to a flip-flop after the triggering
edge in order to reliably activate the device.
Timer A circuit that can be used as a one-shot or as an
oscillator.
1. The output of a D latch will not change if
a. the output is LOW
b. Enable is not active
c. D is LOW
d. all of the above
2. The D flip-flop shown will
D Q
a. set on the next clock pulse
CLK CLK
b. reset on the next clock pulse
c. latch on the next clock pulse Q

d. toggle on the next clock pulse

3. For the J-K flip-flop shown, the number of inputs that
are asynchronous is
PRE
a. 1
b. 2 J Q

c. 3 CLK

d. 4 K Q

CLR
4. Assume the output is initially HIGH on a leading edge
triggered J-K flip flop. For the inputs shown, the output
will go from HIGH to LOW on which clock pulse?
a. 1
CLK
b. 2 J

c. 3 K

d. 4 1 2 3 4
5. The time interval illustrated is called
a. tPHL 50% point on triggering edge

b. tPLH CLK

c. set-up time
Q 50% point on LOW-to-
d. hold time HIGH transition of Q
?
6. The time interval illustrated is called
a. tPHL
b. tPLH D

c. set-up time CLK

d. hold time ?
7. The application illustrated is a
a. astable multivibrator HIGH HIGH

b. data storage device fout

J QA J QB
c. frequency multiplier
fin CLK CLK
d. frequency divider
K K
 Output
lines
D Q0
8. The application illustrated is a C

a. astable multivibrator R

D Q1
b. data storage device C

c. frequency multiplier D Q2

d. frequency divider Parallel data

C

input lines R

D Q3
Clock C

R
Clear
9. A retriggerable one-shot with an active HIGH output has
a pulse width of 20 ms and is triggered from a 60 Hz line.
The output will be a
a. series of 16.7 ms pulses
b. series of 20 ms pulses
c. constant LOW
d. constant HIGH
10. The circuit illustrated is a +VCC

a. astable multivibrator
(4) (8)
R1
b. monostable multivibrator (7)
RESET VCC
DISCH
c. frequency multiplier R2 (6)
THRES OUT
(3)

(2) (5)
d. frequency divider C1
TRIG CONT
GND
(1)
Answers:
1. b 6. d
2. d 7. d
3. b 8. b
4. c 9. d
5. b 10. a