Microprocessor 8085 Architecture

Basic Processor Architecture
1
Building Blocks of Processor Systems
MEM ORY
INPUT-OUTPUT
CONTROL
DATAPATH
CPU
2
Processor System Architecture
The typical processor system consists of:
 CPU (central processing unit)
 ALU (arithmetic-logic unit)
 Control Logic
 Registers, etc…
 Memory
 Input / Output interfaces
Interconnections between these units:
 Address Bus
 Data Bus
 Control Bus
3
Bus and CPU
Bus: A shared group of wires used for communicating
signals among devices
• address bus: the device and the location within the
device that is being accessed
• data bus: the data value being communicated
• control bus: describes the action on the address and data
buses
CPU: Core of the processor, where instructions are executed
• High-level language: a = b + c
• Assembly language: add r1 r2 r3
• Machine language: 0001001010111010101
4
Memory and I/O
Memory: Where instructions (programs) and data are stored
• Organized in arrays of locations (addresses), each storing
one byte (8 bits) in general
• A read operation to a particular location always returns the
last value stored in that location
I/O devices: Enable system to interact with the world

• Device interface (a.k.a. controller or adapter) hardware
connects actual device to bus
• The CPU views the I/O device registers just like
memory that can be accessed over the bus. However,
I/O registers are connected to external wires, device
control logic, etc.
• Reads may not return last value written
• Writes may have side effects
5
8085 Microprocessor Architecture
6
The 8085 Bus Structure
The 8-bit 8085 CPU (or MPU – Micro Processing Unit)
communicates with the other units using a 16-bit address
bus, an 8-bit data bus and a control bus.
7
Address Bus
 Consists of 16 address lines: A0 – A15
 Operates in unidirectional mode: The address

bits are always sent from the MPU to peripheral
devices, not reverse.
 16 address lines are capable of addressing a

total of 216 = 65,536 (64k) memory locations.
 Address locations: 0000 (hex) – FFFF (hex)
8
Data Bus
 Consists of 8 data lines: D0 – D7
 Operates in bidirectional mode: The data bits are
sent from the MPU to peripheral devices, as well
as from the peripheral devices to the MPU.
 Data range: 00 (hex) – FF (hex)
Control Bus
 Consists of various lines carrying the control
signals such as read / write enable, flag bits.
9
The 8085: CPU Internal Structure
The internal architecture of the 8085 CPU is

capable of performing the following operations:
 Store 8-bit data (Registers, Accumulator)
 Perform arithmetic and logic operations (ALU)
 Test for conditions (IF / THEN)
 Sequence the execution of instructions

 Store temporary data in RAM during execution
10
Simplified block diagram
11
The 8085: Registers
12
Registers
 Six general purpose 8-bit registers: B, C, D, E, H, L
 They can also be combined as register pairs to

perform 16-bit operations: BC, DE, HL
 Registers are programmable (data load, move, etc.)
Accumulator
 Single 8-bit register that is part of the ALU !
 Used for arithmetic / logic operations – the result is
always stored in the accumulator.
13
Flag Bits
 Indicate the result of condition tests.
 Carry, Zero, Sign, Parity, etc.
 Conditional operations (IF / THEN) are executed

based on the condition of these flag bits.
Program Counter (PC)
 Contains the memory address (16 bits) of the
instruction that will be executed in the next step.
Stack Pointer (SP)
14
Example: Memory Read Operation
15
Example: Instruction Fetch Operation
 All instructions (program steps) are stored in memory.
 To run a program, the individual instructions must

be read from the memory in sequence, and executed.
 Program counter puts the 16-bit memory address of the

instruction on the address bus
 Control unit sends the Memory Read Enable signal to
access the memory
 The 8-bit instruction stored in memory is placed on the data
bus and transferred to the instruction decoder
 Instruction is decoded and executed
16
17
18
8085 Functional Block Diagram
19

Microprocessor 8085 Architecture

Uploaded by

Copyright:

Available Formats

Microprocessor 8085 Architecture

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Microprocessor 8085 Architecture

Uploaded by

Copyright:

Available Formats

Basic Processor Architecture

CPU: Core of the processor, where instructions are executed

I/O devices: Enable system to interact with the world

 Operates in unidirectional mode: The address

 16 address lines are capable of addressing a

 Address locations: 0000 (hex) – FFFF (hex)

 Data range: 00 (hex) – FF (hex)

The internal architecture of the 8085 CPU is

 Store 8-bit data (Registers, Accumulator)

 Perform arithmetic and logic operations (ALU)

 Test for conditions (IF / THEN)

 Sequence the execution of instructions

Simplified block diagram

 They can also be combined as register pairs to

 Carry, Zero, Sign, Parity, etc.

 Conditional operations (IF / THEN) are executed

 All instructions (program steps) are stored in memory.

 To run a program, the individual instructions must

 Program counter puts the 16-bit memory address of the

You might also like

Pfad - The Proxy pFad of © 2024 Garber Painting. All rights reserved.